Plural Different Bias Control Voltages Provided By Separate Means Patents (Class 330/134)
  • Patent number: 11218117
    Abstract: An amplifier circuit includes: a plurality of amplifiers; a plurality of monitor elements provided for each of the plurality of amplifiers and disposed on a same chip with the corresponding amplifier; and a processor configured to: measure characteristics of each of the plurality of monitor elements; reduce a difference in distortion between a plurality of signals output from the plurality of amplifiers based on the measured characteristics; and compensate for the distortion.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: January 4, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Masayuki Hosoda, Yoichi Kawano, Alexander Nikolaevich Lozhkin
  • Patent number: 10651803
    Abstract: Reducing noise for an amplifier-based system circuit that comprises a first differential input pair and a second differential input pair, a first input stage circuit connected to the first differential input pair, wherein the first input stage is configured with a first transconductance value, a second input stage circuit connected to the second differential input pair, wherein the second input stage is configured with a second transconductance value that is less than the first transconductance value, a transimpedance circuit coupled to the first input stage circuit and the second input stage circuit, and a feedback loop circuit coupled to the transimpedance circuit and to the second differential input pair, wherein the feedback loop circuit is not connected to the first differential input pair.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: May 12, 2020
    Assignee: Texas Instruments Incorporated
    Inventors: Seung Bae Lee, Michael Edwin Butenhoff, Sudhir Nagaraj
  • Patent number: 10587225
    Abstract: A biasing circuit with high current drive capability for fast settling of a biasing voltage to a stacked cascode amplifier is presented. According to a first aspect, the biasing circuit uses transistors matched with transistors of the cascode amplifier to generate a boost current during a transition phase that changes the biasing voltage by charging or discharging a capacitor. The boost current is activated during the transition phase and deactivated when a steady-state condition is reached. According to a second aspect, the biasing circuit uses an operational amplifier in a feedback loop that forces a source node of a cascode transistor of a reference circuit, that is a scaled down replica version of the cascode amplifier, to be at a reference voltage. The high gain and high current capability of the operational amplifier, provided by isolating a high frequency signal processed by the cascode amplifier from the reference circuit, allow for a quick settling of the biasing voltage.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 10, 2020
    Assignee: pSemi Corporation
    Inventors: Jonathan James Klaren, Tero Tapio Ranta
  • Patent number: 10573950
    Abstract: Certain aspects of the present disclosure provide a directional coupler. In certain aspects, the directional coupler generally includes a first inductor and a second inductor wirelessly coupled to the first inductor. In certain aspects, the directional coupler generally includes an input port at a first terminal of the first inductor and a transmitted port at a second terminal of the first inductor. In certain aspects, the directional coupler generally includes a coupled port at a first terminal of the second inductor and an isolated port at a second terminal of the second inductor. In certain aspects, the directional coupler generally includes a first complex impedance component directly coupled to the isolated port and a second complex impedance component directly coupled to the coupled port.
    Type: Grant
    Filed: April 6, 2018
    Date of Patent: February 25, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Haitao Cheng, Zhang Jin, Abbas Abbaspour-Tamijani
  • Patent number: 10466959
    Abstract: A system that includes an automatic volume leveler (AVL) that processes audio data based on audio category and desired volume level. The system may select different settings for audio data associated with different audio sources (e.g., content providers), audio categories (e.g., types of audio data, such as music, voice, etc.), genres, and/or the like. For example, the system may distinguish between music signals and voice signals (e.g., speech) and may apply a first gain curve for the music and a second gain curve for the speech. Additionally or alternatively, the system may distinguish between different genres of music and may apply different gain curves based on the genre. Further, the system may select a gain curve based on a desired volume level. Therefore, output audio data generated by performing AVL may be optimized based on the audio category, audio source, genre, desired volume level, and/or the like.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: November 5, 2019
    Assignee: AMAZON TECHNOLOGIES, INC.
    Inventors: Jun Yang, Zezhang Hou
  • Patent number: 10312863
    Abstract: An amplifying circuit includes a first gain adjusting circuit, a second gain adjusting circuit, a load circuit and a switch module. When the amplifying circuit operates in a first mode, the first gain adjusting circuit receives a first input signal, and generates a first output signal to a second output terminal of the amplifying circuit via the load circuit and the switch module; and when the amplifying circuit operates in a second mode, the second gain adjusting circuit receives a second input signal, and generates a second output signal to a first output terminal of the amplifying circuit via the load circuit and the switch module.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: June 4, 2019
    Assignee: Realtek Semiconductor Corp.
    Inventors: Chia-Jun Chang, Ka-Un Chan
  • Patent number: 10243532
    Abstract: A microprocessor-based ALC (automatic level control) system, for original manufacture or field maintenance and retrofit, providing the stability, reliability and longevity of digital solid state implementation along with ALC characteristics calibrated to one or more programed sets of ALC performance specifications. The ALC system can be embodied as a professional audio ALC amplifier with a purely analog main signal path including an ECA (Electronically Controlled Attenuator) controlled by a highly stable microprocessor-based signal level transducer, an ALC calibrator that can be incorporated into any system, ALC system or ALC-related module thereof, or deployed as stand-alone test equipment, to provide ALC performance and/or automatic recalibration of existing ALC circuitry, compensating components thereof to meet programed ALC performance specifications and thus remedy problems and shortcomings relating to stability, reliability, longevity and/or ALC performance.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: March 26, 2019
    Inventor: David K. Geren
  • Patent number: 10187025
    Abstract: A predictive brownout prevention system may be configured to prevent brownout of an audio output signal. Particularly, the brownout prevention system may be configured to receive information indicative of an amplitude of the audio input signal, receive information indicative of a condition of the power supply, determine from the information indicative of an amplitude of the audio input signal and the information indicative of the condition of the power supply whether a brownout condition exists, and responsive to determining the brownout condition exists, generate the selectable attenuation signal to reduce an amplitude of the audio output signal such that the signal path attenuates the audio input signal or a derivative thereof in order to prevent brownout prior to propagation to the audio output of a portion of the audio input signal having the brownout condition.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 22, 2019
    Assignee: Cirrus Logic, Inc.
    Inventors: Jeffrey Allen May, Anu Chakravarty, John C. Tucker
  • Patent number: 10084420
    Abstract: Provided is a multistage amplifier that can achieve both utilizing in a broad bandwidth and suppressing gain reduction. The multistage amplifier includes a plurality of differential amplifiers which are connected in series; and a direct-current component limiter that cuts off a direct-current component of input signals, in which the direct-current component limiter is disposed between the plurality of differential amplifiers, and in which a transistor size of a first differential amplifier which is disposed immediately after the direct-current component limiter is equal to or greater than a transistor size of a second differential amplifier which is disposed two stages before the direct-current component limiter.
    Type: Grant
    Filed: December 25, 2013
    Date of Patent: September 25, 2018
    Assignee: PANASONIC CORPORATION
    Inventor: Ryo Kitamura
  • Patent number: 9800210
    Abstract: A power amplifier includes: a plurality of FET cells connected in parallel to each other; a plurality of first resistors connected between gate terminals of the plurality of FET cells and grounding terminals respectively; a plurality of second resistors having one ends connected to the gate terminals of the plurality of FET cells respectively and other ends connected to each other; a plurality of capacitors connected in parallel to the plurality of second resistors respectively; and a third resistor connected between a connection point of the other ends of the plurality of second resistors and a power supply terminal, wherein the first resistors have temperature coefficients of resistance greater than those of the second and third resistors and are arranged closer to the corresponding FET cells than the third resistor.
    Type: Grant
    Filed: August 29, 2016
    Date of Patent: October 24, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsuya Kato, Naoki Kosaka, Eri Fukuda, Shigeru Fujiwara, Atsushi Okamura, Kenichiro Chomei
  • Patent number: 9768777
    Abstract: System and method for controlling one or more switches. The system includes a first converting circuit, a second converting circuit, and a signal processing component. The first converting circuit is configured to convert a first current and generate a first converted voltage signal based on at least information associated with the first current. The second converting circuit is configured to convert a second current and generate a second converted voltage signal based on at least information associated with the second current. The signal processing component is configured to receive the first converted voltage signal and the second converted voltage signal and generate an output signal based on at least information associated with the first converted voltage signal and the second converted voltage signal.
    Type: Grant
    Filed: April 2, 2014
    Date of Patent: September 19, 2017
    Assignee: On-Bright Electronics (Shanghai) Co., Ltd.
    Inventors: Chao Yao, Tingzhi Yuan, Qiang Luo, Zhiliang Chen, Lieyi Fang
  • Patent number: 9755585
    Abstract: The present invention provides an RF power amplifier architecture which with dynamic digital control of the amplification by incorporating digitized RF input and output signal envelope data and environmental temperature sensor(s) readings into an arbitrary control algorithm implemented on a digital processor. Via the combination of digitally controlled DC/DC converter and a D/A converter, the quiescent bias of the power FET of the RF output stage can become a realization of virtually any function of the feedback and input data.
    Type: Grant
    Filed: September 6, 2016
    Date of Patent: September 5, 2017
    Assignee: AERO ANTENNA, INC.
    Inventor: Joseph Klein
  • Patent number: 9742077
    Abstract: A system according to one embodiment includes a phased array antenna comprising a plurality of antenna elements, the plurality of antenna elements configured in a planar array, wherein each of the plurality of antenna elements generates a beam pattern directed at an angle out of the plane of the planar array; and driver circuitry coupled to each of the plurality of antenna elements, wherein the driver circuitry comprises a plurality of transceivers, the plurality of transceivers configured to provide independently adjustable phase delay to each of the plurality of antenna elements.
    Type: Grant
    Filed: October 1, 2011
    Date of Patent: August 22, 2017
    Assignee: Intel Corporation
    Inventor: Helen K. Pan
  • Patent number: 9668045
    Abstract: A novel phantom-powered JFET gain circuit that improves audio clarity and linearity, while reducing a high-gain burden, noise, and distortion from a sole usage of a conventional preamplifier, is disclosed. In one embodiment, the novel phantom-powered JFET gain circuit is encased as a standalone box that connects to a microphone on one end and a conventional preamplifier unit or another conventional audio processing unit on another end. In another embodiment, the novel phantom-powered JFET gain circuit is integrated into a portable electronic device or another consumer electronic device with a microphone to provide an earliest-stage gain in a microphone-captured audio signal processing pathway. Yet in another embodiment, the novel phantom-powered JFET gain circuit is integrated into a preamplifier unit and provides the earliest-stage gain in a microphone-captured audio signal processing pathway, prior to additional and conventional signal amplification by the preamplifier unit.
    Type: Grant
    Filed: September 13, 2015
    Date of Patent: May 30, 2017
    Inventor: Rodger Cloud
  • Patent number: 9577583
    Abstract: A power amplifier may include a first amplifying unit receiving a first bias signal to amplify a power level of an input signal; an envelope detecting unit detecting an envelope of the input signal; a comparing circuit unit comparing a peak value of the detected envelope with a preset reference voltage; and a second amplifying unit amplifying the power level of the input signal according to a second bias signal set depending on a comparison result of the comparing circuit unit.
    Type: Grant
    Filed: May 8, 2014
    Date of Patent: February 21, 2017
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Kwang Du Lee, Jeong Hoon Kim, Ho Kwon Yoon, Joong Jin Nam, Kyu Jin Choi, Suk Chan Kang, Jae Hyouck Choi, Kyung Hee Hong
  • Patent number: 9571040
    Abstract: An audio amplifier is provided with: an amplifier circuit; a power supply circuit that generates a plurality of power supply voltages; a power supply relay that selects one of the power supply voltages as the power supply voltage supplied to the amplifier circuit; a switching condition determiner that determines whether the switching condition of the power supply relay is satisfied; a silent section detector that detects a silent section of the audio signal which is equal to or greater than the operation time of the power supply relay; and a switching instruction unit for providing the power supply relay with an instruction for switching the power supply voltage during the silent section when the switching condition is satisfied and the silent section is detected.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 14, 2017
    Assignee: Yamaha Corporation
    Inventor: Morito Yamada
  • Patent number: 9437200
    Abstract: A method and computing system for suppressing noise in an audio signal, comprising: receiving the audio signal at signal processing means; determining that another signal is input to the signal processing means, the input signal resulting from an activity which generates noise in the audio signal; and selectively suppressing noise in the audio signal in dependence on the determination that the input signal is input to the signal processing means to thereby suppress the generated noise in the audio signal.
    Type: Grant
    Filed: July 7, 2014
    Date of Patent: September 6, 2016
    Assignee: Skype
    Inventors: Karsten Vandborg Sorensen, Jon Anders Bergenheim, Koen Bernard Vos
  • Patent number: 9124316
    Abstract: A transmit circuit includes an envelope tracker configured to determine an envelope of a transmit signal and provide bias information based on the determined envelope of the transmit signal. The transmit circuit further includes a power amplifier configured to generate an RF output signal based on the transmit signal, a bias provider configured to provide a bias for the power amplifier based on the bias information, and an impedance determinator configured to determine a measure of a load impedance of a load coupled to an output of the power amplifier. The envelope tracker is configured to adapt the bias information based on the measure of the load impedance.
    Type: Grant
    Filed: May 9, 2014
    Date of Patent: September 1, 2015
    Assignee: Intel Mobile Communications GmbH
    Inventor: Andreas Langer
  • Patent number: 8843180
    Abstract: Embodiments for at methods, apparatus and systems for operating a voltage regulator are disclosed. One apparatus includes a switching voltage regulator, wherein the switching voltage regulator includes a series switch element, a shunt switch element, a switching controller and a switched output filter. The switching controller is configured to generate a switching voltage through controlled closing and opening of the series switch element and the shunt switch element. The switched output filter filters the switching voltage and generates a regulated output voltage, wherein the switched output filter includes a plurality of capacitors that are selectively included within the switched output filter.
    Type: Grant
    Filed: June 5, 2013
    Date of Patent: September 23, 2014
    Assignee: R2 Semiconductor, Inc.
    Inventors: James E. C. Brown, Daniel Dobkin, Pablo Moreno Galbis, Cory Severson, Lawrence M. Burns
  • Publication number: 20140043098
    Abstract: The present application discloses various implementations of a mobile device including a power amplifier (PA) having a driving stage coupled to an output stage. The driving stage is configured to be selectably powered by one of a first voltage supply and a second voltage supply. The output stage is configured to be powered by the second voltage supply. The mobile device further includes a voltage supply selection switch configured to selectably power the driving stage by the second voltage supply when an output power of the PA is less than or equal to a threshold power.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 13, 2014
    Applicant: BROADCOM CORPORATION
    Inventor: Dmitriy Rozenblit
  • Patent number: 8542064
    Abstract: Methods and apparatus to control power in a printer are disclosed. An example apparatus includes a first field effect transistor having a first terminal, a second terminal, and a third terminal, the second terminal coupled with a first voltage input. The example apparatus further includes a second field effect transistor having a fourth terminal, a fifth terminal, and a sixth terminal, the fourth terminal coupled with the first terminal of the first field effect transistor, the fifth terminal coupled with a second voltage input. The example apparatus further includes a first comparator having a first input coupled to the first input voltage, having a second input coupled to the second input voltage, and having an output coupled with the third terminal.
    Type: Grant
    Filed: October 31, 2011
    Date of Patent: September 24, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Barley Mark Hirst
  • Patent number: 8339204
    Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.
    Type: Grant
    Filed: April 25, 2011
    Date of Patent: December 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Shimizu, Yoshikuni Matsunaga, Yuri Kusakari
  • Patent number: 8335478
    Abstract: Provided are a first filter 63a and a second filter 63b each having a pass band in the range of a frequency band that is obtained by, for example, substantially bisecting a frequency band of f1 to f4. In that case, the regions of the first filter 63a and the second filter 63b partially overlap with each other with the center frequency f5 interposed therebetween. In practice, even if the division is not bisection, a configuration is adopted in which a frequency region of the wider band (the first frequency band 61a) closer to a second frequency band 61b side is covered by the second filter 63b. Accordingly, it is possible to suppress the influence of load fluctuation in a multiband-compatible radio communication device.
    Type: Grant
    Filed: July 30, 2008
    Date of Patent: December 18, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroki Kashiwagi
  • Patent number: 8159294
    Abstract: The present invention discloses a multi-voltage headphone driver circuit comprising: at least one operational amplifier having an output supplied to a headphone speaker, the operational amplifier receiving a first power supply as its high operation voltage; a charge pump receiving a second power supply to generate a negative voltage corresponding to the second power supply in magnitude; and an m-fold circuit multiplying the negative voltage by m and providing the result to the operational amplifier as a low operation voltage thereof, wherein m is a real number.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: April 17, 2012
    Assignee: Richtek Technology Corporaton
    Inventors: Jwin-Yen Guo, Ching-Hsiang Yang
  • Patent number: 8106709
    Abstract: An electronic circuit includes a first variable gain amplifier for amplifying a signal at an input to provide a first amplified signal; a filter receiving the first amplified signal to provide a filtered signal; a second variable gain amplifier for receiving and amplifying the filtered signal; a second gain control bock, to provide at least one gain control signal derived from the filtered signal, one of the at least one gain control signal to control the gain of the second variable gain amplifier; and a bounding block for receiving one of the at least one gain control signal from the second gain control block, and for generating therefrom a bounded gain control signal to control gain of the first variable gain amplifier.
    Type: Grant
    Filed: December 3, 2009
    Date of Patent: January 31, 2012
    Inventors: Steve Selby, Fung Ling Chiu, Gary Cheng
  • Patent number: 8081777
    Abstract: An audio amplifier such as for driving headphones. The amplifier includes multiple amplifier devices coupled in parallel. Both a bias generator and a volume control are responsive to a user setting. Under low output signal conditions, one or more of the amplifier devices are disabled in response to the user setting. Disabled amplifier devices do not consume output bias current. Thus the audio amplifier has reduced power consumption, and the system has longer battery life.
    Type: Grant
    Filed: March 20, 2007
    Date of Patent: December 20, 2011
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Brian B. North
  • Patent number: 7952434
    Abstract: Power amplifier circuits which constitute an RF power module used for a digital device capable of handling high frequency signals in two frequency bands are disposed over the same IC chip. The power amplifier circuits are disposed around the IC chip, and a secondary circuit is disposed between the power amplifier circuits. Thus, the power amplifier circuits are provided within the same IC chip to enable a size reduction. Further, the distance between the power amplifier circuits is ensured even if the power amplifier circuits are provided within the same IC chip. It is therefore possible to suppress the coupling between the power amplifier circuits and restrain crosstalk between the power amplifier circuits.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: May 31, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Toshihiko Shimizu, Yoshikuni Matsunaga, Yuri Kusakari
  • Patent number: 7719354
    Abstract: A dynamic biasing system (“DBS”) for dynamically biasing an amplifier with an adjusted bias signal is shown. The DBS may include a first biasing circuit that produces a bias signal and a second biasing circuit in signal communication with both the first biasing circuit and the amplifier, wherein the second biasing circuit compares the bias signal to a predetermined threshold and in response produces the adjusted bias signal.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: May 18, 2010
    Assignee: Skyworks Solutions, Inc.
    Inventor: Nicolas Constantin
  • Patent number: 7647044
    Abstract: The present disclosure relates to a switching device having a display that allows an operator to readily visually assess the signal strength of both a primary signal and a back-up signal. In certain embodiments, the information relating to the signal strength of the primary and back-up signal is provided on a graphic display. In certain other embodiments, the signal strength of the back-up signal is displayed relative to the signal strength of the primary signal.
    Type: Grant
    Filed: August 21, 2006
    Date of Patent: January 12, 2010
    Assignee: ATX Networks Corp.
    Inventors: Brian Tamminen, Todd Loeffelholz
  • Patent number: 7629851
    Abstract: In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient ? due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: December 8, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Hirokazu Tsurumaki, Hiroyuki Nagai, Tomio Furuya, Makoto Ishikawa
  • Patent number: 7629853
    Abstract: An amplifying apparatus including an amplifier having a first FET, a second FET having a source connected to a drain of the first FET, a load resistance connected to a drain of the second FET, a first bias circuit configured to supply a first bias voltage to a gate of the first FET, and a second bias circuit configured to supply a second bias voltage to a gate of the second FET. The second bias circuit includes a second comparison circuit configured to send a control signal to the gate of the second FET so that a bias voltage of a connection node between the first and second FETs changes in conjunction with an output voltage of the first bias circuit.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: December 8, 2009
    Assignee: Fujitsu Limited
    Inventor: Kazuaki Oishi
  • Patent number: 7554395
    Abstract: An amplification circuit and scaling method are configured to apply optimum biasing characteristics such that a multistage power amplifier operates according to defined performance characteristics. The operating conditions of the multistage amplifier are optimized by applying independent bias voltages to each stage within the multistage amplifier while operating in a maximum power output range. To achieve optimum or near-optimum operating conditions, each bias voltage is independently scaled according to a specific power output level.
    Type: Grant
    Filed: June 28, 2007
    Date of Patent: June 30, 2009
    Assignee: Panasonic Corporation
    Inventor: Christian Pennec
  • Patent number: 7512387
    Abstract: A system for controlling a power supplied to a load from a radio frequency amplifier system includes a radio frequency signal generator adapted for generating a radio frequency signal, an amplifier to which the radio frequency signal is supplied and that amplifies the radio frequency signal into a radio frequency power signal, a power coupler connected to the amplifying member for coupling the radio frequency power signals, where the power coupler includes a summing connection adapted for connection to the load and a compensating connection adapted for connection to a dissipative element. A first control value generating member is adapted for receiving a signal proportional to a power output from the power coupler at the summing connection and is adapted for generating a first control signal for controlling the amplifier or a current supply that supplies current to the amplifier.
    Type: Grant
    Filed: May 17, 2005
    Date of Patent: March 31, 2009
    Assignee: Huettinger Elektronik GmbH + Co. KG
    Inventor: Michael Glueck
  • Patent number: 7499502
    Abstract: An amplifier includes a modulation coder receiving an original modulation signal and generating an amplitude signal and a phase signal, a voltage adjusting instrument which generates an amplitude modulation signal from the amplitude signal, a carrier generator generating a phase modulation signal from the phase signal, and an amplification device receiving the phase modulation signal and the amplitude modulation signal serving as a bias voltage and outputting a modulation signal obtained by restoring and amplifying the original modulation signal. The voltage adjusting instrument determines a DC offset voltage on the basis of a level control signal indicating the level of the amplitude modulation signal and generates the amplitude modulation signal to which the DC offset voltage is added.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: March 3, 2009
    Assignee: Panasonic Corporation
    Inventors: Shigeru Morimoto, Hisashi Adachi, Toru Matsuura
  • Publication number: 20090002068
    Abstract: A dynamic biasing system (“DBS”) for dynamically biasing an amplifier with an adjusted bias signal is shown. The DBS may include a first biasing circuit that produces a bias signal and a second biasing circuit in signal communication with both the first biasing circuit and the amplifier, wherein the second biasing circuit compares the bias signal to a predetermined threshold and in response produces the adjusted bias signal.
    Type: Application
    Filed: July 1, 2008
    Publication date: January 1, 2009
    Inventor: Nicolas Constantin
  • Patent number: 7443245
    Abstract: In a high frequency power amplifier circuit that supplies a bias to an amplifying FET by a current mirror method, scattering of a threshold voltage Vth due to the scattering of the channel impurity concentration of the FET, and a shift of a bias point caused by the scattering of the threshold voltage Vth and a channel length modulation coefficient ? due to a short channel effect are corrected automatically. The scattering of a high frequency power amplifying characteristic can be reduced as a result.
    Type: Grant
    Filed: October 26, 2007
    Date of Patent: October 28, 2008
    Assignee: Renesas Technology Corporation
    Inventors: Hirokazu Tsurumaki, Hiroyuki Nagai, Tomio Furuya, Makoto Ishikawa
  • Patent number: 7405617
    Abstract: A dynamic biasing system (“DBS”) for dynamically biasing an amplifier with an adjusted bias signal is shown. The DBS may include a first biasing circuit that produces a bias signal and a second biasing circuit in signal communication with both the first biasing circuit and the amplifier, wherein the second biasing circuit compares the bias signal to a predetermined threshold and in response produces the adjusted bias signal.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: July 29, 2008
    Assignee: Skyworks Solutions, Inc.
    Inventor: Nicolas Constantin
  • Publication number: 20080175335
    Abstract: Provided is a transmission circuit which is capable of compensating for an offset voltage and a sensitivity characteristic of a PA, and operating with low distortion and high efficiency. A regulator 18 supplies, to a PA 201, a voltage which is controlled in accordance with an amplitude signal to which a first offset value has been added. A regulator 19 supplies, to a PA 202, a voltage which is controlled in accordance with an amplitude signal to which a second offset value has been added. The PA 201 amplifies, in accordance with the voltage supplied from the regulator 18, a phase-modulated signal outputted from a phase modulator 13. The PA 202 amplifies, in accordance with the voltage supplied from the regulator 19, an output signal of the PA 201. A digital block 11 controls the first and second offset values in accordance with temperature information T measured by a temperature measuring section 21.
    Type: Application
    Filed: January 22, 2008
    Publication date: July 24, 2008
    Inventors: Shigeru Morimoto, Kaoru Ishida
  • Patent number: 7378881
    Abstract: Embodiments of a variable gain amplifier circuit are described. In one embodiment, multiple resistor devices are coupled in series to form a string of resistor devices and to receive an input current. A multiple input operational amplifier device has an amplifier output coupled to a feedback resistor in the string of resistor devices and multiple amplifier input pairs, each amplifier input being coupled into the string of resistor devices as a tap between two respective adjacent resistors, each amplifier input pair being controlled by a corresponding bias current transmitted from a respective bias current source.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: May 27, 2008
    Inventor: Ion E. Opris
  • Patent number: 7355477
    Abstract: A low cost, robust method and apparatus for controlling the gain of a power amplifier to compensate for changes that are gradual with time. The bias circuit of a power amplifier is sent one of three signals in response to a measurement of the average output power level of the power amplifier. If the average output power lever is less than a desired value, a signal to increment the bias current by a set amount is sent, so that the output power increases. If the average output power lever is more than the desired value, a signal to decrement the bias current by a set amount is sent. A third signal may be sent that causes the bias circuit to reset to a default value. The three signals may be sent as a two bit digital signal.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: April 8, 2008
    Assignee: Agere Systems Inc.
    Inventors: Syed Aon Mujtaba, Edward E. Campbell
  • Publication number: 20080074184
    Abstract: An amplifier arrangement with controllable gain includes a first and a second amplifier device which each have a control input to receive a control signal to adjust a gain factor of the respective amplifier device. A control device is provided which is coupled to the second amplifier device to derive an effective gain factor of the second amplifier device as a function of the control signal. The control device further includes a control output coupled to the respective control inputs of the first and the second amplifier device to provide the control signal depending on a desired gain factor and the effective gain factor.
    Type: Application
    Filed: September 27, 2006
    Publication date: March 27, 2008
    Inventors: Hans Pletzer, Werner Schelmbauer, Harald Pretl
  • Patent number: 7345537
    Abstract: A power amplifier stage has a first amplifier subsection and a second amplifier subsection coupled in a parallel configuration. The first amplifier subsection receives a signal to be amplified and the second amplifier subsection receives the signal to be amplified via a first delay line. The amplified output signal of the first amplifier subsection is passed through a second impedance inverter and is combined with the amplified output signal from the second amplifier subsection. In a low power mode, the first amplifier subsection operates as a linear amplifier and the second subsection is biased off. In a high power mode, both the first and second amplifier subsections operate as linear amplifiers. Selecting the impedances of the second delay element and the first amplifier to be equal is essential for high power mode operation and greatly improves the amplifier efficiency in the low power mode.
    Type: Grant
    Filed: September 19, 2003
    Date of Patent: March 18, 2008
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Thomas R. Apel, Tarun Juneja
  • Patent number: 7227415
    Abstract: Providing a high frequency power amplifier circuit and a radio communication system which can control output power by a power voltage, produce sufficient output power in high regions of demanded output power and improve power efficiency in low regions of demanded output power. In a high frequency power amplifier circuit (RF power module) which comprises two or more cascaded FETs for amplification and controls output power by controlling power voltages of the FETs for amplification to gate terminals of which bias voltages of a predetermined level are applied, different transistors for power voltage control are provided for a last-stage FET for amplification and preceding-stage FETs for amplification. The transistors for power voltage control generate and apply the power voltage so that the preceding-stage FETs for amplification saturate when a demanded output level is relatively low.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: June 5, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Tahara, Takayuki Tsutsui, Tetsuaki Adachi
  • Patent number: 7199657
    Abstract: An amplification apparatus is provided that includes a plurality of gain stages including a first gain stage having first and second transistors and a second gain stage having third and fourth transistors. A plurality of replica stages may also be provided that includes a first replica stage and a second replica stage. Each replica stage may correspond/match one of the plurality of gain stages. An amplifying device may be provided to adjust a body potential of at least the first transistor of the first gain based on an output of the first replica stage and an output of the second replica stage.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: April 3, 2007
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, Vivek K. De
  • Patent number: 7193459
    Abstract: A power amplifier configuration including power amplifier circuitry and power control circuitry and having improved Power Added Efficiency (PAE) is provided. The power amplifier circuitry includes one or more input amplifier stages in series with a final amplifier stage. The power control circuitry provides a variable supply voltage to the input amplifier stages based on an adjustable power control signal. The final amplifier stage is powered by a fixed supply voltage. In operation, as output power of the power amplifier is reduced from its highest power level, the variable supply voltage is reduced. Accordingly, RF power of an amplified signal provided to the final amplifier stage from the input amplifier stages decreases, and the final amplifier stage transitions from saturation to linear operation, thereby increasing the gain of the final amplifier stage. Thus, a desired output level can be maintained while operating at lower current levels.
    Type: Grant
    Filed: June 23, 2004
    Date of Patent: March 20, 2007
    Assignee: RF Micro Devices, Inc.
    Inventors: Darrell G. Epperson, Carlos Gamero, Ryan Bosley, Joel R. Gibson, Michael LaBelle, Scott Yoder
  • Patent number: 7167718
    Abstract: A transmission power control apparatus for a wireless communication apparatus which reduces a power value of a signal input to a power amplifier to the maximum allowable input power value of the power amplifier or below is provided in which the transmission power control apparatus includes: a part for setting a transmission power upper limit value of a call according to a circuit type of the call; and a part for reducing transmission power for the call to the transmission power upper limit value or below.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: January 23, 2007
    Assignee: NTT DoCoMo, Inc.
    Inventors: Takahiro Hayashi, Yoshihiro Ishikawa, Seizo Onoe, Takehiro Nakamura, Mikio Iwamura, Yoshiaki Ofuji
  • Patent number: 7123094
    Abstract: Providing a high frequency power amplifier circuit and a radio communication system which can control output power by a power voltage, produce sufficient output power in high regions of demanded output power and improve power efficiency in low regions of demanded output power. In a high frequency power amplifier circuit (RF power module) which comprises two or more cascaded FETs for amplification and controls output power by controlling power voltages of the FETs for amplification to gate terminals of which bias voltages of a predetermined level are applied, different transistors for power voltage control are provided for a last-stage FET for amplification and preceding-stage FETs for amplification. The transistors for power voltage control generate and apply the power voltage so that the preceding-stage FETs for amplification saturate when a demanded output level is relatively low.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: October 17, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Kenji Tahara, Takayuki Tsutsui, Tetsuaki Adachi
  • Patent number: 7109791
    Abstract: A system is provided for substantially reducing variation in AM to PM distortion of a power amplifier caused by variations in RF drive power and temperature. The system includes power control circuitry and power amplifier circuitry. The power amplifier circuitry includes an input amplifier stage and at least one additional amplifier stage coupled in series with the input amplifier stage. The power control circuitry provides a first supply voltage to the input amplifier stage based on a control signal such that the first supply voltage has a predetermined DC offset with respect to the control signal. The first supply voltage is provided such that the predetermined DC offset substantially reduces variations in the AM to PM distortion of the power amplifier due to variations in radio frequency (RF) drive power.
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: September 19, 2006
    Assignee: RF Micro Devices, Inc.
    Inventors: Darrell G. Epperson, Ryan Bosley
  • Patent number: 7098732
    Abstract: A multi-stage variable gain amplifier is disclosed that utilizes overlapping gain curves to compensate for log-linear errors. Each gain stage is configured to approximate a log-linear response with a sinusoidal error term such that a portion of the curve has positive errors and a portion of the curve has negative errors. In operation, the control signal inputs for the gain stages are driven such that the gain curves overlap and positive errors in each stage are offset by negative errors in the adjacent stage. The resulting combined gain is a more log-linear response.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: August 29, 2006
    Assignee: Silicon Laboratories Inc.
    Inventor: Scott T. Dupuie
  • Patent number: 7071782
    Abstract: A device for amplifying or attenuating HF signals is characterized in that a transistor is connected in a common-emitter configuration in amplifying operation, and a base-collector diode is connected in the forward-biased direction for attenuating operation.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: July 4, 2006
    Assignee: NEC Electronics (Europe) GmbH
    Inventor: Ulrich Delpy