Amplitude Limiting Or Bias Voltage Patents (Class 330/135)
  • Patent number: 11984921
    Abstract: Provided are a supply modulator and a wireless communication apparatus including the same. A supply modulator according to the inventive concept is driven in any one of an average power tracking mode and a discrete level envelope tracking mode to apply an output voltage to a power amplifier, and includes a multiple output voltage balancer, a switching regulator, a switching regulator controller, a switch array, a discrete-level controller, a switch controller, an output filter, and a main controller.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: May 14, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongsu Kim, Junsuk Bang
  • Patent number: 11711022
    Abstract: Various embodiments are directed to a switch circuit comprising: two terminal nodes, comprising an upper node and a lower node; a plurality of switch modules, connected in series between the upper node and the lower node, wherein each of the switch modules comprises a switch, a rectifier, and a capacitor; a connecting circuit, coupled to the switch modules; and a power converter, coupled to the connecting circuit and to a power sink. The switch circuit is configured to limit a voltage or a component of a voltage in the switch circuit, and to recover power from the limiting of the voltage, wherein recovering the power comprises diverting power from the switch modules via the connecting circuit to the power converter, and the power converter outputting the power to the power sink.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: July 25, 2023
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Gideon Van Zyl
  • Patent number: 11705822
    Abstract: Various embodiments are directed to a voltage clamp system comprising: a rectifier; a protected node, a reference node, and one or more internal nodes, coupled to the rectifier; a power converter, coupled to the rectifier via the one or more internal nodes; and one or more output nodes coupled to the power converter and configured to couple to a power sink. The rectifier and the power converter are configured to output power via one or more output nodes coupled to the rectifier, and to limit a component of the voltage between the protected node and the reference node.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: July 18, 2023
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Gideon Van Zyl
  • Patent number: 11652501
    Abstract: Provided are a supply modulator and a wireless communication apparatus including the same. A supply modulator according to the inventive concept is driven in any one of an average power tracking mode and a discrete level envelope tracking mode to apply an output voltage to a power amplifier, and includes a multiple output voltage balancer, a switching regulator, a switching regulator controller, a switch array, a discrete-level controller, a switch controller, an output filter, and a main controller.
    Type: Grant
    Filed: October 18, 2021
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Dongsu Kim, Junsuk Bang
  • Patent number: 10924069
    Abstract: According to an embodiment, a method includes amplifying a signal provided by a capacitive signal source to form an amplified signal, detecting a peak voltage of the amplified signal, and adjusting a controllable impedance coupled to an output of the capacitive signal source in response to detecting the peak voltage. The controllable impedance is adjusted to a value inversely proportional to the detected peak voltage.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: February 16, 2021
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Michael Kropfitsch, Jose Luis Ceballos
  • Patent number: 10855234
    Abstract: A power amplifier includes an output signal generator constructed to generate, on the basis of an input AC signal, an output signal including, in cycles, a first pulse being width higher in voltage than a first reference voltage and a second pulse being width lower in voltage than the first reference voltage and a feedback circuit constructed to generate a first bias signal corresponding to the output signal and feed back the first bias signal to an input side of the output signal generator to equalize a width of the first pulse and a width of the second pulse in the cycles of the output signal.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: December 1, 2020
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventor: Tong Wang
  • Patent number: 10630324
    Abstract: Certain aspects of the present disclosure generally relate to apparatus and techniques for wireless communication. One example apparatus generally includes an antenna terminal, an amplifier, a matching network coupled between the antenna terminal and an output of the amplifier, a first voltage envelope detector coupled to a node between the antenna and the matching network, and a current detection circuit coupled to the amplifier.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Summers, Chi-Fung Kwok, Oleg Popov, Bahareh Siasi, William Daniel Connolley
  • Patent number: 10284144
    Abstract: An amplifier circuit includes an input stage, having a positive input end and a negative a negative input end, for generating a pair of differential signals according to a first input voltage received from the positive input end and a second input voltage received from a negative input end; an output stage, coupled to the input stage for generating an output voltage at an output end according to the pair of differential signals; a feedback stage, coupled between the output end and the negative input end; and a clamping unit, coupled between the positive input end and the negative input end for adjusting the second input voltage when the first input voltage is varied so as to clamp a voltage difference between the first input voltage and second input voltage.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 7, 2019
    Assignee: NOVATEK Microelectronics Corp.
    Inventor: Hsiang-Yi Chiu
  • Patent number: 10153732
    Abstract: An amplifier circuit and a method of recovering an input signal in the amplifier circuit are provided. The amplifier circuit may recover an input signal by using a time constant and an output signal of a signal amplifier which is delayed by a certain period, based on characteristics of an inverse Laplace transform of a transfer function of the signal amplifier. A time required for recovering the input signal may be shorter than the time constant of the signal amplifier.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: December 11, 2018
    Assignees: SAMSUNG ELECTRONICS CO., LTD., KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Insu Jeon, Jhinhwan Lee, Hwansoo Suh
  • Patent number: 10148227
    Abstract: Circuitry that includes a radio frequency (RF) power amplifier (PA) and a dynamic supply boosting circuit, is disclosed. The RF PA receives and amplifies an RF input signal to provide an RF transmit signal using a PA power supply voltage. The dynamic supply boosting circuit provides the PA power supply voltage using a dynamic supply input voltage, wherein when a peak-to-average (PAR) of the RF input signal exceeds a PAR threshold, the dynamic supply boosting circuit boosts the PA power supply voltage, such that the PA power supply voltage is greater than the dynamic supply input voltage.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: December 4, 2018
    Assignee: Qorvo US, Inc.
    Inventors: Dirk Robert Walter Leipold, Baker Scott, George Maxim, David Reed
  • Patent number: 9344304
    Abstract: A switching apparatus comprises a number of instantiations of switching load cells operating at a first voltage and at a second voltage to switch a digital structure. The instantiations are turned on by a respective control bits. Each load cell comprises a charging capacitor coupled to a power amplifier. An output node can be coupled to a load capacitance. Switching circuitry couples the charging capacitor to the load capacitance and connects a voltage regulator to the output node to regulate voltage to the second voltage. The timing logic couples the charging capacitor to the first voltage, couples the charging capacitor to the load capacitance and disconnects the first voltage from the charging capacitor during a switching event, disconnects the charging capacitor from the load capacitance and connects the voltage regulator to the output node after the switching event. The apparatus may be embodied in envelope tracking.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: May 17, 2016
    Assignee: Intel IP Corporation
    Inventor: Emanuel Cohen
  • Patent number: 9184705
    Abstract: A method and an amplifier for amplifying audio signals include a signal processor for processing incoming audio samples in preparation for amplification by an electronic amplifier circuit. A voltage is received from a power supply. Before the signal processor completes processing the incoming audio samples, an input level is estimated based on the incoming audio samples. In response to a comparison between the estimated input level and a threshold value, it is determined whether to boost the voltage received from the power supply. After the signal processor completes processing the incoming audio samples, an output level is estimated based on the processed audio samples. A determination is made, in response to the estimated output level, whether to adjust the threshold value used to determine whether to boost the voltage received from the power supply.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: November 10, 2015
    Assignee: Bose Corporation
    Inventors: Shiufun Cheung, Jay Solomon
  • Patent number: 9037102
    Abstract: Aspects of the disclosure provide a circuit that includes a first circuit, a second circuit, and an adder. The first circuit is configured to generate a first signal by outputting and holding, at a first timing, a first stream in response to an input stream of data. The second circuit is configured to generate a second signal by outputting and holding, at a second timing, a second stream in response to the input stream of data. The adder is configured to add the first signal with the second signal to generate an up-sampled stream for the input stream of data and reduce a frequency component in the up-sampled stream generated by the up-sampling.
    Type: Grant
    Filed: July 10, 2013
    Date of Patent: May 19, 2015
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: Qiang Li, Brian T. Brunn
  • Patent number: 8831138
    Abstract: The circuit is provided for the transmission of data amplitude modulated radio frequency signals. The circuit includes a local oscillator for generating an oscillating signal at a determined carrier frequency, a unit for shaping data pulses to supply a data amplitude modulation control signal (Vmod), and a power amplifier receiving the oscillating signal and the data amplitude modulation control signal (Vmod) for the transmission of data amplitude modulated radio frequency signals by an antenna or an antenna arrangement. The data pulse shaping unit (13) includes a pulse shaper (21) for digitally adapting the data transition edges on the basis of an incoming digital data signal (d), and a digital-analog conversion stage (26, 27) for converting a digital data signal shaped in the unit, in order to supply the data amplitude modulation control signal (Vmod) to the power amplifier.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: September 9, 2014
    Assignee: EM Microelectronic-Marin SA
    Inventor: Michel Moser
  • Patent number: 8781414
    Abstract: An envelope detector includes an input receiving a digital input signal indicative of a magnitude of a signal to be amplified by a power amplifier. A circuit is provided for generating an analog envelope signal based on the digital input signal. The envelope detector includes an output for outputting the analog envelope signal.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: July 15, 2014
    Assignee: Intel Mobile Communications GmbH
    Inventors: Krzysztof Dufrene, Harald Pretl, Patrick Ossmann
  • Publication number: 20140065990
    Abstract: Various embodiments described herein relate to a power management block and one or more amplification blocks used in the transmitter of a communication subsystem. The power management block provides improved control for the gain control signal provided to a pre-amplifier and the supply voltage provided to a power amplifier, both of which are included in a selected one of the amplification blocks. The power expended by the power amplifier is optimized by employing a continuous control method in which one or more feedback loops are employed to take into account various characteristics of the transmitter components and control values. Post power amplifier transmission power is detected for input into the one or more feedback loops executed in the power management block. A controller for the power amplifier is design to stabilize the system with respect to gain expansion in the power amplifier.
    Type: Application
    Filed: November 11, 2013
    Publication date: March 6, 2014
    Applicant: BlackBerry Limited
    Inventors: Wen-Yen Chan, Nasserullah Khan, Ian Ka Yin Chung, Hamza Mohaimeen Bari
  • Patent number: 8624670
    Abstract: A digital pre-distortion system and method are provided. The method includes performing a digital pre-distortion operation; and limiting an input of the power amplifier to be no greater than a limit threshold.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Electronics Co., Ltd
    Inventor: Young-Yoon Woo
  • Publication number: 20130241644
    Abstract: The present invention discloses a dynamic power control method utilized in an amplifier. The dynamic power control method includes detecting an absolute difference between a positive supply voltage of the amplifier and an output voltage of the amplifier, to acquire a positive voltage difference; detecting an absolute difference between a negative supply voltage of the amplifier and the output voltage of the amplifier, to acquire a negative voltage difference; and adjusting the positive supply voltage and the negative supply voltage according to the positive voltage difference, the negative voltage difference and a threshold.
    Type: Application
    Filed: June 27, 2012
    Publication date: September 19, 2013
    Inventors: Wen-Yen Chen, Ming-Hung Chang
  • Patent number: 8466755
    Abstract: Provided is a Polar modulation apparatus which compensates for output characteristics of a power amplifier. A data generator generates an amplitude component signal and a phase component signal. A phase modulator generates a phase modulated signal obtained by phase modulating the phase component signal. An adder adds an amplitude offset voltage to the amplitude component signal. A power amplifier which includes a first hetero-junction bipolar transistor, amplifies the phase modulated signal by using the amplitude component signal. A monitor unit monitors the power amplifier and outputs a monitor voltage. The control unit calculates the amplitude offset voltage according to the monitor voltage and outputs the calculated amplitude offset voltage to the adder. The monitor unit includes a second hetero-junction bipolar transistor and outputs a collector emitter voltage of the second hetero-junction bipolar transistor as the monitor voltage.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: June 18, 2013
    Assignee: Panasonic Corporation
    Inventor: Yoshihiro Hara
  • Patent number: 8432219
    Abstract: An amplitude control system including one or more multi-element array power amplifiers (MEA-PA), each MEA-PA including multiple amplifiers, multiple capacitors, and multiple enable circuits. Each amplifier has an input coupled to a common input node and an output coupled to a corresponding one of multiple intermediate nodes. Each capacitor has a first end coupled to an output node and a second end coupled to a corresponding intermediate node. The enable circuits are collectively controlled by an amplitude control value, and each is operative to enable or disable a corresponding amplifier. The enable circuits may be dynamically controlled to modulate amplitude. A coupling circuit may be provided to couple an intermediate node to a reference node when a corresponding amplifier is disabled to adjust a coupling ratio. Each amplifier, when enabled, may receive one of multiple supply reference voltages. The capacitors may have equal capacitance or may be binary-weighted.
    Type: Grant
    Filed: October 6, 2011
    Date of Patent: April 30, 2013
    Assignee: Passif Semiconductor Corp.
    Inventor: Benjamin W. Cook
  • Patent number: 8422698
    Abstract: A signal processing apparatus includes: clip detector means that detects presence/absence of a clipped part with a deformed waveform in each of N audio signals output from N microphones (where N is an integer equal to or greater than 2) based on a dynamic range of a circuit; and interpolation means that treats an audio signal in the N audio signals which has the clipped part detected by the clip detector means as an interpolation target, and other audio signals as non-interpolation targets, and interpolates the waveform of the clipped part of the interpolation target using the waveform of at least one audio signal in the non-interpolation targets.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Sony Corporation
    Inventor: Okifumi Hosomi
  • Publication number: 20120126893
    Abstract: This invention provides a power amplifier (100) including a signal source control unit (110) which generates and outputs an amplitude signal serving as the amplitude modulated component of an input signal and a pulse modulated signal based on the amplitude signal, and outputs a transmission signal obtained by superposing the input signal on a carrier, a delay adjustment unit (120) which synchronizes the amplitude signal, pulse modulated signal, and transmission signal with each other, a voltage signal generation unit (130) which outputs a voltage signal corresponding to the amplitude signal synchronized with the transmission signal, a current signal generation unit (140) which outputs a current signal corresponding to the pulse modulated signal synchronized with the transmission signal, and a transmission signal amplification unit (150) which amplifies the transmission signal, and outputs a transmission signal obtained by modulating the amplitude of the amplified transmission signal based on a modulated power
    Type: Application
    Filed: April 23, 2010
    Publication date: May 24, 2012
    Inventors: Shingo Yamanouchi, Kazuaki Kunihiro
  • Patent number: 8145149
    Abstract: Embodiments for at least one method and apparatus of a wireless transceiver are disclosed. For one embodiment, the wireless transceiver includes a transmit chain, wherein the transmit chain includes a power amplifier. The wireless transceiver additionally includes a receiver chain that is tunable to receive wireless signals over at least one of multiple channels, wherein the multiple channels are predefined. Further, the wireless transceiver includes a voltage converter. The voltage converter provides a supply voltage to the power amplifier, and operates at a single switching frequency, wherein the single switching frequency and all harmonics of the single switching frequency fall outside of the multiple channels.
    Type: Grant
    Filed: June 17, 2010
    Date of Patent: March 27, 2012
    Assignee: R2 Semiconductor, Inc
    Inventors: Ravi Ramachandran, Frank Sasselli
  • Patent number: 8036402
    Abstract: A distortion compensation system minimizes distortion in an audio system by monitoring a supply voltage and adjusting a clipping threshold and/or compression knee. An adjustable gain circuit controls the gain of the audio signal according whether the audio signal exceeds a variable threshold. The variable threshold is adjusted within a threshold range based on the supply voltage. Distortion due to clipping of the audio signal is minimized while available power at any given time is maximized.
    Type: Grant
    Filed: December 15, 2005
    Date of Patent: October 11, 2011
    Assignee: Harman International Industries, Incorporated
    Inventor: Kenneth Carl Furge
  • Publication number: 20100321109
    Abstract: An RF power amplifier system adjusts the supply voltage to the power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the RF input signal and an attenuated amplitude of the RF output signal of the power amplifier. A variable gain amplifier (VGA) adjusts the amplitude of the RF input signal, thus providing a second means of adjusting the amplitude of the output of the power amplifier. The gain of the VGA or the supply voltage to the power amplifier is controlled based on the AC components of the amplitude correction signal, while the DC components of the amplitude correction signal are blocked from controlling the VGA or the supply voltage to the power amplifier. The DC level of the gain control of the VGA, the average supply voltage to the power amplifier, or the closed loop gain of the overall amplitude correction loop is controlled separately by a compression control signal.
    Type: Application
    Filed: August 10, 2010
    Publication date: December 23, 2010
    Applicant: QUANTANCE, INC.
    Inventors: Serge Francois Drogi, Vikas Vinayak
  • Patent number: 7840193
    Abstract: A modulator 23 corrects an amplitude signal Rd by adding thereto an offset value ? and generates, based on the corrected amplitude signal Rd, an amplitude signal Ra for amplitude-modulating a radio-frequency signal. The modulator 23 includes: an offset voltage measurement section 109 operable to measure an offset voltage V2cal of the amplitude signal Ra; a correction value calculation section 110 operable to obtain a difference value ?V2cal between the offset voltage V2cal measured by the offset voltage measurement section 109 and an initial value of the offset voltage V2cal and operable to calculate, based on the difference value ?V2cal, a correction value VODAC for correcting the offset voltage V2cal; and an addition section 106 operable to add the correction value VODAC calculated by the correction value calculation section 110 to a signal processed until the amplitude signal Ra is generated from the amplitude signal Rd.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Hara, Shigeru Morimoto
  • Publication number: 20100244952
    Abstract: A gain control circuit includes a comparator that compares an input gain value with a count value to generate a comparison result signal, a counter that counts up or counts down the count value in accordance with the comparison result signal, and a gain modulator circuit that modulates the count value to generate a gain control signal which changes in a time-divided manner. The gain modulator circuit modulates the count value so that a gain obtained by time-averaging a gain corresponding to the gain control signal matches a gain based on the count value.
    Type: Application
    Filed: January 25, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU MICROELECTRONICS LIMITED
    Inventor: Toshiya Kamibayashi
  • Patent number: 7734263
    Abstract: A transmission circuit operates with high efficiency and low distortion. An amplitude and phase extraction section extracts amplitude data and phase data from input data. A phase modulation section phase-modulates the phase data to output a resultant signal as a phase-modulated signal. An amplifier section amplifies the phase-modulated signal to output a resultant signal as a transmission signal. An amplitude control section supplies, to the amplifier section, a voltage controlled in accordance with an AC component represented by a fluctuation component of the amplitude data and a DC component represented by an average value level of the fluctuation component of the amplitude data.
    Type: Grant
    Filed: June 21, 2007
    Date of Patent: June 8, 2010
    Assignee: Panasonic Corporation
    Inventors: Masakatsu Maeda, Taichi Ikedo
  • Patent number: 7565283
    Abstract: A method and system for controlling potentially harmful signals in a signal arranged to convey speech is described. The method includes the steps of establishing characteristics of the signal when it is conveying speech; monitoring the signal; and controlling the signal relative to the established characteristics.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: July 21, 2009
    Assignee: Hearworks Pty Ltd.
    Inventor: Michael John Amiel Fisher
  • Patent number: 7499502
    Abstract: An amplifier includes a modulation coder receiving an original modulation signal and generating an amplitude signal and a phase signal, a voltage adjusting instrument which generates an amplitude modulation signal from the amplitude signal, a carrier generator generating a phase modulation signal from the phase signal, and an amplification device receiving the phase modulation signal and the amplitude modulation signal serving as a bias voltage and outputting a modulation signal obtained by restoring and amplifying the original modulation signal. The voltage adjusting instrument determines a DC offset voltage on the basis of a level control signal indicating the level of the amplitude modulation signal and generates the amplitude modulation signal to which the DC offset voltage is added.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: March 3, 2009
    Assignee: Panasonic Corporation
    Inventors: Shigeru Morimoto, Hisashi Adachi, Toru Matsuura
  • Publication number: 20090015324
    Abstract: A system for controlling amplifier power is provided. The system includes a voltage envelope detector receiving a voltage signal and generating an attenuated voltage envelope signal. A current envelope detector receives a current signal and generates an attenuated current envelope signal. A controller receives power level data and generates attenuation control data for the voltage envelope signal and the current envelope signal. A detector receives the voltage envelope signal and the current envelope signal and generates a control signal based on the greater of the voltage envelope signal and the current envelope signal. A power amplifier level controller receives the control signal and generates a power amplifier level control signal.
    Type: Application
    Filed: July 11, 2007
    Publication date: January 15, 2009
    Inventors: Rahul Magoon, Scott D. Kee, Seyed-Ali Hajimiri, Ichiro Aoki, Roberto Aparicio Joo, Morten Damgaard, Setu Mohta, Geoff Hatcher
  • Patent number: 7446613
    Abstract: A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to maintain a constant input impedance. The predriver includes a limiting amplifier that provides isolation between the power amplifier and the RF input. A DC feedback circuit is used by the predriver that maintains the DC level of the inverters to a desired level.
    Type: Grant
    Filed: August 30, 2006
    Date of Patent: November 4, 2008
    Assignee: Black Sand Technologies, Inc.
    Inventors: Alan L. Westwick, Timothy J. Dupuis, Susanne A. Paul
  • Patent number: 7386075
    Abstract: An apparatus for and method of extending the dynamic range of a RF communications receiver. The invention provides a mechanism for controlling the gain of both the LNA and down conversion mixer in the front end portion of an RF receiver. Both the LNA and the mixer are adapted to have both low and high gain modes of operation. The control mechanism typically comprises a two bit gain control that places both the LNA and mixer in one of four operating gain mode states. The selection of the most appropriate operating gain mode state, is preferably determined in accordance with various metrics such as the received levels of the desired signal, levels of interference signals, bit error rate and receiver RSSI.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: June 10, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Alexander Mostov, Oren Eliezer
  • Patent number: 7372327
    Abstract: A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to maintain a constant input impedance. The predriver includes a limiting amplifier that provides isolation between the power amplifier and the RF input. A DC feedback circuit is used by the predriver that maintains the DC level of the inverters to a desired level.
    Type: Grant
    Filed: March 11, 2006
    Date of Patent: May 13, 2008
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Timothy J. Dupuis, Susanne A. Paul
  • Patent number: 7161427
    Abstract: A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to maintain a constant input impedance. The predriver includes a limiting amplifier that provides isolation between the power amplifier and the RF input. A DC feedback circuit is used by the predriver that maintains the DC level of the inverters to a desired level.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: January 9, 2007
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Timothy J. Dupuis, Susanne A. Paul
  • Patent number: 7148745
    Abstract: One embodiment in accordance with the invention is a circuit. For example, the circuit can include a first stage amplifier coupled to receive a reference voltage. The circuit can also include a second stage amplifier coupled with an output of the circuit and the first stage amplifier. Note that the output can be fed back to the first stage amplifier. Additionally, the circuit can include a module coupled with the second stage amplifier and can restrict current flow to the second stage amplifier and the output provided the circuit is in a sleep mode. Furthermore, the module can drive a terminal of the second stage amplifier to a logic low voltage provided the circuit is in the sleep mode.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 12, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventor: Gary P. Moscaluk
  • Patent number: 7113045
    Abstract: A method and apparatus provides an input structure for a power amplifier. In one example, the input structure has an input network and a predriver circuit to provide an input signal to the power amplifier. The input network includes a transformer for helping to maintain a constant input impedance. The predriver includes a limiting amplifier that provides isolation between the power amplifier and the RF input. A DC feedback circuit is used by the predriver that maintains the DC level of the inverters to a desired level.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: September 26, 2006
    Assignee: Silicon Laboratories Inc.
    Inventors: Alan L. Westwick, Timothy J. Dupuis, Susanne A. Paul
  • Patent number: 7038538
    Abstract: An operational amplifier comprises multiple stages. A differential input stage that includes an adaptive high voltage differential pair generates up and down output currents in response to up and down input voltages. The differential input stage includes adaptive common input high voltage (HV) bias. An intermediate stage converts the up and down output currents into a first output voltage signal. The intermediate stage includes a folded cascode arrangement. The intermediate stage is biased by fixed voltage bias signals. The intermediate stage also includes unaffected slew rate stability compensation and a combined split stability compensation. An output stage includes a class AB source follower driver that generates a second output voltage signal in response to the first output voltage signal. The output stage is biased with an adaptive push-pull source follower output HV bias. The output stage includes feed-forward slew rate enhancement.
    Type: Grant
    Filed: February 26, 2003
    Date of Patent: May 2, 2006
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Sakhawat M. Khan, William John Saiki
  • Patent number: 6998915
    Abstract: An apparatus for switching a matching circuit in a mobile communication terminal includes a PIN diode connected in parallel to an RF signal input and output line to be turned on and off to connect and disconnect an impedance matching-element to the RF signal input and output line in accordance with a frequency band switching-signal, and a bias circuit for generating a bias voltage applied to the PIN diode in accordance with the frequency band switching-signal, thereby shifting an amplitude of an RF signal to a positive side at an off-time of the PIN diode.
    Type: Grant
    Filed: January 16, 2003
    Date of Patent: February 14, 2006
    Assignee: NEC Corporation
    Inventor: Makoto Akiya
  • Patent number: 6985039
    Abstract: Method and circuit for stabilizing the output power of a power amplifier, operated with signals having a large peak-to-average ratio and fed by a DC power supply with fluctuating output voltage. An allowable fluctuating range for the voltage output from the DC power supply and a constant voltage level are determined. A controllable voltage enhancement circuitry that can output an enhancement voltage is provided. The input of the voltage enhancement circuitry and a first DC supply path are connected to the output of the DC power supply. The output of the voltage enhancement circuitry is connected to a second DC supply path. While the instantaneous value of the fluctuating output voltage is lower than the constant voltage level, the voltage enhancement circuitry generates an enhancement voltage that causes the sum of the voltages supplied through the first and the second supply paths, to be identical to the constant voltage level.
    Type: Grant
    Filed: April 21, 2004
    Date of Patent: January 10, 2006
    Assignee: Paragon Communications Ltd.
    Inventors: Israel Bar-David, Avner Elia, Alexander Veinblat
  • Patent number: 6973399
    Abstract: A circuit arrangement for the correction of periodic signals from an incremental position measuring system that includes a first assembly comprising a multiplexer having an input to which a periodic signal is supplied and an output out of which an output signal is transmitted, a second assembly that receives the output signal and compares the output signal with at least one preset threshold value and, the second assembly selects a manipulated variable as a function of an actual position of a signal parameter in relation to the at least one preset threshold value from at least two preset, different manipulated variables and an actuating member that performs an action on the signal parameter in order to adjust the signal parameter in a direction toward a preset setpoint value.
    Type: Grant
    Filed: March 22, 2000
    Date of Patent: December 6, 2005
    Assignee: Dr. Johannes Heidenhain GmbH
    Inventors: Reiner Burgschat, Mathias Krauss
  • Patent number: 6954105
    Abstract: An amplifier may include an output stage including first and second output transistors, and a biasing stage for generating first and second biasing voltages at control terminals of the first and second output transistors, respectively, based upon a supply voltage and an input signal of the amplifier. The amplifier may also include a clamping stage having first and second clamping transistors for clamping outputs of the first and second output transistors to upper and lower clamping voltages, respectively. Additionally, the amplifier may also advantageously include a saturation detector connected to the clamping stage for providing a saturation signal for at least one of (a) the output of the first output transistor being clamped to the upper clamping voltage, and (b) the output of the second output transistor being clamped to the lower clamping voltage.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: October 11, 2005
    Assignee: STMicroelectronics, Inc.
    Inventor: Walter Stanley Gontowski, Jr.
  • Patent number: 6477358
    Abstract: Method for controlling the power gain for outputting a transmitted signal from a radio device. At the beginning of the transmitted signal, the output power is increased to a preset power level along a preset characteristic curve. At the end of the transmitted signal, the preset power is decreased along the preset characteristic curve. The power gain is controlled accordingly by a control signal (8, 9). A reference control signal (5) is used for the rising and falling edges of the control signal (8, 9). The control signal (8, 9) is limited to a preset maximum control signal value (6, 7).
    Type: Grant
    Filed: November 4, 1999
    Date of Patent: November 5, 2002
    Assignee: Robert Bosch GmbH
    Inventors: Thomas Mader, Gerhard Kottschlag, Gerhard Pitz
  • Patent number: 5703910
    Abstract: The present receiver includes a radiofrequency part (RF) coupled to a limiting amplifier (SL) which is in turn coupled to a demodulation means (DM) which recovers a digital signal from a received signal obtained by modulating a carrier signal with this digital signal. The limiting amplifier (SL) has an input-output characteristic which is substantially linear for smaller input signals and which strives with a decreasing gain towards a limit value for larger input signals. Due to this input-output characteristic smaller received signals are treated linearly up to the demodulation means (DM). The latter can therefore for these signals compensate for a specific spectrum shaping of the digital signal performed before the actual modulation. In this way the receiver will perform in a nearly optimal way resulting in low bit error rates. For larger received signals the limiting amplifier (SL) is non-linear and such compensation is consequently without effect resulting for these signals in a performance degradation.
    Type: Grant
    Filed: September 30, 1996
    Date of Patent: December 30, 1997
    Assignee: Alcatel N.V.
    Inventors: Marc Marie Ghislain Durvaux, Raphael Paul Claude Cassiers
  • Patent number: 5675611
    Abstract: Some mobile station cellular networks use either amplitude modulation or constant envelope modulation depending on the situation. The pulsed transmitter of the mobile station is switched on and off by a first control signal (TXP) and the output power envelope shaping of the pulse to be transmitted is controlled in the feedback loop by a second control signal (TXC). According to the invention the output power is controlled by a third control signal (TXCE) which in the amplitude modulation case switches off the feedback loop for the period of the information transfer and which at other times closes the feedback loop.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 7, 1997
    Assignee: Nokia Mobile Phones Ltd.
    Inventors: Kari T. Lehtinen, Jouko Hakkanen
  • Patent number: 5608756
    Abstract: The invention relates to a device identifying traffic on a cable. The different types of traffic are characterized by different levels and frequency ranges. The device includes a limiter connected to the paired cable and delivering an output signal having substantially constant amplitude And a frequency corresponding to the strongest frequency component of the input signal. The limiter may be constructed of inverters coupled as an amplifier or of an amplifier having a Schmitt trigger. The limiter is connected to a frequency indicator indicating what frequency ranges within which the strongest frequency component lies. The frequency indicator may consist of monostables or counters and decoders. The decoder interprets the output signal of the counter and may be constructed of a fixed gate network or of a programmable memory. The output signal of the frequency indicator is connected to an indicator indicating the frequency range in question, e.g. by means of flashing light-emitting diodes.
    Type: Grant
    Filed: February 28, 1995
    Date of Patent: March 4, 1997
    Assignee: Televerket
    Inventors: Alexander Latour-Henner, Bjorn Isheden
  • Patent number: 5606284
    Abstract: A variable gain amplifying circuit is controlled by a control voltage Vc from which a high-frequency component has been removed. To provide the control voltage Vc, a holding circuit smoothes the higher one of an output voltage of the variable gain amplifying circuit, which has been rectified by a rectifying circuit, and a voltage detected by a minute voltage detecting circuit, so that the control voltage Vc is obtained via a direct-current amplifying circuit. Since the clamping circuit varies the control voltage Vc based on a reference voltage Vref on receiving a minute input signal, even when an AGC characteristic is changed by varying the reference voltage Vref, the minimum gain is always corrected to be constant.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: February 25, 1997
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Tamesue, Koichi Nagano, Masuo Nakamura
  • Patent number: 5349304
    Abstract: An operational amplifier input stage has at least two positive input transistors and one negative input transistor for providing more accurate and efficient limiting or rectification in limiter and rectifier circuits. The two positive input transistors are connected in parallel having a common drain connected to one side of a load and the negative input transistor's drain is connected to the other side of the load. The sources of all transistors are connected to a common node which is connected to a constant current source. This arrangement enables simplistic high accuracy limiting and rectifier circuits, having a reduced number of extrinsic components, thereby reducing unwanted speed limitations, to be realized. The operational amplifier input stage is also very useful in low supply circuit applications.
    Type: Grant
    Filed: February 12, 1993
    Date of Patent: September 20, 1994
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventor: Marc H. Ryat
  • Patent number: 5341114
    Abstract: Integrated circuit structure and processing is provided for a high power limiter including at least a first anti-parallel array of monolithically integrated Schottky diodes. In a further embodiment, integrated circuit structure and processing is provided for an MMIC, microwave and millimeter wave monolithic integrated circuit, including an amplifier and a high power limiter monolithically integrated on the same substrate.
    Type: Grant
    Filed: November 2, 1990
    Date of Patent: August 23, 1994
    Assignee: AIL Systems, Inc.
    Inventors: Joseph A. Calviello, John A. Pierro
  • Patent number: 5334945
    Abstract: A power control circuit for use in radio transmitters such as portable telephone sets includes a power amplifier for amplifying the power of a transmission signal to obtain an output signal; control circuits for controlling the amplitude of the signal output by the power amplifier; a limiter for partially limiting the amplitude of the signal from the power amplifier in order to obtain a limited signal; a multiplication circuit for multiplying the limited signal from the limiter and part of the signal from the power amplifier in order to acquire a multiplied signal; a low-pass filter for extracting a DC component of the multiplied signal from the multiplication circuit; and a comparison circuit for comparing the DC component from the low-pass filter with a reference voltage in order to obtain a comparison output.
    Type: Grant
    Filed: February 23, 1993
    Date of Patent: August 2, 1994
    Assignee: Sony Corporation
    Inventors: Satoshi Yokoya, Nobutaka Takao