Output Networks Patents (Class 330/192)
  • Patent number: 7080185
    Abstract: An access destination determining section determines whether an access is directed to region 1 or region 2. A region 1 drive capability register and a region 2 drive capability register set drive capabilities of output buffers when accesses to region 1 and region 2 generate, respectively. For example, if “1” is set to region 1 drive capability register, when an access to region 1 generates, a Buf2 output enable signal is output at high level to enable outputs of Buf2s. Therefore, a drive capability of a bus can be altered according to a region to which an access is made by a CPU or the like, thereby enabling prevention of unnecessary power consumption and generation of noise.
    Type: Grant
    Filed: November 18, 2002
    Date of Patent: July 18, 2006
    Assignee: Renesas Technology Corp.
    Inventor: Takashi Kurafuji
  • Patent number: 4718100
    Abstract: Cabling (10) is provided for interconnecting amplifier (12) having a positive side (14) and a return side (16) to a load (18) having a positive side (20) and a return side (22). The cabling comprises a first open circuited conductor (24) having a first end (26) connected to a selected one of the amplifier positive side (14) and the amplifier return side (16) and having a second end (28) extending towards and terminating free from connection to the load (18). A second open circuited conductor (30) is provided which has a first end (32) connected to a respective one of the load positive side (20) and the load return side (22), said respective one being of a different polarity than the polarity of the selected one of the amplifier positive side (14) and amplifier return side (16) to which the first open circuited conductor (24) is connected and having a second end (34) extending towards and terminating free from connection to the amplifier (12).
    Type: Grant
    Filed: March 15, 1985
    Date of Patent: January 5, 1988
    Inventor: Bruce A. Brisson
  • Patent number: 4048578
    Abstract: An R.F. amplifier circuit having a high selectivity with a simple and inexpensive construction is provided. An R.F. choke coil acting as a bias supplying element is connected to a collector of an amplifying transistor to supply it with an optimum biasing current for a high electric field strength. A first capacitor is connected in parallel, at a high frequency, with the R.F. choke coil, which is connected to an LC tuning circuit through a second capacitor. A resonance frequency of the R.F. choke coil and the first capacitor is chosen to be sufficiently lower than that of the LC tuning circuit to maintain a single tuned circuit while at the same time an output impedance of the amplifying transistor is stepped up by the first and second capacitors to insure a high quality factor.
    Type: Grant
    Filed: October 27, 1976
    Date of Patent: September 13, 1977
    Assignee: Hitachi, Ltd.
    Inventor: Hiroshi Kimura