Involving Structure Of Three Diverse Function Electrode Type Patents (Class 330/309)
  • Patent number: 11267347
    Abstract: A power storage device includes a plurality of power storage units which are stacked and disposed in a predetermined direction, a plurality of terminal portions which are provided in the plurality of power storage units, and a plurality of conductive members which extend in the predetermined direction along the plurality of power storage units and are connected to the plurality of terminal portions. Each of the plurality of conductive members includes a connection portion attached to the terminal portion, a main body portion provided integrally with the connection portion, and an electrically insulating coating covering a surface of the main body portion. In each of the plurality of conductive members, a length of the connection portion in the predetermined direction is formed to change with a trend of increasing as a length of the main body portion in the predetermined direction increases.
    Type: Grant
    Filed: January 24, 2020
    Date of Patent: March 8, 2022
    Assignee: HONDA MOTOR CO., LTD.
    Inventor: Hideyuki Yoshida
  • Patent number: 9231111
    Abstract: An object is to provide a semiconductor device that includes an oxide semiconductor and is suitable for a power device. An object is to provide a semiconductor device in which large current can flow. An object is to provide a highly reliable semiconductor device. A semiconductor device includes an oxide stack in which a first oxide layer, a first oxide semiconductor layer, a second oxide semiconductor layer, and a second oxide layer are stacked and has a structure in which a region that contains an element imparting conductivity and is provided in the first oxide semiconductor layer overlaps an electrode functioning as a source electrode and does not overlap an electrode functioning as a drain electrode.
    Type: Grant
    Filed: February 6, 2014
    Date of Patent: January 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Akihisa Shimomura, Tetsuhiro Tanaka, Sachiaki Tezuka
  • Patent number: 8086358
    Abstract: A method and system for utilizing the heat dissipated by quiescent IC leakage currents to control the start-up temperature of components. A temperature control sub-system utilizes a thermal sensor to sense the junction temperature of the component. When the temperature is below an operating threshold, the control sub-system applies power to the component, and the component is self-heated due to the quiescent leakage current inherent to the component. This quiescent self-heating property serves as a source of pre-heat to elevate the temperature of the component, until the temperature, as indicated by the thermal sensor, rises above the minimum specified operating temperature of the component. The system may then be reliably initialized by applying full system power, and triggering a hardware reset or defined initialization sequence/procedure. Once the component(s) is operational, self-heating continues to maintain the component's temperature above the minimum operating threshold.
    Type: Grant
    Filed: July 11, 2007
    Date of Patent: December 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gary E. O'Neil, Michael E. Stopford, James B. Tate
  • Patent number: 7057453
    Abstract: Method and system for reducing parasitic feedback and resonances in high-gain transimpedance amplifiers. In a first embodiment of the present invention, a resistive layer is implemented in the gaps of a high-gain transimpedance amplifier's metallic planes. In a second embodiment of the present invention, a resistive layer is implemented underneath a high-gain transimpedance amplifier's ground plane, vias are implemented to create contact between the resistive layer and the ground plane.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: June 6, 2006
    Assignee: Inphi Corporation
    Inventors: Tom Peter Edward Broekaert, Marian Pospieszalski
  • Patent number: 6300669
    Abstract: A semiconductor integrated circuit device comprises a multiple-stage amplifier including a plurality of transistors. The multiple-stage amplifier has a first stage comprising a plurality of bipolar transistors each having a single emitter structure. The bipolar transistors are connected parallel to each other. The semiconductor integrated circuit device can easily be designed, is of a self-aligned structure, and has a single transistor size. The semiconductor integrated circuit device may be used as a low-noise, high-power-gain high-frequency amplifier.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: October 9, 2001
    Assignee: NEC Corporation
    Inventor: Yasushi Kinoshita
  • Patent number: 5572161
    Abstract: A method and circuit for tuning an equivalent resistor in a filter so that the filter is insensitive to temperature changes in which an amplifier output is connected to a common gate of plural MOSFETs for providing equivalent resistances, and in which one input to the amplifier is connected to a reference resistor and the other input to the amplifier is connected to an equivalent resistor that includes one of the plural MOSFETs. An input current to the reference resistor and to the equivalent resistor's MOSFET is inversely proportional to the MOSFET's conduction parameter, k (i.e., .mu.C.sub.ox /2), so that both the inputs to the amplifier vary to change the amplifier output voltage to the common gate. The amplifier output changes render the filter insensitive to temperature changes.
    Type: Grant
    Filed: June 30, 1995
    Date of Patent: November 5, 1996
    Assignee: Harris Corporation
    Inventor: Brent A. Myers
  • Patent number: T983011
    Abstract: an arrangement for stabilizing a bipolar semiconductor device such as might be commonly used in emitter follower or current switching configuration by the addition of lumped capacitance between the base of the semiconductor device and ground. In one preferred embodiment the lumped capacitance is derived from a flared or enlarged end of a base stabilizing resistor connected to the base of the semiconductor device, and in an alternative embodiment the capacitance is derived from a base collector junction of another unconnected semiconductor device located upon a common substrate with the semiconductor to be stabilized. The effect of the lumped capacitance, when added to the circuit, is to move the Z.sub.in plot of the transistor toward the fourth quadrant of a Nyquist diagram without the addition of a large series base resistance. The addition of the lumped capacitance is preferably utilized in conjunction with a small base stabilizing resistor in order to achieve stability in the input of the semiconductor.
    Type: Grant
    Filed: July 30, 1976
    Date of Patent: June 5, 1979
    Assignee: International Business Machines Corporation
    Inventors: Sylvester W. Giuliani, Arnold P. Mercer