With Semiconductor Amplifying Device (e.g., Transistor) Patents (Class 330/250)
  • Patent number: 11183972
    Abstract: An electronic device is provided. The electronic device includes an antenna, an amplification circuit configured to amplify a signal to be transmitted through the antenna, a first sensing circuit configured to sense first information corresponding to a voltage value of power supplied to the amplification circuit, a second sensing circuit configured to sense second information corresponding to a current value of the power, and a protective circuit. The protective circuit may be configured to summate the first information and the second information into a single parameter, to determine whether a summation value corresponding to the single parameter deviates from an operating area determined by characteristics of the amplification circuit, and to adjust an output of the amplification circuit if the summation value deviates from the operating area.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: November 23, 2021
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyunseok Choi, Dongil Yang, Youngju Kim, Jooseung Kim, Sanghun Sim, Youngmin Lee
  • Patent number: 11159189
    Abstract: A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: October 26, 2021
    Assignee: Skyworks Solutions, Inc.
    Inventors: Matthew Lee Banowetz, Philip H. Thompson, Edward James Anthony, James Henry Ross
  • Patent number: 11024541
    Abstract: A process for molding a back side wafer singulation guide is disclosed. Structures for heat mitigation include an overmold formed over a contact surface of a device layer of a wafer, covering bump structures. The overmold and bump structures are thinned and planarized, and the overmold provides an underfill to increase interconnect reliability of a semiconductor die in a flip chip bonded package. However, visibility of singulation guides on the contact surface is obstructed. A channel is formed extending through the device layer and into the handle layer, and is filled with the overmold. The handle layer is replaced with a thermally-conductive molding layer formed on the back side for dissipating heat generated by semiconductor devices. The thermally-conductive handle is thinned until the overmold in the channel beneath the device layer is exposed. The exposed overmold provides a visible back side singulation guide for singulating the wafer.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 1, 2021
    Assignee: Qorvo US, Inc.
    Inventors: Neftali Salazar, Rommel Quintero, Thomas Scott Morris
  • Patent number: 10931236
    Abstract: Provided is a detector circuit that includes: a first transistor that has an alternating current signal input to a base thereof, and that outputs a first detection signal that depends on the alternating current signal from a collector thereof; a second transistor that has the first detection signal input to a base thereof, and that outputs a second detection signal that depends on the first detection signal from a collector thereof; and an alternating current signal path along which the alternating current signal is supplied to the base of the second transistor.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: February 23, 2021
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Yasutaka Sugimoto, Hiroyuki Hirooka
  • Patent number: 10848107
    Abstract: Various transimpedance amplifier (TIA) arrangements for ultrasonic front-end receivers used in ultrasonic sensing applications are disclosed. An example TIA includes three common-source gain stages in a feedback loop with a common-gate stage. In some aspects, the TIA may include a level shifter configured to maintain the voltage at the gate of a transistor used to implement the first common-source gain stage of the feedback loop shifted by a certain amount with respect to the voltage at an input port to the TIA. In some aspects, at least portions of the TIA may be biased using bias currents that are configured to be process-, supply voltage-, and/or temperature-dependent. Various embodiments of the TIAs disclosed herein may benefit from one or more of the following advantages: reduced noise, reduced input impedance, reduced temperature coefficient of input impedance, and stability for a wide range of sensor frequencies.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: November 24, 2020
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Sanjay Tumati, Vinayak Agrawal, John A. Cleary
  • Patent number: 10516367
    Abstract: The present disclosure relates to a logic control circuit including a first inverter and a voltage limiter. The first inverter is connected to a first input voltage. The first inverter includes a first transistor having a first terminal and a second terminal. The second terminal of the first transistor is connected to a ground. The voltage limiter includes a second transistor. The second transistor has a gate connected to a ground, a source connected to the first terminal of the first transistor and a drain connected to a second input voltage.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: December 24, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Jaw-Ming Ding
  • Patent number: 10425047
    Abstract: A phased array antenna system having a plurality of antenna elements arranged into an array is disclosed. Each of a plurality of amplifier circuitries has an output terminal coupled to a corresponding one of the plurality of antenna elements and includes a power amplifier having a control terminal coupled to an input terminal. The power amplifier has a first current terminal coupled to the output terminal and a second current terminal coupled to a fixed voltage node. Further included in each of the plurality of amplifier circuitries is a current limiter having a bias terminal coupled to the control terminal of the power amplifier to adjust a bias point of the power amplifier to limit current flowing through the first current terminal and the second current terminal to within a predetermined current range. Some embodiments also include a voltage limiter to limit voltage amplitude at the output terminal.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: September 24, 2019
    Assignee: Qorvo US, Inc.
    Inventors: Alexander Wayne Hietala, Nadim Khlat, Michael F. Zybura
  • Patent number: 10326419
    Abstract: A power amplification circuit includes a first transistor, which includes a source coupled to a first power supply and receives an input signal at a gate of the first transistor, a capacitor, which includes a first terminal and a second terminal, the first terminal being coupled to a drain of the first transistor, and a transformer, which is coupled between the second terminal and the gate of the first transistor, transforms a first signal input from the second terminal, and outputs a second signal having a phase different from a phase of the first signal to the gate of the first transistor. The first transistor outputs an output signal from the drain of the first transistor.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: June 18, 2019
    Assignee: PANASONIC CORPORATION
    Inventor: Takayuki Abe
  • Patent number: 10199332
    Abstract: A semiconductor device includes a power transistor in a semiconductor substrate portion, where the semiconductor substrate portion includes a central portion and a kerf, components of the power transistor are arranged in the central portion, and the central portion has a thickness d. The semiconductor device also includes a support element disposed over a main surface of the central portion, where the support element has a smallest lateral extension t at a side adjacent to the main surface of the semiconductor substrate portion and a height h, where 0.1×h?d?4×h and 0.1×h?t?1.5×h.
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: February 5, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Oliver Hellmund, Peter Irsigler, Sebastian Schmidt, Hans-Joachim Schulze, Martina Seider-Schmidt
  • Patent number: 10171916
    Abstract: According to an embodiment, a circuit includes a high-? resistor including a plurality of semiconductor junction devices coupled in series and a plurality of additional capacitances formed in parallel with the plurality of semiconductor junction devices. Each semiconductor junction device of the plurality of semiconductor junction devices includes a parasitic doped well capacitance configured to insert a parasitic zero in a noise transfer function of the high-? resistor. Each additional capacitance of the plurality of additional capacitances is configured to adjust a parasitic pole in the noise transfer function of the high-? resistor in order to compensate for the parasitic zero.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: January 1, 2019
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Luca Valli, Benno Muehlbacher, Richard Gaggl
  • Patent number: 10136215
    Abstract: The invention relates to a method and apparatus for recognizing a digital audio signal in a system, in which at least some of the electronic components are at times in sleep or unenergized mode, in which method the digital audio signal is amplified and recognized, the amplified signal is decoded in a decoding circuit, the decoded signal is led to a signal processor for further processing and digital/analog conversion, and an audio signal is created from the analog signal. According to the invention, the amplified, undecoded signal is led directly to the signal- or microprocessor to be used and recognized, and the circuit implementing the decoder is kept in sleep mode unless a digital audio signal has been recognized.
    Type: Grant
    Filed: September 24, 2015
    Date of Patent: November 20, 2018
    Assignee: Genelec Oy
    Inventors: Pekka Moilanen, Kari Pöyhönen, Juho Väisänen
  • Patent number: 9825591
    Abstract: Aspects of this disclosure relate to dynamic error vector magnitude (DEVM) compensation. In one embodiment, an apparatus includes an amplifier, a low pass filter, and a bias circuit. The amplifier, such as a power amplifier, can amplify an input signal. The low pass filter, such as an integrator, can generate a correction signal based at least partly on an indication of a duty cycle of the amplifier. The indication of the duty cycle of the amplifier can be an enable signal for the amplifier, for example. The bias circuit can generate a bias signal based at least partly on the correction signal and provide the bias signal to the amplifier to bias the amplifier.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: November 21, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Lui Lam, Mark M. Doherty
  • Patent number: 9755678
    Abstract: Provided herein are apparatus and methods for transconductance amplifiers, such as split cascode low-noise transconductance amplifiers (LNTAs). In an embodiment, an LNTA includes split current paths each coupled to a different mixer by way of a different alternating current (AC) coupling capacitor. The split current paths of the LNTA can be enabled during different modes of operation, such as when the input to the LNTA is within different frequency bands.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: September 5, 2017
    Assignee: Analog Devices Global
    Inventors: Sivanendra Selvanayagam, Shane A. O'Mahony, Michael J. Deeney, Niall Kevin Kearney
  • Patent number: 9722771
    Abstract: A power amplifier module can include one or more switches, a coupler module, input signal pins, and a controller having first and second output terminals. The input signal pins can receive a voltage input/output signal, a clock input signal, and a data input signal. The controller can (i) set a mode of the one or more switches using a synchronous communication protocol in which the controller outputs a synchronous clock signal on the first output terminal and a data signal on the second output terminal, when the power amplifier module is in a first operating mode, or (ii) set a mode of the coupler module using an asynchronous communication protocol in which the controller outputs a first asynchronous control signal on the first output terminal and a second asynchronous control signal on the second output terminal, when the power amplifier module is in a second operating mode.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 1, 2017
    Assignee: Skyworks Solutions, Inc.
    Inventors: Matthew Lee Banowetz, Philip H. Thompson, Edward James Anthony, James Henry Ross
  • Patent number: 9530941
    Abstract: The present disclosure relates to a semiconductor light emitting device, comprising: a plurality of semiconductor layers, including an active layer, generating light via electron-hole recombination; a first electrode; a non-conductive distributed bragg reflector coupled to the plurality of semiconductor layers, reflecting the light from the active layer; and a first light-transmitting film coupled to the distributed bragg reflector from a side opposite to the plurality of semiconductor layers with respect to the non-conductive distributed bragg reflector, with the first light-transmitting film having a refractive index lower than an effective refractive index of the distributed bragg reflector.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: December 27, 2016
    Assignee: SEMICON LIGHT CO., LTD.
    Inventors: Soo Kun Jeon, Eun Hyun Park, Yong Deok Kim
  • Patent number: 9240390
    Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.
    Type: Grant
    Filed: April 24, 2014
    Date of Patent: January 19, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shun Meen Kuo, Paul R. Hart, Margaret A. Szymanowski
  • Patent number: 9207692
    Abstract: An envelope tracking power supply and an offset capacitive element are disclosed. The offset capacitive element is coupled between a switching output and an analog output of the envelope tracking power supply, which operates in one of an envelope tracking mode, a transition mode, and an average power tracking mode. During the envelope tracking mode, the envelope tracking power supply provides an envelope power supply signal using both the switching output and the analog output. During the transition mode, the envelope tracking power supply drives a voltage across the offset capacitive element from a first voltage to a second voltage, such that during a transition from the envelope tracking mode to the transition mode, the offset capacitive element has the first voltage, and during a transition from the transition mode to the average power tracking mode, the offset capacitive element has the second voltage.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: December 8, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Nadim Khlat, Michael R. Kay, Mohammad Ahsanul Adeeb
  • Patent number: 9182293
    Abstract: A power device temperature monitor is provided. The power device temperature monitor includes a power device having a control terminal and an output terminal, where the output terminal is configured to output a current as directed by a voltage of the control terminal. The power device temperature monitor includes an inductor coupled to the output terminal of the power device and an amplifier coupled to the inductor. The power device temperature monitor includes a computing device that receives an output of the amplifier, the computing device is configured to derive a temperature of the power device based upon the output of the amplifier.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: November 10, 2015
    Assignee: ATIEVA, Inc.
    Inventor: Yifan Tang
  • Patent number: 9035702
    Abstract: A microwave semiconductor amplifier includes a semiconductor amplifier element, an input matching circuit and an output matching circuit. The semiconductor amplifying element includes an input electrode and an output electrode and has a capacitive output impedance. The input matching circuit is connected to the input electrode. The output matching circuit includes a bonding wire and a first transmission line. The bonding wire includes first and second end portions. The first end portion is connected to the output electrode. The second end portion is connected to one end portion of the first transmission line. A fundamental impedance and a second harmonic impedance seen toward the external load change toward the one end portion. The second harmonic impedance at the one end portion has an inductive reactance. The output matching circuit matches the capacitive output impedance of the semiconductor amplifying element to the fundamental impedance of the external load.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: May 19, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 9030268
    Abstract: A power combiner/divider having a waveguide, a plurality of amplifiers disposed on a supporting structure, a plurality of probes, each one having a first end electrically coupled to an output of a corresponding one of the plurality of amplifiers and a second end projecting outwardly from the supporting structure and into the waveguide. The probes are disposed in a common region of the waveguide. The region has a common electric field maximum within the waveguide. A first portion of the probes proximate the sidewalls have lengths different from a second portion of the probes disposed in a region distal from the sidewalls of the waveguide. The waveguide is supported by the support structure. The power combiner is a monolithic microwave integrated circuit structure.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: May 12, 2015
    Assignee: Raytheon Company
    Inventors: Nicholas J. Kolias, Kenneth W. Brown
  • Patent number: 9026063
    Abstract: Disclosed embodiments include a direct current to direct current (DC-DC) converter including one or more charge pumps and configured to receive an input voltage and a first clock signal and a second clock signal. The first clock signal and second clock signal may be non-overlapping, and each may alternate between a ground voltage and a first voltage. The DC-DC converter may be configured to produce an output voltage over the clock cycle that has a negative polarity with a magnitude substantially equal to a sum of magnitudes of the input voltage and an integer multiple of the first voltage, the integer multiple being equal to a number of the one or more charge pumps in the DC-DC converter.
    Type: Grant
    Filed: May 17, 2011
    Date of Patent: May 5, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Andrew Labaziewicz, Manbir Nag
  • Patent number: 9019036
    Abstract: A power combiner/divider having a waveguide, a plurality of amplifiers disposed on a supporting structure, a plurality of probes, each one having a first end electrically coupled to an output of a corresponding one of the plurality of amplifiers and a second end projecting outwardly from the supporting structure and into the waveguide. The probes are disposed in a common region of the waveguide. The region has a common electric field maximum within the waveguide. A first portion of the probes proximate the sidewalls have lengths different from a second portion of the probes disposed in a region distal from the sidewalls of the waveguide. The waveguide is supported by the support structure. The power combiner is a monolithic microwave integrated circuit structure.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: April 28, 2015
    Assignee: Raytheon Company
    Inventors: Nicholas J. Kolias, Gabriel M. Rebeiz
  • Publication number: 20150108355
    Abstract: Disclosed are a charge sensitive amplifier, a detector and an X-ray photographing apparatus including the same. The charge sensitive amplifier includes an amplification unit that amplifies an electric charge input thereto, a capacitor that has one end of the capacitor, connected to an input terminal of the amplification unit, and the other end connected to an output terminal of the amplification unit, and a buffer unit that has an input terminal and an output terminal which is connected to the input terminal of the amplification unit and the one end of the capacitor. Impedance at the input terminal of the buffer unit is lower than impedance at the output terminal of the buffer unit.
    Type: Application
    Filed: August 8, 2014
    Publication date: April 23, 2015
    Inventors: Kang-Ho LEE, Jin-Myoung KIM, Jae-chul PARK
  • Patent number: 8983414
    Abstract: A communication system front-end architecture and a method of fabricating same are disclosed in which a diverse set of semiconductor technologies and device types (including CMOS, SiGe CMOS, InP HBTs (heterojunction bipolar transistors), InP HEMTs (high electron mobility transistors), GaN HEMTs, SiC devices, any number from a diverse set of MEMS sensors and actuators, and potentially photonics) is merged onto a single silicon, or other material substrate to thereby enable the development of smaller, lighter, and higher performance systems.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: March 17, 2015
    Assignee: Corporation for National Reseach Initiatives
    Inventors: Mehmet Ozgur, Michael Pedersen, Michael A. Huff
  • Patent number: 8963634
    Abstract: Techniques for sensing current delivered to a load by a differential output stage, e.g., in a Class D amplifier. In one aspect, voltages across sense resistors coupled in series with first and second branches of the differential output stage are low-passed filtered and digitized. The sense resistors may be coupled in series with the sources of transistors of the first and second branches, wherein the transistors are selectively switchable on and off by input voltage driving voltages. The input driving voltages may correspond to a ternary voltage waveform such that during a given phase, the two transistors coupled in series with the sense resistors may be turned off. Further aspects provide for the first and second branches having cascoded NMOS and/or PMOS transistors, and the sense resistors being provided between a pair of cascoded transistors.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: February 24, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Ankit Srivastava, Matthew D. Sienko, Meysam Azin, Xiaohong Quan, Peter J. Shah
  • Publication number: 20150008980
    Abstract: An apparatus of a power amplifier is provided. The apparatus includes an input boosting circuit configured to match a second harmonic input signal using a harmonic control circuit of an input stage to maximize an efficiency and an output power, a die cell configured to receive and amplify an output signal of the input boosting circuit, and an output boosting circuit configured to receive an output signal of the die cell and to match a second harmonic output signal of the output signal of the die cell using a harmonic control circuit of an output stage to maximize the efficiency and the output power.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 8, 2015
    Inventors: Il-Du KIM, Bumman KIM, Jung-Hwan SON, Kyoung-Tae KIM, Dong-Geun LEE
  • Publication number: 20140266434
    Abstract: A circuit for implementing a gain stage in an integrated circuit is described. The circuit comprises a first inductor formed in a first plurality of metal layers; a second inductor formed in a second plurality of metal layers, the second inductor coupled to a center tap of the first inductor; and wherein the second inductor has a diameter that is less than a diameter of the first inductor. A method of implementing a gain stage in an integrated circuit is also described.
    Type: Application
    Filed: March 14, 2013
    Publication date: September 18, 2014
    Applicant: Xilinx, Inc.
    Inventor: Xilinx, Inc.
  • Publication number: 20140270777
    Abstract: An electronic device comprising an optical gate, an electrical input an electrical output and a wide bandgap material positioned between the electrical input and the electrical output to control an amount of current flowing between the electrical input and the electrical output in response to a stimulus received at the optical gate can be used in wideband telecommunication applications in transmission of multi-channel signals.
    Type: Application
    Filed: March 18, 2014
    Publication date: September 18, 2014
    Applicant: Lawrence Livermore National Security, LLC
    Inventor: Stephen Sampayan
  • Publication number: 20140253232
    Abstract: An amplifier circuit includes: a first filter that receives input of amplitude information of an input signal, and performs filtering so that a gain of a frequency component higher than a first cutoff frequency becomes greater than a gain of a frequency component lower than the first cutoff frequency; a power supply circuit that has a low-pass filter characteristic that a gain of a frequency component lower than a second cutoff frequency is greater than a gain of a frequency component higher than the second cutoff frequency, and receives input of amplitude information outputted from the first filter and generates a power supply voltage corresponding to the amplitude information outputted from the first filter; and an amplifier that receives supply of the power supply voltage generated by the power supply circuit, and amplifies a signal based on the input signal.
    Type: Application
    Filed: May 21, 2014
    Publication date: September 11, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Kazuaki Oishi
  • Patent number: 8818304
    Abstract: According to one embodiment, a transmitter includes a first buffer, a second buffer, a logic circuit, and a class E power amplifier. The first buffer receives a first sinusoidal signal, and converts the first sinusoidal signal to a first rectangular wave signal. The second buffer receives a second sinusoidal signal having a phase delay with respect to the first sinusoidal signal, and converts the second sinusoidal signal to a second rectangular wave signal. The logic circuit receives the first and second rectangular wave signals, and performs logical operation processing on the first and second rectangular wave signals to generate a logic signal with a predetermined duty cycle. The class E power amplifier receives the logic signal, and performs amplification operation based on the logic signal.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: August 26, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yutaka Shimizu
  • Patent number: 8791719
    Abstract: In accordance with some embodiments, the present disclosure relates to a dual mode control interface that can be used to provide both a radio frequency front end (RFFE) serial interface and a two-mode general purpose input/output (GPIO) interface within a single digital control interface die. In certain embodiments, the dual mode control interface, or digital control interface, can communicate with a power amplifier. Further, the dual mode control interface can be used to set the mode of the power amplifier.
    Type: Grant
    Filed: October 23, 2012
    Date of Patent: July 29, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventor: David Steven Ripley
  • Publication number: 20140155003
    Abstract: A transformer (101) includes four terminals (N1 to N4), and parasitic resistances (109 and 110) are present in the transformer (101). A coupling capacitor (102) is provided between the terminals (N1 and N3), and a coupling capacitor (103) is provided between the terminals (N2 and N4). Shunt capacitors (104 to 107) are respectively provided between the respective terminals (N1 to N4) and a ground. Further, a phase shifter (112) is electrically connected to the terminal (N2), and a phase shifter (113) having a phase delay larger than that of the phase shifter (112) is connected to the terminal (N3).
    Type: Application
    Filed: November 16, 2012
    Publication date: June 5, 2014
    Inventor: Toshifumi Nakatani
  • Publication number: 20140077883
    Abstract: A cascode gain stage apparatus includes an input transistor having an RF input node and a transistor output node, an output transistor having a transistor input node and an RF output node, and a DC blocking capacitor connected between the transistor input and transistor output nodes.
    Type: Application
    Filed: March 13, 2013
    Publication date: March 20, 2014
    Inventors: Teledyne Scientific & Imaging, LLC, The Regents of the University of California, a California Corporation
  • Publication number: 20140002187
    Abstract: Systems and methods are disclosed for integrating functional components of front-end modules for wireless radios. Front-end modules disclosed may be dual-band front-end modules for use in 802.11ac-compliant devices. In certain embodiments, integration of front-end module components on a single die is achieved by implementing a high-resistivity layer or substrate directly underneath, adjacent to, and/or supporting SiGe BiCMOS technology elements.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Michael Joseph McPartlin, Mark M. Doherty
  • Publication number: 20140002188
    Abstract: A power amplifier module includes a power amplifier including a GaAs bipolar transistor having a collector, a base abutting the collector, and an emitter, the collector having a doping concentration of at least about 3×1016 cm?3 at a junction with the base, the collector also having at least a first grading in which doping concentration increases away from the base; and an RF transmission line driven by the power amplifier, the RF transmission line including a conductive layer and finish plating on the conductive layer, the finish plating including a gold layer, a palladium layer proximate the gold layer, and a diffusion barrier layer proximate the palladium layer, the diffusion barrier layer including nickel and having a thickness that is less than about the skin depth of nickel at 0.9 GHz. Other embodiments of the module are provided along with related methods and components thereof.
    Type: Application
    Filed: June 13, 2013
    Publication date: January 2, 2014
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventors: Howard E. Chen, Yifan Guo, Dinhphuoc Vu Hoang, Mehran Janani, Tin Myint Ko, Philip John Lehtola, Anthony James LoBianco, Hardik Bhupendra Modi, Hoang Mong Nguyen, Matthew Thomas Ozalas, Sandra Louise Petty-Weeks, Matthew Sean Read, Jens Albrecht Riege, David Steven Ripley, Hongxiao Shao, Hong Shen, Weimin Sun, Hsiang-Chih Sun, Patrick Lawrence Welch, Peter J. Zampardi, JR., Guohao Zhang
  • Publication number: 20130336066
    Abstract: A sense amplifier (100) includes first and second inverters (112 and 113). The first inverter has an input terminal (116) and an OUT_B output node and a first transistor (124). The second inverter (113) has an input terminal (115) and an OUT output node and a second transistor (125). The OUT_B output node of the first inverter is coupled to an input terminal of the second inverter, and the OUT node of the second inverter is coupled to an input terminal of the first inverter. The sense amplifier does not use a reference current; therefore, the sense amplifier does not need a reference current generator. The sense amplifier needs only one enable signal to reset a latch (110) of the sense amplifier. When coupled to a non-volatile memory element, voltages at the output nodes are indicative of a logic level of a bit stored in the non-volatile memory element.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Walter Luis TERCARIOL, Andre Luis VILAS BOAS, Fernando Zampronho NETO
  • Publication number: 20130293297
    Abstract: The present invention relates to an integrated amplification circuit for a transducer signal comprising a semiconductor substrate. The semiconductor substrate comprises a signal limiting network comprising first and second parallel legs coupled between an input of a preamplifier and a first predetermined electric potential of the integrated amplification circuit. The first leg comprises a plurality of cascaded semiconductor diodes coupled to conduct current in a first direction through the limiting network and the second leg comprises a plurality of cascaded semiconductor diodes coupled to conduct current in a second direction through the limiting network. A current blocking member is configured to break a parasitic current path between an anode or a cathode of a semiconductor diode of the first leg or the second leg and the semiconductor substrate.
    Type: Application
    Filed: May 1, 2012
    Publication date: November 7, 2013
    Applicant: ANALOG DEVICES A/S
    Inventors: Igor Mucha, Pavol Tikovic, Marek Matej
  • Publication number: 20130234794
    Abstract: A microwave semiconductor amplifier includes a semiconductor amplifier element, an input matching circuit and an output matching circuit. The semiconductor amplifying element includes an input electrode and an output electrode and has a capacitive output impedance. The input matching circuit is connected to the input electrode. The output matching circuit includes a bonding wire and a first transmission line. The bonding wire includes first and second end portions. The first end portion is connected to the output electrode. The second end portion is connected to one end portion of the first transmission line. A fundamental impedance and a second harmonic impedance seen toward the external load change toward the one end portion. The second harmonic impedance at the one end portion has an inductive reactance. The output matching circuit matches the capacitive output impedance of the semiconductor amplifying element to the fundamental impedance of the external load.
    Type: Application
    Filed: December 27, 2012
    Publication date: September 12, 2013
    Inventor: Kazutaka TAKAGI
  • Patent number: 8526536
    Abstract: A transmitter (200) comprises a first Chireix compensation circuit (230, 232, 238, 240) and a second Chireix compensation circuit (234, 236, 238, 240), wherein each Chireix compensation circuit has two inputs and two outputs. Two constant envelope input signals (22, 224) to be amplified are guided by a switch (226) to either the first or second Chireix amplifier unit. The selection as such depends on the phase (212) of the input signals to be amplified. The outputs of the two Chireix compensation circuits are cross-coupled to an inductive load (242). A Chireix inductor (238) and a Chireix capacitor (240), each having one terminal grounded, are also connected to the inductive load (242). By switching the signals to be amplified in response to their phase, optimum matching is ensured.
    Type: Grant
    Filed: May 15, 2010
    Date of Patent: September 3, 2013
    Assignee: NXP B.V.
    Inventors: Jan Sophia Vromans, Mark Pieter van der Heijden, Mustafa Acar
  • Publication number: 20130207730
    Abstract: Disclosed is an impedance matching circuit capable of wideband matching. The impedance matching circuit includes: a first variable inductor unit of which one end is connected to the first node and an inductance value varies; a second inductor unit connected between the first node and a second node and having a variable inductance value; a first variable capacitor unit of which one end is connected to the first node and a capacitance value varies; and a second variable capacitor unit of which one end is connected to the second node and a capacitance value varies, and the other end of the first variable capacitor unit and the other end of the second variable capacitor unit are connected to a ground voltage terminal to perform the impedance matching between a circuit connected to the other end of the first variable inductor unit and a circuit connected to the second node.
    Type: Application
    Filed: January 17, 2013
    Publication date: August 15, 2013
    Applicant: Electronics and Telecommunications Research Institute
    Inventor: Electronics and Telecommunications Research Institute
  • Patent number: 8508515
    Abstract: A buffering circuit with reduced power consumption is provided. The output buffering circuit includes first and second amplifier circuits. The first amplifier circuit includes a first input stage and a first output stage both coupled between a first power voltage and a second power voltage lower than the first power voltage, and an assistant discharging unit configured to provide a discharging current flowing from a first output node to a first intermediate power voltage during a discharging operation of the first amplifier circuit. The second amplifier circuit includes a second input stage and a second output stage both coupled between the first power voltage and the second power voltage, and an assistant charging unit configured to provide a charging current flowing from a second intermediate power voltage to a second output node during a charging operation of the second amplifier circuit.
    Type: Grant
    Filed: August 5, 2009
    Date of Patent: August 13, 2013
    Assignees: Himax Technologies Limited, NCKU Research and Development Foundation
    Inventors: Jia-Hui Wang, Chien-Hung Tsai, Ying-Lieh Chen, Chin-Tien Chang
  • Patent number: 8463143
    Abstract: An amplifier for an optical receiver is disclosed. The amplifier includes a common base buffer, a differential amplifier, and some buffer amplifiers, where circuit block from the common base buffer to the buffer amplifiers have the differential arrangement and are connected in series in this order. The amplifier further includes an offset compensator that receives the outputs of the buffer amplifier put in the rear end of the amplifier and outputs control signals, which are complementary to each other and filtered by a low-pass-filter, to the base of the transistors in the common base buffer to compensate the offset appeared in the output of the buffer amplifier.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: June 11, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Yoshiyuki Sugimoto
  • Patent number: 8451058
    Abstract: There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: May 28, 2013
    Assignee: Broadcom Corporation
    Inventors: Delong Cui, Afshin Momtaz, Jun Cao
  • Publication number: 20130116017
    Abstract: Apparatus and methods for power amplifiers are disclosed. In one embodiment, a power amplifier circuit assembly includes a power amplifier and an impedance matching network. The impedance matching network is operatively associated with the power amplifier and is configured to provide a load line impedance to the power amplifier between about 6 ? and about 10 ?. The impedance matching network includes a fundamental matching circuit and one or more termination circuits, and the fundamental matching circuit and each of the of the one or more termination circuits include separate input terminals for coupling to an output of the power amplifier so as to allow the fundamental matching circuit and each of the one or more termination circuits to be separately tuned.
    Type: Application
    Filed: November 1, 2012
    Publication date: May 9, 2013
    Applicant: SKYWORKS SOLUTIONS, INC.
    Inventor: SKYWORKS SOLUTIONS, INC.
  • Publication number: 20130088295
    Abstract: A power amplifier (20) for operation in at least a first and a second frequency band, wherein a center frequency f2 of the second frequency band is higher than a center frequency f1 of the first frequency band, is disclosed. The power amplifier (20) comprises a transistor (35) for amplifying an input signal of the power amplifier (20) and an output coupling network (45) for connecting the power amplifier to a resistive load (55). The output coupling network (45) is operatively connected to an output terminal (40) of the transistor (35), has an output terminal (50) for connection to said resistive load (55), and is configured such that, when the power amplifier (20) is connected to said resistive load (55), the power amplifier (20) is arranged to operate in class F for frequencies in one of the first and the second frequency bands, and operate in inverse class F for frequencies in the other one of the first and the second frequency band.
    Type: Application
    Filed: June 29, 2010
    Publication date: April 11, 2013
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Linsheng Liu, Xiaochuan Jiang
  • Patent number: 8417200
    Abstract: Embodiments provide transmitter topologies that improve the power efficiency and bandwidth of RF transmitters for high transmission power applications. In an embodiment, the common-emitter/source PA of conventional topologies is replaced with a current-input common-base/gate PA, which is stacked on top on an open-collector/drain current-output transmitter. The common-base/gate PA protects the output of the transmitter from large output voltage swings. The low input impedance of the common-base/gate PA makes the PA less susceptible to frequency roll-off, even in the presence of large parasitic capacitance produced by the transmitter. At the same time, the low input impedance of the common-base/gate PA reduces the voltage swing at the transmitter output and prevents the transmitter output from being compressed or modulated. In an embodiment, the DC output current of the transmitter is reused to bias the PA, which results in power savings compared to conventional transmitter topologies.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: April 9, 2013
    Assignee: Broadcom Corporation
    Inventors: Ray (Ramon) Gomez, Leonard Dauphinee, Massimo Brandolini, Jianhong Xiao, Dongsoo Koh, Young Shin, Chonghua Zhong, Rezaur Rahman Khan
  • Patent number: 8411879
    Abstract: A speaker driver circuit driven by positive and negative voltages, comprising: at least one operational amplifier providing an output to a headphone speaker, and a voltage converter receiving a supplied voltage (VDD), generating r-fold positive and negative voltages (r·VDD and ?r·VDD, wherein r is any positive real number except 1) according to the supplied voltage, and supplying the positive and negative voltages to the operational amplifier for its high and low operation voltage levels respectively.
    Type: Grant
    Filed: July 21, 2009
    Date of Patent: April 2, 2013
    Assignee: Richtek Technology Corporation
    Inventors: Jwin-Yen Guo, Ching-Hsiang Yang
  • Patent number: 8390496
    Abstract: System and method for common mode translation in continuous-time sigma-delta analog-to-digital converters. An embodiment includes a loop filter having an RC network coupled to a differential signal input, a Gm-C/Quantizer/DAC circuit (GQD) coupled to the loop filter, a common-mode level adjust circuit coupled to signal inputs of the GQD, and a tuning circuit coupled to the GQD and the common-mode level adjust circuit. The GQD evaluates an input signal provided by the RC network. computes a difference between a filtered input signal and the feedback quantization signal to generate an error signal, measures the error signal, and compensates for the error signal with sigma-delta noise-shaping. The common-mode level adjust circuit alters a common-mode level of a differential input signal to be substantially equal to a desired common-mode level and the tuning circuit provides a compensation voltage to the common-mode level adjust circuit based on a difference between the common-mode levels.
    Type: Grant
    Filed: February 23, 2010
    Date of Patent: March 5, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Ayman A. Fayed, Russell Byrd, Baher Haroun
  • Publication number: 20130038390
    Abstract: Power amplifiers and methods of coating a protective film of alumina (Al2O3) on the power amplifiers are disclosed herein. The protective film is applied through an atomic layer deposition (ALD) process. The ALD process can deposit very thin layers of alumina on the surface of the power amplifier in a precisely controlled manner. Thus, the ALD process can form a uniform film that is substantially free of free of pin-holes and voids.
    Type: Application
    Filed: October 18, 2012
    Publication date: February 14, 2013
    Applicant: RF MICRO DEVICES, INC.
    Inventor: RF MICRO DEVICES, INC.
  • Publication number: 20130002358
    Abstract: A circuitry adapted to operate in a high-temperature environment of a turbine engine is provided. A relatively high-gain differential amplifier (102) may have an input terminal coupled to receive a voltage indicative of a sensed parameter of a component (20) of the turbine engine. A hybrid load circuitry may be coupled to the differential amplifier. A voltage regulator circuitry (244) may be coupled to power the differential amplifier. The differential amplifier, the hybrid load circuitry and the voltage regulator circuitry may each be disposed in the high-temperature environment of the turbine engine.
    Type: Application
    Filed: July 12, 2012
    Publication date: January 3, 2013
    Inventors: David J. Mitchell, John R. Fraley, Jie Yang, Cora Schillig, Bryon Western, Roberto Marcelo Schupbach