Abstract: A signal amplifier includes a discrete-variable-gain amplifying unit, a gain of which takes a discrete value and changes stepwise, a linear-variable-gain amplifying unit connected in series to the discrete-variable-gain amplifying unit, a gain of which changes continuously, control-signal outputting means for detecting a level of an output signal from a series connection circuit of the discrete-variable-gain amplifying unit and the linear-variable-gain amplifying unit and outputting a control signal corresponding to a difference between the level of the output signal and a reference voltage set as a comparative level to control the gain of the linear-variable-gain amplifying unit, and gain-switching control means for controlling to switch the gain of the discrete-variable-gain amplifying unit when the control signal deviates from a setting range for the control signal that is set according to a variable gain range of the discrete-variable-gain amplifying unit.

Abstract: A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.

Abstract: A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.

Abstract: A circuit including a first sensitive node, a first component connected between the first sensitive node and a first terminal of a first switch, said first switch controlled by a first control signal variable between a supply voltage level and a second voltage level, and a second switch including a first terminal connected to the first terminal of said first switch, and a second terminal connected to a clean voltage supply, said second switch controlled to connect the first node of said first switch to said clean voltage supply when said first switch is in a non-conducting state.

Abstract: Provided is a gain amplifier having a switched-capacitor structure capable of minimizing settling time, in which an input capacitor is connected to an input terminal during a first clock sampling an input signal, and thus an output terminal of the amplifier is reset in advance to an estimated output voltage value rather than 0 by the input capacitor. Accordingly, the slight move of the output terminal of the amplifier is sufficient to settle to a desired value in an amplification mode, so that slewing time can be reduced, and as a result, overall settling time and power consumption can be minimized.

Abstract: An amplifier is disclosed that includes configurable feedback based on the output of a received signal strength indicator. The feedback may be increased for high received signal levels, and decreased for low received signal levels. In an embodiment, the configurable impedance may comprise a plurality of discrete impedance settings. Amplitude and/or time hysteresis may be incorporated.

Abstract: The invention is directed to a multi-band switch having a transmitter switching section with a plurality of transmission ports, and a receiver switching section with a plurality of receiver ports, each having associated switching topologies to switch one of the ports to an antenna port. The switching topologies may use a plurality of series-connected FETs, such as insulated gate n-channel FETs, where the transmitter port switching elements may have larger switching transistors than the receiver port switching elements. The main signal path transistors of the transmitter and receiver switching elements be interdigitated FETs, in which source region fingers and drain region fingers alternate within the transistor area. These interdigitated source and drain regions may be spaced apart from each other by a sinuous channel region, over which is a gate metallization.

Abstract: An amplifier circuit that is less likely to cause an error in a gain and a DC offset voltage and is suitable for reducing a size and power consumption is offered. A first resistor and a second resistor are connected in series between an input terminal and an output terminal. A third resistor and a fourth resistor are connected in series between a VREFL terminal and a VREFH terminal. A ratio of a resistance of the first resistor to a resistance of the second resistor is equal to a ratio of a resistance of the third resistor to a resistance of the fourth resistor. A voltage at a connecting node between the first resistor and the second resistor is applied to a first differential input terminal (?) of an operational amplifier, while either a voltage at a connecting node between the third resistor and the fourth resistor or VREFH is selectively applied to a second differential input terminal (+) of the operational amplifier.

Abstract: An amplifier circuit that is less likely to cause an error in a gain and a DC offset voltage and is suitable for reducing a size and power consumption is offered. A first resistor and a second resistor are connected in series between an input terminal and an output terminal. A third resistor and a fourth resistor are connected in series between a VREFL terminal and a VREFH terminal. A ratio of a resistance of the first resistor to a resistance of the second resistor is equal to a ratio of a resistance of the third resistor to a resistance of the fourth resistor. A voltage at a connecting node between the first resistor and the second resistor is applied to a first differential input terminal (?) of an operational amplifier, while either a voltage at a connecting node between the third resistor and the fourth resistor or VREFH is selectively applied to a second differential input terminal (+) of the operational amplifier.

Abstract: A low noise amplifier including a first-stage signal amplifier, a second-stage signal amplifier and a gain control unit is disclosed. The first-stage signal amplifier is for receiving an input signal and outputting a first output signal accordingly. The second-stage signal amplifier is coupled to the first-stage signal amplifier for outputting a second output signal according to the first output signal. The second-stage signal amplifier includes a first output transistor for outputting the second output signal. The gain control unit includes a first variable resistance device coupled to an input terminal of the first output transistor for adjusting voltage gain of the second output signal.

Abstract: A gain controlled amplifier and a cascoded gain controlled amplifier based on the same are disclosed. The gain controlled amplifier includes an operational amplifier for amplifying an input signal, an input resistor connected to an input terminal of the operational amplifier, a feedback resistor connected to an output terminal of the operational amplifier, and a resistor circuit for providing voltages having different levels to the input terminal and the output terminal of the operational amplifier, respectively, according to a digital signal composed of specified bits. The gain controlled amplifier employs an R-2R ladder circuit controlled by a digital signal so as to obtain a gain that is in linear proportion to a decibel scale. Since the R-2R ladder circuit operates with a small resistance value, the chip size of the gain controlled amplifier can be reduced.

Abstract: A line driver includes: a differential amplifier for amplifying an input signal to generate an output signal; first and second series resistors coupled respectively to output terminals of the differential amplifier and through which the output signal is output; first and second negative-feedback resistors each coupled between a respective input terminal and a respective output terminal of the differential amplifier; first and second positive-feedback variable resistors each coupled between a respective input terminal of the differential amplifier and a respective one of the first and second series resistors; and an adjusting unit coupled to the first and second positive-feedback variable resistors to adjust a resistance thereof with reference to the output signal.

Abstract: A linear programmable switch-capacitance gain amplifier (PGA) is described. The PGA divides the dB-gain curve into several parts by the concept of piece-wise linearity, and then simultaneously executes the dB-linear gain adjustment of MSB and the LSB at the same gain stage. Present invention achieves the PGA dB-linearity by setting up every capacitance of the sampling capacitor array and the holding capacitor array, then arranging the sampling capacitor array and the holding capacitor array by coordinating the switching of the capacitor switches.

Abstract: The present invention relates to a circuit configuration (10) having a feedback operational amplifier (AMP) for amplifying an input signal (Vin) input into the circuit arrangement (10) and outputting the amplified input signal as an output signal (Vout). The circuit amplification (Vout/Vin) may be changed by selectively connecting or disconnecting impedances (R1, . . . RN). Integration elements (INT1. . . INT N) connected upstream from each of the control inputs of transistors (S1, . . . SN) used for this purpose ensure a certain temporal smoothing of the curve of the circuit amplification (Vout/Vin) when connecting or disconnecting an impedance (R1, . . . RN). The integration element particularly ensures that even in the event of a sudden change of the affected activation signal (VD1, . . . VDN), the affected impedance (R1, . . . RN) is not also suddenly disconnected or connected.

Abstract: In one embodiment, an amplifier arrangement includes an amplifier having a first input, a second input and an output, a first resistor network, having a first parallel circuit formed by a first number N of resistors, and a second resistor network, having a first resistor or a second parallel circuit formed by a second number M of resistors. The resistors of the first and second resistor networks each have approximately the same nominal value, an approximately identical width W and an approximately identical length L of a resistive layer. The first and second resistor networks are coupled to the amplifier.

Abstract: A method of controlling an adjustable gain of an amplifier is disclosed. The method includes setting an output of a replica amplifier to be equivalent to a precision reference with a control loop, summing an adjustable offset voltage into the control loop, adjusting the adjustable offset voltage until an error offset voltage of the control loop is nulled, and controlling the adjustable gain of the amplifier with an output of the control loop. An apparatus for controlling an adjustable gain of an amplifier is also disclosed. The apparatus includes a control loop for setting the adjustable gain. The control loop includes an adjustable gain replica amplifier. A switch receives an output of the replica amplifier and a precision reference. An error amplifier receives outputs from the switch and generates a control voltage. The control voltage controls an adjustable gain of the replica amplifier and the adjustable gain of the amplifier.

Abstract: A gain controlled amplifier and a cascoded gain controlled amplifier based on the same are disclosed. The gain controlled amplifier includes an operational amplifier for amplifying an input signal, an input resistor connected to an input terminal of the operational amplifier, a feedback resistor connected to an output terminal of the operational amplifier, and a resistor circuit for providing voltages having different levels to the input terminal and the output terminal of the operational amplifier, respectively, according to a digital signal composed of specified bits. The gain controlled amplifier employs an R-2R ladder circuit controlled by a digital signal so as to obtain a gain that is in linear proportion to a decibel scale. Since the R-2R ladder circuit operates with a small resistance value, the chip size of the gain controlled amplifier can be reduced.

Abstract: This variable gain amplifier is provided with an operational amplifier. The non-inversion input terminal of the operational amplifier is connected to a reference potential. A feedback resistor is connected between the output terminal and inversion input terminal of the operational amplifier. An input resistor is inserted between the inversion input terminal of the operational amplifier and the input terminal of the variable gain amplifier circuit. An adjustment resistor is connected between the inversion input terminal of the operational amplifier and the reference potential. The resistance value of the adjustment resistor is controlled in such a way as to maintain constant against the resistance value change a combined resistance value in its parallel connection with the input resistor when changing the resistance value of the input resistor.

Abstract: A sensor interface filter having adjustable gain and Q is provided. The sensor interface includes a first operational amplifier coupled to gain circuitry, a gain stage, and a resistor. The gain circuitry and gain stage are electrically coupled to each other. The gain stage includes a gain stage switch, and is coupled to control circuitry. The control circuitry controls the state of the gain stage switch to vary the number of feedback current paths providing feedback to the inverting input of the first operational amplifier, altering the gain provided by the first operational amplifier. The sensor interface further includes a second operational amplifier coupled to filter circuitry and feedback switches. The feedback switches are coupled to the control circuitry, which controls the state of the feedback switches to vary the gain provided by the second operational amplifier and the filter Q of the sensor interface. A method is also provided.

Abstract: An analog variable gain amplifier (VGA) adjusting a signal level of a mobile communication system is provided. More particularly, design of a VGA using an operational transconductance amplifier (OTA) having a wide linear input/output range is disclosed. The VGA includes two double-differential-pair OTAs and feedback resistors. A first differential input of a first double differential pair OTA receives an input signal from the forward stage, and a second differential input is negatively fed back through a differential output and a passive resistor. An input in which a first block of the connection structure and first and second differential inputs of a second double differential pair OTA are connected receives an output signal of the first block stage. The output is negatively fed back in series through a variable resistor whose resistance varies exponentially with an adjustment voltage from outside.

Abstract: The present invention relates to a power amplifier for amplifying an electronic input signal (51) and a multi-band capable frontend with such power amplifier. The power amplifier comprises an amplifier transistor stage (1) having an input (52) and an output (53) and a feedback loop (4) placed between the output (53) and the input (52) of the amplifier transistor stage (1). The feedback loop (4) comprises a capacitor (41) and a resistive element (44) in a RF path and an inductive element (42) in a DC feed path, wherein said resistive element comprises a feedback transistor (45) arranged as variable resistor within the feedback loop, and a bias control circuit (46).

Abstract: A gain adjustment circuit includes a gain varying device for varying the gain of an input signal; and a detection device for detecting a variable output signal of the gain varying device, wherein the detection output signal of the detection device is fed back to the gain varying device.

Abstract: A feedback circuit disposed across input and output terminals of an amplifier is adapted so as not inject DC current back into the input terminal of the amplifier. The feedback circuit includes, in part, first and second current sources, a transistor, and a resistive load. The first current source supplies current to one of the terminals of the transistor in communication with an input terminal of the amplifier. The second current source receives this current and diverts it to a voltage supply. The transistor is maintained in the active region of operation. The resistive load has a first terminal in communication with an output terminal of the amplifier and a second terminal in communication with the transistor. The DC voltages at the two terminals of the resistive load are substantially equal so as to inhibit DC current flow therethrough.

Abstract: The present invention relates to a circuit configuration (10) having a feedback operational amplifier (AMP) for amplifying an input signal (Vin) input into the circuit arrangement (10) and outputting the amplified input signal as an output signal (Vout). In order to be able to change the circuit amplification (Vout/Vin) easily and reliably in the circuit configuration (10) and simultaneously keep an impairment of the output signal (Vout) caused by noise relatively low, capacitance values (Cb, C) of the coupling path (12) and of the feedback path (14) are adjusted simultaneously to one another correlated in a special way.

Abstract: A sensor interface filter having adjustable gain and Q is provided. The sensor interface includes a first operational amplifier coupled to gain circuitry, a gain stage, and a resistor. The gain circuitry and gain stage are electrically coupled to each other. The gain stage includes a gain stage switch, and is coupled to control circuitry. The control circuitry controls the state of the gain stage switch to vary the number of feedback current paths providing feedback to the inverting input of the first operational amplifier, altering the gain provided by the first operational amplifier. The sensor interface further includes a second operational amplifier coupled to filter circuitry and feedback switches. The feedback switches are coupled to the control circuitry, which controls the state of the feedback switches to vary the gain provided by the second operational amplifier and the filter Q of the sensor interface. A method is also provided.

Abstract: The present invention provides an optical receiver operable for optical signals each having different transmission speed. The optical receiver includes a light-receiving device, a pre-amplifier, a main amplifier, and a control circuit. The pre-amplifier, may be a trans-impedance amplifier, includes a parallel connection of a switching device and a resistor in a trans-impedance or a load element. By switching ON/OFF the switching device, the gain and the bandwidth of the pre-amplifier may be changed. By providing a filter circuit, whose cut-off frequency may be switched, in the main amplifier, the bandwidth of the optical receiver may be varied.

Abstract: A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.

Abstract: A programmable gain amplifier includes a first gain setting circuit and a second gain setting circuit that are both coupled to an output of an amplifier. A trim adjustment circuit is and arranged to complete feedback to the amplifier by digitally panning between the first gain setting and the second gain setting based on a trim setting. The trim setting can be provided by a look-up table that is indexed with gain settings. The first and the second gain setting circuits can each include an array of series coupled resistors, where a tap point from each array is selectively coupled to the trim adjustment circuit for adjusting the overall gain. The first and second gain setting circuits can be matched to one another, with the addition of a gain offset circuit that is configured to skew the nominal gain values between the first and second gain setting circuits.

Abstract: A disclosed amplifier circuit is capable of changing a gain to amplify an input signal according to a control signal. The amplifier circuit comprises a differential amplifier circuit adapted to receive and amplify the input signal to output the amplified input signal as an output signal, a first resistance and one or more second resistances connected to the differential amplifier circuit and adapted to set the gain, and one or more gain control circuits adapted to change the gain by controlling one or more electrical couplings of the one or more second resistances according to the control signal.

Abstract: A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.

Abstract: A programmable gain amplifier (PGA) circuit includes a gain adjust circuit and a gain select circuit that are both coupled to an output of an amplifier. The gain select circuit completes feedback to the amplifier while the gain adjust circuit is arranged to boost or cut the gain of the gain selection circuit. The gain adjust circuit can be arranged as a trim adjustment to the overall gain of the PGA circuit, where a different trim adjustment can be mapped to each gain setting such as from a look-up table. In other example implementations, the PGA circuit can periodically switch between multiple gain settings using a modulation scheme such that the overall gain is blended between the various gain settings according to a duty cycle, pulse-width, or delta-sigma modulation, with a time averaging effect on the overall gain of the PGA circuit.

Abstract: A low noise amplifier is provided that includes a first circuit block capable of amplifying a first voltage signal that is input to the amplifier. The first circuit block includes a first terminal coupled to a first supply voltage by a variable resistance, and a second terminal coupled to a second supply voltage. The second terminal is coupled to an output terminal of the amplifier, and the first voltage signal is applied to a further terminal of the first circuit block. The amplifier also includes a feedback network coupled to the output terminal and to the further terminal of the first circuit block, and a second circuit block coupled between the second supply voltage and the further terminal of the first circuit block. The second circuit block is adapted to compensate for variations in value of the variable resistance to ensure a substantially constant input resistance of the amplifier.

Abstract: Circuitry for use in a differential amplifier includes an input stage having a first differential amplifier and an offset compensation stage that includes at least one controllable current source. The offset compensation stage is connected to a bias input of the first differential amplifier. The circuitry includes an output stage having a second differential amplifier, where the output stage is after an output of the input stage, and a programmable resistor network for controlling an amplification of the input stage. The programmable resistor network controls the amplification in accordance with a feedback from the first differential amplifier.

Abstract: An amplifier 11 to which transistors 13 and 14 functioning as variable resistors are connected in parallel is used. A burst signal is received by a light receiving element 10 and the received signal is converted into an input current signal Iin. The input current signal Iin is converted in the amplifier 11 into an output voltage Vo. Determination is made in a determining circuit 20 as to whether the output voltage Vo exceeds a current voltage V1 which is a threshold. The result of determination is stored in a register circuit 15. Based on the result of determination outputted from the register circuit 15, a desired voltage is selected from among a number of voltages generated beforehand in a control voltage generating circuit. The selected voltage is used to generate a control voltage Vg1 or Vg2 to be applied to the transistors 13 and 14; and the generated control voltage Vg1 or Vg2 is inputted to the transistor 13 or 14 of the amplifier 11.

Abstract: A method and apparatus are provided for operating a feedback network (300, 400). The method and apparatus operate to combine (240) a feedback signal (IF) and an incoming signal (VIN) to generate an adjusted signal (IADJ) at an input node of an amplifier element (110); amplifying the amplifier input signal in the amplifier element to produce an amplifier output signal (VOUT) at an output node of the amplifier element; processing the amplifier output signal according to a feedback operation (230) to generate the feedback signal (IF); and providing an assist current (350, 450, IASSIST) to the output node of the amplifier element, separate from an output current provided by the amplifier element.

Abstract: A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.

Abstract: A method of controlling an adjustable gain of an amplifier is disclosed. The method includes setting an output of a replica amplifier to be equivalent to a precision reference with a control loop, summing an adjustable offset voltage into the control loop, adjusting the adjustable offset voltage until an error offset voltage of the control loop is nulled, and controlling the adjustable gain of the amplifier with an output of the control loop. An apparatus for controlling an adjustable gain of an amplifier is also disclosed. The apparatus includes a control loop for setting the adjustable gain. The control loop includes an adjustable gain replica amplifier. A switch receives an output of the replica amplifier and a precision reference. An error amplifier receives outputs from the switch and generates a control voltage. The control voltage controls an adjustable gain of the replica amplifier and the adjustable gain of the amplifier.

Abstract: An integrated circuit includes a resistive circuit with reduced mismatch that includes a primary resistive network with several main resistances (Rp) each having the same theoretical main value. It also includes an auxiliary resistance (Rau) having an auxiliary theoretical resistive value equal to the product or to the quotient of the theoretical main resistive value by ?{square root over (2)}. All these resistances are connected together so as to attribute a theoretical overall resistive value to the primary resistive network equal to the theoretical auxiliary resistive value.

Abstract: An amplifier array includes a servo amplifier, which has a reference signal input, a return signal input, and an output signal connection, which supplies an output signal path, a reference signal generator, which supplies reference signals with different level heights to the reference signal input, and with a return, which supplies a signal, attenuated by a value of the feedback attenuation, from the output path as a return signal to the return signal input, whereby the servo amplifier supplies an amplified difference between the reference signal and return signal in the output signal path. The amplifier array has a connectable bypass gain path, which in the connected state is supplied phase-coupled to the reference signal generator and which supplies a bypass output signal in the output path.

Abstract: A signal amplifier includes a discrete-variable-gain amplifying unit, a gain of which takes a discrete value and changes stepwise, a linear-variable-gain amplifying unit connected in series to the discrete-variable-gain amplifying unit, a gain of which changes continuously, control-signal outputting means for detecting a level of an output signal from a series connection circuit of the discrete-variable-gain amplifying unit and the linear-variable-gain amplifying unit and outputting a control signal corresponding to a difference between the level of the output signal and a reference voltage set as a comparative level to control the gain of the linear-variable-gain amplifying unit, and gain-switching control means for controlling to switch the gain of the discrete-variable-gain amplifying unit when the control signal deviates from a setting range for the control signal that is set according to a variable gain range of the discrete-variable-gain amplifying unit.

Abstract: A preamplifier includes a negative-feedback amplifier circuit that converts a current signal from a photodetector into a voltage signal; and a conversion-gain control circuit that simultaneously controls a resistance value of a feedback resistor portion of the negative-feedback amplifier circuit and a resistance value of a load resistor portion of the negative-feedback amplifier circuit, based on the voltage signal from the negative-feedback amplifier circuit. Each of the feedback resistor portion and the load resistor portion includes a fixed resistor element, a MOSFET element, and a diode-connected transistor, connected in parallel.

Abstract: In a charge amplifier, an operational amplifier is provided. The operational amplifier has an inverting input terminal, a non-inverting input terminal, and an output terminal. An adjustable feedback resistor element is provide to be connected between the inverting terminal and the output terminal. A resistance adjusting circuit is provided to be electrically connected to the adjustable feedback resistor element. The resistance adjusting circuit adjusts the resistance of the adjustable feedback resistor element to a first resistance during a first predetermined period after power-on. The resistance adjusting circuit also adjusts the resistance of the adjustable feedback resistor element to a second resistance after the first predetermined period has elapsed. The second resistance is higher than the first resistance.

Abstract: A transimpedance amplifier is provided which includes a feedback path. The feedback path includes a feedback resistor and a voltage generator. The feedback resistor has a parasitic capacitance associated therewith. The feedback resistor also has a first node at a first voltage. The voltage generator can be capacitively coupled to the feedback resistor at a second node via the parasitic capacitance. The voltage generator is configured to generate a second voltage at the second node which is substantially equal to the first voltage. This prevents a current from flowing through the parasitic capacitance thereby reducing and/or eliminating the effect of the parasitic capacitance on the transimpedance amplifier.

Abstract: In one embodiment, the present invention includes a circuit comprising an amplifier having an input terminal, an output terminal, a positive supply voltage, and a negative supply voltage. The amplifier is configured to have a first gain. A variable feedback circuit is coupled between the input terminal and the output terminal. The difference between the voltage on the output terminal and input terminal is received by the variable feedback circuit, which changes the gain of the circuit and reduces distortion.

Abstract: The present invention relates to a method of controlling a variable gain amplifier having at least one semiconductor switch, the amplifier having a first gain when the semiconductor switch is in a first steady state and a first gate voltage is applied to the semiconductor switch, and the amplifier having a second gain when the semiconductor switch is in a second steady state and a second gate voltage is applied to the semiconductor switch, whereby a sequence of third gate voltages is applied to the semiconductor switch to transition between the first and second gains.

Abstract: A gain-controlled transimpedance amplifier circuit that comprises a first gain unit including an input for receiving a first current and an output, a current source for providing a second current, a second gain unit including an input and an output, a first impedance unit of a first impedance coupled in parallel with the second gain unit, and a comparator including an output, a first input coupled to the output of the first gain unit, and a second input coupled to the output of the second gain unit.

Abstract: A high frequency variable gain amplification device 100 includes: a feedback circuit 103 capable of changing a feedback impedance to adjust the gain of an amplifier 101 in accordance with a control signal from a control device 200; and a current consumption adjustment circuit 102 capable of adjusting current consumption of the amplifier 101. The control device 200 controls the feedback impedance and the current consumption based on a desired signal power level and an undesired signal power level. If the desired signal power level exceeds a predetermined value, the control device 200 reduces the feedback impedance to increase the amount of a feedback signal, thereby allowing the amplifier 101 to operate with low gain so as to prevent the distortion characteristic from being reduced and to reduce the current consumption.

Abstract: The invention relates to a VGA stage having a novel circuit configuration for amplifying/attenuating a differential input signal which is transmitted via a transmission line (H). The VGA stage comprises an operational amplifier (OPV1, OPV2), which is connected as shunt feedback, for amplifying the input signal; a string of resistors (R01, R01?) for attenuating the signal; and a control device (2) for switching the string of resistors (R01, R01?).

Abstract: An amplifier circuit for converting the current signal from an optical receiving element into a voltage signal. The amplifier circuit includes a transimpedance amplifier having a differential amplifier and a feedback resistor, a first adjustable resistor which is connected in parallel with the feedback resistor and whose resistance value is defined by a first control signal, and a series circuit connected in parallel with the feedback resistor. The series circuit includes a first capacitor and a second adjustable resistor, whose resistance value is defined by a second control signal. The two adjustable resistors are preferably formed as MOS resistors and have the same control signal applied to them. The amplifier circuit permits the provision of a high dynamic range during the operation of a transimpedance amplifier.

Abstract: A selectable-gain amplifier selectively couples different capacitors and feedback networks to a gain stage to provide operating characteristics that may include constant bandwidth operation. An interpolated VGA includes pairs of gm cells with cross-connected outputs and may include output cascodes. A dual-rank interpolator utilizes a correction current with a second-order temperature characteristic which may compensate for temperature effects in the transistor ranks.