Abstract: A crystal oscillator drive circuit controls the maximum amplitude of the drive signal to a crystal by limiting the bias current of a gm cell which senses the oscillation amplitude of the crystal. The bias current is commutated by the gm cell responsive to the crystal oscillation. The commuted current is converted to a single-ended current by a current mirror. An output stage converts the current to an output voltage having a voltage swing that is determined by the resistance of a load resistor. The output voltage is then fed back to drive the crystal through a positive feedback path. The output voltage swing and the drive signal to the crystal are limited by the bias current of the gm cell. A fully complementary implementation of the drive circuit includes two complementary gm cells, two current mirrors, and an output stage having two load resistors.

Abstract: An oscillator circuit, having an inverter with input and output terminals interconnected through a feedback resistance, operates in two modes. In a first mode, the input and output terminals are coupled to an external crystal resonator. In a second mode, an external clock signal is supplied to the input terminal. In the second mode, the input terminal is disconnected from the output terminal, and in addition, the output-drive capacity of the inverter is reduced, or the output terminal of the inverter is held at a fixed potential.

Abstract: A multi-stage apparatus used as a voltage controlled oscillator. Each stage includes a first complementary differential current switch and a second complementary differential current switch with a second set of complementary differential current switches having a first complementary differential current switch and a second complementary differential current switch, the two sets of complementary differential current switches are connected in a push pull arrangement. In this arrangement, the outputs of the first complementary differential current switch of the first set of complementary differential current switches and the first complementary differential current switch of the second set of complementary differential current switches are connected with the input of the second complementary differential current switch of the first set of complementary differential current switches.

Abstract: A CMOS inverter capable of reducing a through current therein including an E-type PMOS transistor, an E-type NMOS transistor and a D-type NMOS transistor. In the E-type PMOS transistor, the gate and the drain are connected to input and output terminals. In the E-type NMOS transistor, the gate and the drain are connected to the input and the output terminals and the source to the ground. In the D-type NMOS transistor, the source is connected to the source of the E-type PMOS transistor, the gate to the ground, and the drain to a power source.

Abstract: A ring oscillator comprising an odd number of inverters connected in a ring, and apparatus for driving the ring oscillator so that it oscillates at a frequency slightly less than its maximum oscillating frequency such that harmonics of the oscillating frequency are suppressed.

Abstract: A relaxation oscillator of reduced complexity is described which can be constructed as part of a silicon integrated circuit. The current controlled oscillator includes complementary field effect transistors operating in enhancement mode. The drain of one FET is connected to the gate of the other FET and vice versa. The resulting CMOS circuit functions as a four-layer diode. A resistor is connected between the drains of both transistors. A storage capacitor is connected between the sources of both transistors. A current source is connected to charge the storage capacitor such that the frequency of an oscillator output signal is determined by the current generated by the current source.

Abstract: A ring oscillator for a semiconductor device comprising a ring oscillation circuit for generating a pulse signal according to a logic state of a control signal, the pulse signal having a predetermined period and a reduced operating voltage level, a comparator for comparing the pulse signal from the ring oscillation circuit with a reference voltage signal according to the logic state of the control signal and amplifying it in accordance with the compared result, and a driver for buffering an output signal from the comparator. The ring oscillation circuit includes an inverter chain for supplying the pulse signal with the reduced operating voltage level. According to the present invention, power consumption can significantly be reduced in the ring oscillation circuit.

Abstract: In a ring oscillator type VCO in which plural stages of inverter circuits are cascade-connected to each other so as to constitute a positive feedback loop, delay amounts for both a rising edge and a falling edge of an output signal from the inverter circuit are controlled to have the same delay amount by way of a control signal. These delay amounts of the rising edge and the falling edge are controllable in such a manner that the duty ratio of an oscillator output signal is not varied. Each stage of the inverter circuit is arranged by three-stage inverters made of load transistors and driver transistors, and the control voltage is applied to the load transistors of the two adjoining inverters among the three-stage inverters.

Abstract: A differential mode voltage controlled oscillator (VCO) includes an odd number of delay cells. Each delay cell has a pair of input terminals and a pair of output terminals with the input terminals of each delay cell being connected to the output terminals of a preceding delay cell in a ring. Each delay cell has a delay time for inverting a complementary pair of signals from which a clock signal is derived. A positive temperature coefficient voltage-to-current converter receives the control voltage of the VCO and controls the maximum currents (and therefore the delays) of the delay cells. A pair of cross-coupling transistors in each delay cell keeps the signals on the output terminals out of phase (complementary). The cross-coupling transistors have sizes which maximize gain of the delay cells at the threshold voltages of the cross-couple transistor and thereby increase output voltage swing at high frequencies.

Abstract: A voltage controlled oscillator (VCO) (2) provides an output signal which has a 50% duty cycle and a frequency which depends on the voltage of a control signal (V) supplied thereto. The VCO (2) comprises first (C.sub.L) and second (C.sub.R) capacitors and first (3) and second (5) circuits. Each of the first and second circuits comprises a current supply arrangement (10, 12, 14, or 18, 20, 22) coupled to a respective one of the capacitors (C.sub.L or C.sub.R) and to receive the control signal (V), and a Schmitt trigger (6 or 16) coupled to the respective current supply arrangement and to the other capacitor, which is not coupled to the respective current supply arrangement. Each current supply arrangement of the first and second circuits alternately charges and discharges the respective capacitor, in dependence on the switching of the respective Schmitt trigger, so that the VCO (2) oscillates between the charging of the first and the charging of the second capacitor.

Abstract: An electrically controlled oscillator circuit having multi-phase outputs with programmable frequency. The circuit includes a ring oscillator having a plurality of inverting stages. Each stage has an output which is connected to a switch that can be programmed to select one of a plurality of capacitors with different values to change the frequency range of the oscillator. Controlled current is fed to the stages to vary the frequency of the oscillator within a selected frequency range. Using capacitors to change the frequency range of the oscillator reduces variations of the oscillator output frequency.

Abstract: A differential inverter such as may be used in an oscillator circuit. The differential inverter is connected between first and second current sources. The differential inverter includes first and second single signal CMOS inverters connected in parallel between the first and second controlled current sources. Each of the current sources is a MOS transistor. A bias circuit is connected to the control gates of the MOS transistors and provides bias signals thereto, the bias circuit includes a variable current source with bias signals being generated in response to the current flow in the variable current source.

Abstract: A phase lock loop operates independent of temperature and process variation by digitally loading a VCO until reaching the desired operating frequency. The VCO reaches a high output frequency even under worst case processing by controlling multiple current mirrors to increase inverter switching current without slowing the response of the VCO to changes in loop node voltage. An Initialize-to-VDD circuit sets the loop node voltage to V.sub.DD so that the load control circuit need only increase loading to slow down the VCO to the desired operating frequency. A frequency range detector monitors the output frequency of the VCO and passes control signals to a load control circuit to activate digital loads and slow down the VCO to the desired operating frequency.

Abstract: A method and apparatus for switching between gain curves of a switched gain voltage controlled oscillator (VCO) 52, 52' or 52". In one form, the present invention uses a switched gain voltage controlled oscillator (VCO) 52, 52' or 52" which utilizes a ring oscillator. A Gain Control signal is used to select between using a high gain curve and using a low gain curve. The low gain curve is produced by selecting a high resistance path to either power or ground. The high gain curve is produced by selecting a low resistance path to either power or ground.

Abstract: An oscillator of the feedback amplifier type is described that employs a complementary bipolar transistors pair in which the collectors have a common connection with the output terminal. The oscillator operates from a single power supply, provides near rail-to-rail voltage swings, and hence may interface directly with CMOS logic. Because of the relatively low base-emitter voltages operation with supply voltages less than one volt is possible.

Abstract: A CMOS oscillator is disclosed using an inverter in which a pair of control terminals are employed to invoke various sized devices which control the flow of current. The inverter gain is determined by the size of the CMOS devices employed. A tuned circuit coupled to the inverter causes it to oscillate at the frequency of parallel resonance. The control terminals are coupled to the inverter invoke transistors that are sized as desired to establish the current flow and gain in the inverter. The current flow is controlled to optimize the gain of the inverter in terms of the frequency of oscillation. A Schmitt trigger can be employed to clean up the oscillator output for digital clock source applications.

Abstract: A CMOS crystal oscillator circuit for producing a 32 KHz clock signal operates at low power over a range of power supply voltages without overdriving the crystal. To accomplish this, the complementary MOS transistors in the oscillator inverter are supplied with operating current from a constant low current source. The constant low current is at an optimum value for crystal stability and power consumption and is independent of supply voltage variations. To ensure quick initial start-up of the oscillator circuit, a second current source is connected in parallel with the constant current source; and the second source initially is switched on for a pre-established time interval to supply significantly greater operating current to the oscillator inverter only during initial start-up of the oscillator. After this pre-established time interval, the second current source is rendered inoperative or non-conductive for the duration of the operation of the oscillator circuit.

Abstract: A CMOS ring oscillator includes an odd number of serially connected inverter stages with each stage comprising a CMOS transistor pair. The output of each stage is taken at the common terminal of the CMOS transistor pair with capacitive means shunting the output of each stage to circuit ground. The input of each stage is applied at the gate of the p-channel transistor. A fixed reference voltage, V.sub.REF, is applied to the gate of each n-channel transistor, whereby the discharge of voltage on the capacitive means through the n-channel transistor is independent of supply voltage.

Abstract: A ring oscillator circuit comprises a plurality of inverter states (301, 302, 303) connected in a series loop. Each stage has a voltage input (315, 315', 315") with an associated input capacitance and input threshold voltage, and a current output (316, 316', 316"). An active output circuit regulates the output currents so as to regulate the frequency of oscillation. A single reference circuit (307) can be used by more than one stage. The output circuit can vary the output currents to compensate for variable supply voltages. The oscillator can be used as part of a bias generator in an integrated circuit.

Abstract: Maximum frequency range in a VLSI voltage controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is implemented by an MOS transistor connected in source-follower configuration to minimize input capacitance, and the second stage is implemented by a bipolar transistor to provide the needed gain. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. The bias of an output buffer amplifier may be selectively shifted to maintain optimum duty cycle with the different triggering levels of diverse logic driven by the oscillator, and the bias may be dynamically driven by an analog signal to provide a duty cycle-modulated output.

Abstract: Maximum frequency range in a CMOS voltage-controllable crystal oscillator is obtained with a two-stage amplifier with feedback across both stages. The first stage is connected in source-follower configuration to minimize input capacitance, and the second stage provides the needed gain. To eliminate body effect, the source electrode and body of the second stage CMOS device are connected together. A bidirectional voltage limiter connected to a crystal node limits the oscillations to a symmetrical waveform. Changes in effective duty cycle caused by the different triggering levels of diverse logic connected to the oscillator output are compensated for by selectively shifting dc bias to a buffer amplifier.

Abstract: A crystal oscillator comprising a crsytal and an inverter amplifier which utilizes a current mirror to provide a voltage output having a frequency double the frequency of the voltage waveform present in the inverter amplifier.

Abstract: A temperature and voltage stable clock circuit for use in implantable cardiac pacers employs CMOS devices to minimize current drain. The circuit includes a timing capacitor which is alternately charged to and discharged between two established threshold voltages during respective charge and discharge cycles, the periods of which determine the clock frequency. To render the frequency of the clock circuit independent of changes in capacitor charge and discharge currents brought about by changes in temperature, the threshold voltage is increased with temperature so that the charge and discharge cycles remain constant. To render the frequency of the clock circuit independent of changes in the power supply voltage, a Wilson current source is used to maintain a constant charge and discharge current to the timing capacitor.

Abstract: An oscillator includes two transistors or like devices having their emitters connected to a common of a power source. The two transistors or like devices are interconnected with the base of the first connected to the collector of the second and the base of the second connected to the collector of the first. An inductance is placed across the base-collector connectors and a circuit through the oscillator is completed via a lead to one of the base-collector connectors.

Abstract: A circuit for supplying first and second currents to a load comprises two current generators for providing those currents during first and second time intervals and a resistance through which those currents flow. Two control potentials developed by two semiconductor junctions are applied across the resistance. First and second control circuits control the two current generators so that the first and second currents are provided during the first and second time intervals, respectively. The current supply circuit is useful in a multivibrator wherein the timing capacitor thereof is the load to which the first and second currents are supplied.

Abstract: An oscillator circuit adapted for use as a voltage controlled oscillator in which all of the transistors of the oscillator circuit are operated in non-saturated regions so that the minority carrier accumulation time does not affect the maximum operating frequency of the circuit. First and second current mirror circuits are coupled to opposed outputs of a differential amplifier circuit and are coupled to charge and discharge a capacitor with constant current in response to the states of the differential amplifier circuit. The differential amplifier circuit is provided with a hysteresis characteristic.

Abstract: A power inverter oscillator circuit has an output transformer with a primary winding, coupled in parallel with a capacitor, and the opposite ends of which are connected to the respective emitters of a PNP and a NPN transistors. The collector of the NPN transistor is coupled to the positive terminal and the collector of the PNP transistor is coupled to a negative terminal. In addition, a switching transformer is provided having a primary coil coupled at one end to one terminal and at the other end to the emitter of the transistor which is coupled to the other terminal. The switching transformer has two secondary coils or windings wherein one of the secondary coils is coupled between one terminal and the base of the transistor whose collector is coupled to the other terminal and the other secondary coil is coupled between the base of the other transistor and the remaining terminal.

Abstract: A pulsing oscillator employs a capacitor that is charged through a diode from a current-source circuit and repeatedly discharges through a PNP and an NPN transistor when the capacitor voltage reaches a predetermined voltage. Another transistor is connected in shunt with a diode and capacitor, and is turned on only when the first mentioned transistors turn on so as to divert the frequency controlling current from the current source away from the capacitor during the time of discharge. The output pulse width remains constant for all values of control current and large control currents may be used without risking the "latching-on" by large control currents of the transistors intended to carry the discharge current from the capacitor.

Abstract: An electronic timepiece wherein the timekeeping circuitry utilizes semiconductor-insulating substrate integrated circuitry for effecting high frequency operation is provided. The timepiece includes an oscillator circuit adapted to produce a high frequency time standard signal and is comprised of at least one inverter stage coupled to a high frequency time standard. A divider circuit formed of a plurality of series-connected divider stages produces a low frequency timekeeping signal in response to the high frequency time standard signal being applied thereto. A display is provided for displaying time in response to the timekeeping signal being applied thereto. The oscillator circuit, divider circuit and display include integrated circuit elements and at least the inverter stage of the oscillator circuit includes at least one complementary coupled pair of P-channel and N-channel conductive field-effect transistors having a semiconductor-insulating substrate construction.

Abstract: A voltage controlled oscillator which, for example, may be utilized in a phase locked loop, includes an odd number (n) of cascaded COS-MOS inverter stages with a feedback path coupling the output of the last stage to the input of the first stage to form a ring configuration. The ring configuration oscillates at a frequency f.sub.1 determined by the transconductances of the inverter stages and the shunt capacitances between the stages. Signals comprising impulses of current having frequency components at f.sub.1 and 2f.sub.1 flow through the power supply inputs of each of the stages as they successively are switched from one state to another. A frequency selective impedance path is coupled between a source of power supply voltage and the power supply inputs of each of the stages to develop a second signal having a frequency f.sub.2 equal to a multiple nf.sub.1 or 2nf.sub.1. The voltage applied to the commonly connected power supply inputs may be controlled to control f.sub.1 and, consequently, f.sub.2.

Abstract: An ultrasonic generator comprising an ultrasonic transducer having a natural frequency at which the dynamic admittance becomes maximum; a main circuit consisting of a switching circuit or first current regulator and a second current regulator connected in series to said switching circuit or first current regulator, the ultrasonic transducer being interconnected between an electrical source and the junction between said switching circuit or first current regulator and the second current regulator; a driving circuit for alternately driving the switching circuit or first current regulator and the second current regulator at a frequency equal to or substantially equal to the natural frequency of the ultrasonic transducer, thereby supplying the driving current thereto; and a feedback circuit for deriving an AC voltage in proportion to the magnitude of the driving current and feeding back this voltage to the driving circuit.

Abstract: A system for telemetering the performance of an implanted cardiac pacer incorporating a low power, low voltage, frequency-voltage sensitive pulse generator which supplies a pulse-interval-modulated telemetry output and includes an astable complementary multivibrator in combination with a voltage clipping feedback network.

Abstract: A low current, low voltage impulse generating system for cardiac pacers using a complementary multivibrator in combination with an RC network which operates in an astable, supply voltage insensitive mode to produce fixed rate pacing pulses.

Abstract: Disclosed is a highly stable CMOS oscillator for use as the master time reference in a wristwatch. A novel bias circuit comprising a CMOS pair and a relatively large resistor supply a bias voltage to the amplifier of the oscillator. The resistor can be made larger than normal because it is outside the oscillator feedback loop and does not reduce the amplifier open loop gain.

Abstract: An odd number of cascaded inverter stages are connected in a ring configuration. Each stage has a control terminal associated therewith. The signal propagation delay time through a particular stage is controlled by the application of control signals to the control terminal. The frequency of the output signal is determined by the delay per stage and the number of stages in the ring configuration. The output signal can be taken from a point between any two cascaded stages in the ring.