Abstract: A clock circuit includes a voltage-controlled oscillator (VCO) having a control input and a first clock output. The clock circuit includes a frequency-locked loop (FLL) having an FLL input and a control output, the control output coupled to the control input. A microelectromechanical system (MEMS) resonator-based oscillator has a second clock output. A multiplexer has a first multiplexer input, a second multiplexer input, a selection input, and a multiplexer output. The first multiplexer input is coupled to the first clock output. The second multiplexer input is coupled to the second clock output. The multiplexer output is coupled to the FLL input.

Abstract: A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

Abstract: An illustrative digital communications receiver and a fractional-N phase lock loop based clock recovery method provide substantially reduced sensitivity to nonlinearities in any included phase interpolators. One receiver embodiment includes: a fractional-N phase lock loop that provides a clock signal; a phase interpolator that applies a controllable phase shift to the clock signal to provide a sampling signal; a sampling element that produces a digital receive signal by sampling an analog receive signal; a timing error estimator that produces a timing error signal; a first feedback path coupling the timing error signal to the phase interpolator to minimize a phase component of the estimated timing error; a second feedback path coupling the timing error signal to the phase interpolator; and a third feedback path coupling the timing error signal to the fractional-N phase lock loop, the second and third feedback paths minimizing a frequency offset component of the estimated timing error.

Abstract: A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

Abstract: A circuit includes an oscillator having a driver and a resonator. The driver receives a supply voltage at a supply input and provides a drive output to drive the resonator to generate an oscillator output signal. A power converter receives an input voltage and generates the supply voltage to the supply input of the driver. A temperature tracking device in the power converter controls the voltage level of the supply voltage to the supply input of the driver based on temperature such that the supply voltage varies inversely to the temperature of the circuit.

Abstract: In the frequency calibration circuit, the digital phase-locked-loop circuit repeats a calibration operation involving outputting the digital control signal corresponding to a time difference between the first clock signal which is input from the first oscillator and has a first frequency accuracy, and the second clock signal which is input from the second oscillator and has a second frequency accuracy lower than the first frequency accuracy, changing the capacitance of the discrete type capacitor bank in accordance with the digital control signal using the second oscillator as a digital control oscillator, and changing an oscillation frequency of the second clock signal in accordance with the capacitance of the discrete type capacitor bank, thereby calibrating a phase of the second clock signal to a phase of the first clock signal.

Abstract: A frequency generation solution controls an oscillator amplitude using two feedback paths to generate high frequency signals with lower power consumption and lower noise. A first feedback path provides continuous control of the oscillator amplitude responsive to an amplitude detected at the oscillator output. A second feedback path provides discrete control of the amplitude regulating parameter(s) of the oscillator responsive to the detected oscillator amplitude. Because the second feedback path enables the adjustment of the amplitude regulating parameter(s), the second feedback path enables an amplifier in the first feedback path to operate at a reduced gain, and thus also at a reduced power and a reduced noise, without jeopardizing the performance of the oscillator.

Abstract: A method of eliminating spurs in measurements of an electrical response of a device under test (OUT) obtained uses a measurement instrument including a mixer and a receiver. The measurement instrument is configured to generate, via the mixer, an intermediate frequency (IF) signal for use by the receiver from a radio frequency (RF) signal and a local oscillator (LO) signal. Input is received from a user at the measurement instrument and includes start frequency and end frequency. Parameters for a frequency sweep are generated based on the input. A measurement for each frequency of the frequency sweep is calculated using averaging of a plurality of samples obtained at that frequency. Frequencies are identified within the frequency sweep at which spurs will occur due to the measurement instrument. The parameters for a frequency of the frequency sweep at which a spur will occur are modified so that a null for a measurement at the frequency falls on the spur.

Abstract: A method of determining a noise figure (NF) response of a device under test (DUT) comprises determining a frequency response of a noise receiver over a first frequency range, measuring a gain of the DUT over a second frequency range encompassing the first frequency range, measuring output-noise power of the DUT over the second frequency range, determining an estimated gain of the DUT based on the frequency response of the noise receiver and the gain of the DUT over the first frequency range, and determining the NF response of the DUT over the second frequency range based on the estimated gain and the output-noise power.

Abstract: A power amplifier circuit includes N (N is an integer equal to or greater than 2) power amplifier circuit cores, which in operation, amplify power of an input signal, N inductors, which in operation, are connected to the N power amplifier circuit cores, and ring-oscillator-type transconductance (gm) generation circuitry, which in operation, generates transconductance (gm) for compensating power loss of the N inductors.

Abstract: A digital input circuit includes a series connection of a current limiter and a switch having a switch control input coupled between a signal input and ground, and a logic level shifter coupled to the signal input and having a switch control output coupled to the switch control input and a signal output, where a maximum amplitude at the signal input is greater than a maximum amplitude at the signal output. A digital input method includes coupling an input signal to ground with a current limiter by closing an electronic switch, providing an output signal responsive to the input signal, where a maximum amplitude of the input signal is greater than a maximum amplitude of the output signal, by latching the output signal while the input signal is above a threshold voltage and opening the electronic switch after the output signal is latched.

Abstract: Various techniques for automatic amplitude control of an oscillator are described. An apparatus includes an oscillator circuit configured to generate an oscillating signal. The apparatus includes a feedback circuit configured to control a bias signal of the oscillator circuit to maintain a target peak amplitude of the oscillating signal based on a current-mode indicator of a peak amplitude of the oscillating signal and a reference current. The feedback loop includes a rectifier circuit configured to generate the current-mode indicator and a summing node configured to provide a bias control signal based on a difference between the current-mode indicator and the reference current. The feedback circuit may include a capacitor coupled to the summing node and configured to accumulate charge according to the difference. A magnitude of the current-mode indicator may be at least two orders of magnitude less than a magnitude of the current through an output node of the oscillator circuit.

Abstract: An electronic device and a method for control of an output amplitude of a Voltage Control Oscillator (VCO) in the electronic device is provided. The electronic device includes a first circuit configured to output a frequency signal corresponding to a control voltage, and a second circuit configured to generate control bits that control an amplitude of the frequency signal based on a comparison result between a peak voltage of the frequency signal and a reference voltage of the frequency signal.

Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.

Abstract: A system is disclosed for a voltage controlled oscillator (“VCO”) having a large frequency range and a low gain. Passive or active circuitry is introduced between at least one VCO cell in the voltage controlled oscillator and the voltage source for the VCO cell which reduces a gain value for the VCO to maintain stability of the system.

Abstract: A voltage-controlled oscillator with high loop gain includes a first transistor, a second transistor, an inductor, a third transistor, a fourth transistor and a gain circuit. The gain circuit provides a high loop gain in the voltage-controlled oscillator, which operates at wider tuning range but with low power consumption due to capacitance value provided by transistors thereof.

Abstract: According to an example embodiment, a device includes a resonant circuit configured and arranged to provide a peak current flow at a resonance frequency. A trimming circuit provides variable impedances to the resonant circuit and thereby changes the resonance frequency for the resonant circuit. A driver circuit is configured to generate a trimming signal that oscillates at a desired frequency. A switch circuit couples and decouples the driver circuit to the resonant circuit for driving the resonant circuit with the trimming signal. An amplitude detection circuit detects amplitudes for signals generated in response to the trimming signal being connected to the resonant circuit. A processing circuit correlates detected amplitudes from the amplitude detection circuit with different impedance values of the variable trimming circuit.

Abstract: A phase locked loop circuit includes a phase frequency detector, a control circuit, a charge pump, a loop filter, a supply circuit, a ring oscillator, a frequency divider and a voltage detector. The phase frequency detector generates a frequency-increasing signal and a frequency-decreasing signal according to a phase difference between an input signal and a feedback signal. The control circuit generates a first control signal and/or a second control signal according to the frequency-increasing signal and the frequency-decreasing signal. The charge pump generates a current signal according to the first control signal and/or the second control signal. The voltage detector monitors a supply voltage of the supply circuit, and controls the control circuit to generate only the second control signal so as to reduce the supply voltage if the supply voltage is greater than a high reference voltage.

Abstract: A radio frequency generator includes a power control module, a frequency control module and a pulse generating module. The power control module is configured to generate a power signal indicating power levels for target states of a power amplifier. The frequency control module is configured to generate a frequency signal indicating frequencies for the target states of the power amplifier. The pulse generating module is configured to (i) supply an output signal to the power amplifier, (ii) recall at least one of a latest power level or a latest frequency for one of the target states of the power amplifier, and (iii) adjust a current power level and a current frequency of the output signal from a first state to a second state based on the power signal, the frequency signal, and at least one of the latest power level and the latest frequency of the power amplifier.

Abstract: There are provided a control circuit for a digitally controlled oscillator and a control apparatus for a digitally controlled oscillator using the same. The control circuit for a digitally controlled oscillator includes: a peak detection circuit detecting amplitude of a signal output from the digitally controlled oscillator; and a transconductance control circuit comparing an output of the peak detection circuit with a predetermined reference signal to control a transconductance value of a negative transconductance circuit included in the digitally controlled oscillator.

Abstract: Provided is a temperature compensated oscillator includes an oscillation circuit for oscillating an oscillator. In the oscillator, when an oscillation frequency is changed by a second control signal after being controlled by a first control signal, variation in the oscillation frequency due to a second control signal is set to a fixed amount. The oscillation frequency of the oscillator is controlled on the basis of both the first control signal and the second control signal, but an oscillation amplitude adjusting section is also added, the oscillation amplitude adjusting section allowing the oscillation amplitude of the oscillator to be changed by the second control signal. The oscillator thus allows a fixed amount of oscillation frequency control over a wide range (full range) of oscillation frequency control due to the first control signal.

Abstract: According to one embodiment, a phase locked loop (PLL) circuit includes an application unit, a correlator, an integrator and a power supply noise canceller. The application unit applies the test signal to a power supply voltage. The correlator extracts a frequency error signal as a monitor signal and calculates a correlation value for the test signal and the monitor signal to generate a correlation signal. The integrator integrates the correlation signal to generate an integral signal. The power supply noise canceller provides a cancellation gain corresponding to the integral signal to the power supply voltage to which the test signal is applied, to generate a control signal.

Abstract: The disclosed embodiments provide a resonant oscillator circuit. The resonant oscillator circuit includes a clipping mechanism configured to clip an output voltage of a signal pulse generated by the resonant oscillator circuit to a predefined constant level. The resonant oscillator circuit also includes a feedback path configured to return energy from the clipping mechanism to an input of the resonant oscillator circuit.

Abstract: A method and circuitry for calibrating the gain of a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a comparator configured to provide a first indication if the VCO gain is not within the specified gain range, and a second indication if the VCO is within the specified gain range. The circuit further includes a control unit configured to, upon occurrence of at least a first cycle of a clock signal, cause adjustment of the VCO gain responsive to receiving the first indication. For each one or more successive cycles of the clock signal, the control unit is configured to cause corresponding adjustments of the VCO gain until the comparator provides the second indication. The control unit is configured to discontinue adjustments to the VCO gain responsive to receiving the second indication.

Abstract: Methods and apparatus for tuning devices having resonators are described. Phase shifters are included in the circuits and used to shift the phase of the output signal(s) of the resonators. In some implementations, the phase shifters are configured in a feedback loop with the resonators. One or more of the apparatus described herein may be implemented as part, or all, of a microelectromechanical system (MEMS).

Abstract: An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Abstract: A circuit includes a controllable oscillator and a controller coupled to the controllable oscillator. The controller is configured to provide a current control and a gain control to the controllable oscillator. The gain control is configured to change a gain of the controllable oscillator during a calibration process.

Abstract: Devices are provided comprising oscillator circuits coupled to a supply voltage via an adjustable resistance. Corresponding methods to control adjustable resistances are also provided.

Abstract: Methods and systems are disclosed that utilize digital control loops to control an amplitude level for output signals generated by crystal oscillator circuitry. The disclosed embodiments utilize multiple selectable current drive circuits to control the amplitude level of the output signals from crystal oscillator circuitry. The current drive circuits are selectably used, or not used, to provide a bias current to the crystal oscillator circuitry based upon a multi-bit digital control signal. The multi-bit digital control signal can be generated, for example, by control circuitry that compares the oscillator output signal to a reference output signal level.

Abstract: A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connected to the input of the VCO buffer and the gate of a p-type metal-oxide-semiconductor field effect (PMOS) transistor. The circuit further includes a first switch connected to the first capacitor and the gate of the PMOS transistor. The circuit also includes a third capacitor connected to the input of the VCO buffer. The circuit further includes a fourth capacitor connected to the input of the VCO buffer and the gate of an n-type metal-oxide-semiconductor field effect (NMOS) transistor. The circuit also includes a second switch connected to the third capacitor and the gate of the NMOS transistor.

Abstract: A limiter circuit in a voltage controlled oscillator (VCO) includes a first control circuit, a second control circuit and a driving circuit having a pull-up transistor and a pull-down transistor. The first control circuit generates a first driving control signal for controlling the pull-up transistor based on an AC input signal and a first DC bias voltage. The second control circuit generates a second driving control signal for controlling the pull-down transistor based on the AC input signal and a second DC bias voltage. The driving circuit generates an output signal based on the first driving control signal and the second driving control signal. The output signal swings between a first voltage at the pull-up transistor and a second voltage at the pull-down transistor.

Abstract: According to one embodiment, an oscillator circuit includes a first comparator circuit, a second comparator circuit, a first voltage control circuit, a second voltage control circuit, a clock generation circuit. The first comparator circuit is configured to compare a first voltage with a first threshold voltage to generate a first comparison result. The second comparator circuit is configured to compare a second voltage with a second threshold voltage to generate a second comparison result. The first voltage control circuit is configured to decrease the first voltage by a first voltage value in synchronization with timing when the first comparison result changes. The second voltage control circuit is configured to decrease the second voltage by a second voltage value in synchronization with timing when the second comparison result changes.

Abstract: An apparatus for generating an oscillating signal including an oscillator configured to generate the oscillating signal, a controller configured to generate a control signal that controls a characteristic (e.g., amplitude or frequency) of the oscillating signal, and a power supply configured to supply power to the oscillator as a function of the control signal. The power supply may be configured to supply power to the oscillator as a function of the amplitude or frequency of the oscillating signal to improve power efficiency.

Abstract: An amplitude control circuit includes a pair of peak detectors. The pair of peak detectors are responsive to a voltage reference generator. The amplitude control circuit is configured to be responsive to an oscillating signal of a crystal oscillator and configured to generate a control signal to control an amplitude of the oscillating signal.

Abstract: A method may include synchronizing an output of a phase-locked loop to a signal received at its input. The method may further include suppressing emission at a potentially problematic channel by applying at least one of a first gain and a first resistance of the phase-locked loop for a communication at the potentially problematic channel, wherein at least one of the first gain and the first resistance are different from a second gain and a second resistance applied for communications at channels other than potentially problematic channels.

Abstract: An apparatus for generating an oscillating signal including an oscillator configured to generate the oscillating signal, a controller configured to generate a control signal that controls a characteristic (e.g., amplitude or frequency) of the oscillating signal, and a power supply configured to supply power to the oscillator as a function of the control signal. The power supply may be configured to supply power to the oscillator as a function of the amplitude or frequency of the oscillating signal to improve power efficiency.

Abstract: A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below ?80 dBc.

Abstract: In a voltage controlled oscillation circuit including a cascade connection of a voltage-to-current conversion circuit (310) for generating an input voltage converted current which is a current corresponding to an input voltage and a current controlled oscillation circuit (120) of which an oscillation frequency varies according to the input voltage converted current, the voltage-to-current conversion circuit (310) includes a first current source for outputting a current in proportion to the input voltage and a plurality of second current sources for outputting a current in proportion to a voltage obtained by shifting the input voltage. Then, a current obtained by adding a current output from the first current source and currents output from the plurality of current sources is output as the input voltage converted current to the current controlled oscillation circuit (120).

Abstract: A gain control system comprises a reference stage, a bias replication stage, an operational amplifier, an automatic gain control block, a gain stage, and a crystal oscillator in one embodiment. A negative feedback loop is formed by portions of the operational amplifier, the replica biasing stage, the gain stage, and the automatic gain control stage. The negative feedback loop operatively controls an amplitude of oscillation in the crystal oscillator. The automatic gain control block produces output currents at reference levels in proportion to an input current source. The output current reference levels provide a corresponding yet independent scaling of currents in the bias replication stage and the gain stage. By the scaling capabilities provided a high common mode of voltage is provided between the crystal oscillator and the voltage reference section while stable oscillating characteristics are provided over a broad frequency range.

Abstract: An oscillator device having an oscillation system including an oscillator and a resilient supporting member, a driving member configured to supply a driving force to the oscillation system based on a driving signal, a detecting member configured to detect at least an oscillation amplitude of the oscillator, a driving amplitude control unit configured to control at least a driving amplitude of the driving signal, and a driving frequency control unit configured to control a driving frequency of the driving signal to be supplied to the driving member, wherein, in a state in which the driving amplitude control unit controls the driving amplitude of a driving signal so that the oscillation amplitude to be detected becomes equal to a target value, and on the basis of information including driving frequencies in different driving states being driven with driving signals of these driving frequencies as well as the controlled driving amplitude, the driving frequency control unit acquires, as a resonance frequency of t

Abstract: Methods and apparatus for tuning devices having resonators are described. Phase shifters are included in the circuits and used to shift the phase of the output signal(s) of the resonators. In some implementations, the phase shifters are configured in a feedback loop with the resonators. One or more of the apparatus described herein may be implemented as part, or all, of a microelectromechanical system (MEMS).

Abstract: There is provided an oscillator circuit including: a current source; a resonant unit; an oscillation amplification unit connected to the current source and connected in parallel to the resonant unit; a feedback resistor connected in parallel to the oscillation amplification unit; a switch unit having a first end connected to the current source side of the oscillation amplification unit; a replica circuit connected between a second end of the switch unit and a ground side of the oscillation amplification unit and having a configuration identical to a configuration of the oscillation amplification unit; and a level detecting unit that detects an input voltage of the oscillation amplification unit, and, when the detected input voltage is higher than a bias voltage level at a time of oscillation, cause the switch unit to allow a current from the current sources to bypass through the replica circuit.

Abstract: Aspects of a method and system for reduced clock feed-through in a phase locked loop are provided. In this regard, a control voltage for controlling a VCO may be generated via a filter comprising at least one switching element clocked via a clock booster circuit and comprising one or more thick oxide transistors to reduce clock feed-through. A first switching element of the filter may be a first transmission gate comprising thick oxide transistors. The first transmission gate may be part of a sample and hold circuit. A DC voltage on an input node of the sample and hold circuit may be periodically reset via a reset switching element, which may comprise thick oxide transistors. The reset switching element may be controlled via a clock booster circuit. The filter may also comprise a buffer having an input stage comprising one or more thick oxide transistors.

Abstract: A voltage controlled oscillator is provided to make it possible to enlarge a variable frequency range with an increase in a conversion gain suppressed. A converter (12) converts an input voltage to a first physical amount. A variable converter (13) outputs a second physical amount in accordance with each switch state of a switch group (13a). A variable converter (14) outputs a third physical amount in accordance with each switch of a switch group (14a) and an input voltage when the input voltage is within a predetermined range. A variable frequency oscillator (15) outputs a signal with a frequency in accordance with the first, second and third physical amounts.

Abstract: A temperature-compensated-resistance (TCR) circuit, which may be part of an integrated circuit, is provided. The TCR circuit consists of two resistors and a diode. The two resistors are connected in parallel and the diode is connected in series with one of the resistors. The two parallel legs of the TCR circuit may be connected to a reference voltage source, such as a ground. No specialized devices, such as bipolar transistors, Zener or Schottky diodes, or specially-processed resistors, are required by the TCR circuit. The resistors and the diode of the TCR circuit may be chosen to adjust for temperature variations in the resistance values of the resistor, leading to a negative, zero, or positive temperature coefficient of resistance for the circuit. A phase-locked loop (PLL) circuit is described as an application of the TCR circuit.

Abstract: A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal.

Abstract: An oscillator signal stabilization method is provided for a radio transceiver, for example. In the present stabilization method, amplitude variation of a radio frequency oscillator signal generated by a frequency-adjustable oscillator signal generator is stabilized in an adaptive compensation circuit having adjustable compensation parameters. The stabilized oscillator signal is fed from the compensation circuit to one or more frequency dividers for frequency division. The compensation circuit is configured to stabilize signal variations caused by component non-idealities and, thereby, prevent undesired frequency division errors in the frequency dividers.

Abstract: Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.

Abstract: A PLL circuit comprising an oscillation unit, a frequency division unit, a phase comparison unit, and a generation unit comprises a switching unit that switches between a first state in which a control voltage output from the generation unit is input into the oscillation unit and a second state in which a reference voltage is input into the oscillation unit; and a correction unit that, in the second state, compares the control voltage output from the generation unit with the reference voltage, and corrects a frequency at which the oscillation unit oscillates with respect to a voltage input into the oscillation unit, such that the control voltage output from the generation unit is equivalent to the reference voltage.

Abstract: A oscillating member device comprises: an oscillation system containing of a oscillating member and an elastic support, a driver unit for supplying a driving force to the oscillation system according to a driving signal, a waveform generator for generating periodic signals at a prescribed frequency, a driving signal generator for generating the driving signals in accordance with the periodic signals and an amplitude control level, and a oscillating amplitude detector for detecting a oscillating amplitude of the oscillating member; and practicing a control loop for controlling the amplitude control level according to a difference between a target oscillating amplitude and a detected oscillating amplitude detected by the oscillating amplitude detector, and the gain thereof; the oscillating member device comprising a gain adjuster for adjusting a gain of the control loop, and the gain of the gain adjuster being set based on the amplitude control level in a state that the oscillating amplitude of the oscillating