Abstract: A method and device for frequency synthesizing, in which the digital frequency synthesizer includes a clock pair having two similar ring-oscillators to separately generate a search frequency and an output frequency, a frequency tracking unit, and a clock controlling unit. The frequency-search method includes two stages: one stage is the coarse search stage based on the "Prune-and-Search", and other stage is the fine search stage based on the "fixed-step" algorithm. In order to determine which search scheme is used to search the target frequency and to determine the lock status, two cost functions for search and lock-in are derived. These two cost functions define the search threshold and the lock threshold, and these thresholds define the cost window and the lock window. If the frequency error is higher than both the search and lock thresholds, a coarse search is activated to estimate the correct frequency.

Abstract: The present invention relates to methods and devices for such control and supervision of an oscillator signal from a controllable oscillator that is done mainly to control the frequency variation of the oscillator signal. According to the invention, the controllable oscillator is controlled by a controlling voltage, which in turn is modified by a correction signal, generated in a control loop. A time discrete representation of a secondary phase is generated in the control loop, the secondary phase corresponding to a frequency being the difference between the frequency of the oscillator signal and a constant frequency. A time discrete approximation signal is generated in dependence of the time discrete representation of the secondary phase. A time discrete error signal is generated in dependence of the time discrete approximation signal, the time discrete error signal indicating the difference between the actual frequency slope of the oscillator signal and a desired frequency slope.

Abstract: An integrated circuit (11) has a frequency detection circuit (22) which provides one or more digital signals (50) to a current source (26) based upon a detected frequency of operation of a generated reference clock (48). The signals (50) allows the current source (26) to change its operational state between two or more discrete current output levels in a digitally-controlled manner. Using signals (50), a high current output level can selected and provided by the current source (26) to the external oscillator circuit (16) during a start up mode to ensure that the integrated circuit (11) can start up in an optimally reduced time period. After a start up operation is complete, the signals (50) can then be used to switch the current source (26) into a lower current operational mode whereby electromagnetic interference (EMI) effects are reduced during the normal modes of operation occurring after start up.

Abstract: A frequency control apparatus controls the frequency of an output signal thereof in synchronism with an externally input timing signal. A variable frequency oscillator generates the output signal such that the output signal has a frequency thereof variable in response to a control signal input to the variable frequency oscillator. An input device receives the timing signal. A checking device checks a monitor amount variable in response to the frequency of the output signal from the variable frequency oscillator, in timing in which the timing signal is input. A calculating device calculates a difference between the checked monitor amount and a predetermined desired amount. A control device controls the control signal input to the variable frequency oscillator such that the calculated difference becomes zero.

Abstract: A source for a linear homodyne transceiver that generates repeated linear chirps. A YIG oscillator with a main coil and an FM coil receives a basic linear current ramp at the main coil to generate a chirp. The FM coil is coupled to receive a PLL error signal. The PLL receives a sample of the output signal from the YIG oscillator at one input and a linear chirp reference signal at the other input generated by a DDS chirp generator. Any variation between the linear chirp frequency at any instant and the actual frequency output by the YIG is corrected by an error signal to the FM coil to correct for nonlinearities of the YIG caused by variations in the chirp rate, the rate of change of frequency per second per chirp, temperature variations and microphonics.

Abstract: A frequency standard generator for generating a high accuracy reference frequency by synchronizing a high accuracy atomic frequency standard or equivalent thereof and minimizing a phase difference between the generated reference frequency and the received atomic frequency standard.

Abstract: A system for compensating for reference frequency drift in a communications system. The inventive system includes a frequency source for providing a reference frequency. An error determination circuit determines if the reference frequency is within a predetermined range of a desired reference frequency and provides an error signal in response thereto. A frequency correction circuit steps the reference frequency up and/or down by a predetermined amount in response to the error signal until the reference frequency is within the predetermined range of the desired reference frequency. In a specific embodiment, the predetermined amount is twice the short-term capture range of the reference frequency which corresponds to approximately four parts per million. The predetermined range is the short-term capture range or two parts per million. The predetermined range is dependent upon the reference frequency band in which the receiver can successfully receive and decode the receive signal.

Abstract: A method is described for the digital control of a phase-locked loop consisting in the separate estimation of both phase and frequency errors of the data source as compared with those of the local oscillator and in the separate and adaptive filtering of the two signals. The value of the VCO control voltage is calculated on the basis of the two filtered signals. The phase and frequency error estimation and the frequency and phase error filtering are carried out in such a way as to eliminate the time-varying random components titter and noise) without delaying the feedback signals, since the portion of the signals that varies with time because of the variation of the commands, is subtracted before estimations and filterings.

Abstract: A frequency stabilization circuit includes a local oscillator, a mixer, a level comparator, a frequency comparator, and a controller. The local oscillator outputs a local oscillation signal in accordance with a control voltage. The mixer converts a received radio frequency signal into an intermediate frequency signal using the local oscillation signal from the local oscillator. The level comparator compares a DC voltage corresponding to the intermediate frequency signal from the mixer with a reference voltage to determine whether the reception electric field level of the radio frequency signal is high or low. The frequency comparator compares the frequency of the intermediate frequency signal from the mixer with the frequency of the reference signal to output frequency difference information. The frequency comparator outputs previous frequency difference information when the comparison result of the level comparator indicates a decrease in reception electric field level.

Abstract: An apparatus and method for synthesizing low-noise, high stability, multi-frequency microwave signals is disclosed. The output frequencies of a lower frequency, low-noise, synthesizer are upconverted to higher microwave frequencies by mixing these frequencies with the output frequency of an ultra low noise microwave oscillator, determined by a very high Q resonator. Such resonators exhibit large frequency dependence on temperature, but the frequency of an ultra low noise microwave oscillator cannot be stabilized by phase-lock to a stable reference because of its very narrow voltage-controlled frequency tuning range, caused by the very high Q of the resonator. The microwave synthesizer output frequency stabilization is achieved by a novel phase-lock loop which uses the frequency tunability of a low noise SAW oscillator to compensate for the frequency drift of the microwave oscillator.

Abstract: An integrated, crystalless oscillator includes a voltage controlled oscillator circuit for generating an output signal, and a frequency-locked feedback network to stabilize the frequency of the output signal. The frequency-locked feedback network includes a divide-down circuit and a frequency-controlled variable resistor, the divide-down circuit divides down the frequency of the output signal to produce a feedback frequency which is used to control the frequency-controlled variable resistor. The control voltage for the voltage controlled oscillator circuit is derived from the voltages across a fixed resistor and the frequency-controlled variable resistor. The voltages across these resistors drive an amplifier, with the output of the amplifier being the control voltage for the voltage controlled oscillator circuit.

Abstract: A phase locked loop for synchronizing decoding clocks with encoding clocks in a Moving Picture Experts Group (MPEG) system. The phase-locked loop circuit includes a voltage controlled oscillator for converting a decoding clock into an encoding clock, a register unit for storing multiplexing program clock reference signals, each input with a desired number of bits, a counter being initialized by a first program clock reference signal output from the register unit, thereby generating a local program clock reference signal, and a phase error control unit for combinationally operating the program clock reference signal stored in the register unit and the local program clock reference signal, thereby generating a phase error signal for controlling the voltage controlled oscillator.

Abstract: A monolithic oscillator having dual programmable fixed frequency outputs includes crystal-less oscillator circuitry utilizing frequency-locked feedback to generate ai signal having a select frequency, the frequency being stabilized over temperature and voltage by compensation circuitry associated with the crystal-less oscillator circuitry. A programmable prescaler is coupled to the crystal-less oscillator circuitry for varying the frequency of the signal generated by the crystal-less oscillator circuitry by a select amount. The monolithic oscillator further includes inputs for receiving an external signal, such as an external reference signal, or for connection to a crystal for providing an alternative frequency reference. A multiplexer is used to select either the external signal (or crystal) or the signal from the crystal-less oscillator circuitry to be used for the output signal.

Abstract: A frequency synthesizer circuit comprises a controller, a synthesizer and a voltage controlled oscillator are used to generate an oscillating signal in response to external commands. The synthesizer provides a lock detect signal to the controller when the synthesizer detects that the oscillating signal has reached a desired frequency following application of a load signal. A first timer, a second timer, and a counter are adapted to receive the load signal and the lock detect signal. The first timer provides a first measurement corresponding to an amount of time between the load signal and a first receipt of the lock detect signal. The second timer provides a second measurement corresponding to an amount of time between the load signal and a final receipt of the lock detect signal. The counter provides a count value corresponding to a total number of times that the lock detect signal is received inclusive of the first receipt and the final receipt of the lock detect signal.

Abstract: In an integrated crystal-less device that generates an output signal with the frequency of the output signal dependent at least in part on a resistive element, there is provided circuitry for providing compensation for the temperature coefficient the of resistive element, the circuitry includes a bandgap reference and a resistive network. The bandgap reference utilizes components having stable temperature coefficient to generate a first voltage, a reference voltage, and also to generate second voltage, a voltage proportional to absolute temperature. The resistive network includes two trimmable resistors, which are trimmed such that the resistive network in combination with the bandgap reference compensates for the absolute value of the resistive element in a selected temperature range.

Abstract: A canceler loop is used to provide negative feedback to a crystal oscillator to reduce the effects of shock and vibration on the spectral purity of the crystal oscillator. The canceler loop demodulates the output of the crystal oscillator and supplied a stabilizing voltage representative of the demodulated output to cancel frequency modulation induced by shock and vibration. The stabilizing voltage is used to cancel the noise sidebands of the frequency spectrum of the crystal oscillator output without tuning the center frequency.

Abstract: A 1-port tunable frequency discriminator that is incorporated into a frequency lock loop (FLL) for providing an improved FLL having reduced phase noise and settling times is provided. The invented 1-port tunable delay line discriminator reduces the phase noise generated by VCO's to approximately 105 dBc/Hz at 10 kHz, to better than 120 dBc/Hz at 100 kHz. The invention additionally reduces post tuning drift to less than 10 kHz after one microsecond. A secondary feedback loop, such as a conventional phase lock loop, can be incorporated into the invented FLL for providing phase and frequency coherency. The invention is formed by coupling a voltage controlled oscillator source (VCO) to a microwave signal detector and to an open ended delay line. When a microwave signal generated by the VCO reaches an end of the open ended delay line, a majority of the signal is reflected back along the line.

Abstract: A PLL synthesizer includes a reference oscillator, an controllable oscillator which generates an oscillation signal which varies in frequency according to a control signal, a phase comparator, and a loop filter. The loop filter includes an A/D converter, a digital filter, and a D/A converter. The digital filter removes high-frequency components from the output of the A/D converter according to setting data. The digital filter is set to a filter characteristic depending to a selected frequency of the oscillation signal. The digital output signal of the digital filter is converted to an analog signal which is used as the control signal of the controllable oscillator.

Abstract: A phase detector responsive to a first signal having a carrier frequency and a second signal close to the carrier frequency, including a carrier suppression circuit which produces a carrier suppressed signal from the first and second signals, and a mixer responsive to the carrier suppressed signal and the carrier frequency to produce an output signal corresponding to the phase difference between the first and second signals.

Abstract: An application specific integrated circuit (ASIC) including a phase-locked loop (PLL) circuit operably coupled to an internal clock and an external clock. The present PLL circuit includes an internal phase detector circuit, an internal charge pump operably coupled to the phase detector circuit, a loop filter operably coupled to the charge pump, and an internal programmable voltage-controlled oscillator 200, 300. The internal programmable voltage controlled oscillator includes a plurality of delay elements, which have a respective switch to turn-on the delay elements. A storage device having a plurality of outputs providing selected switch signals to the voltage oscillator program one of a plurality of center frequencies. Each of the outputs is operably coupled respectively to the delay elements through the respective switch. The switch isolates a first group of delay elements from a second group of delay elements.

Abstract: The output of a voltage-controlled oscillator (VCO), after being passed through a resonator having a single-peak characteristic, is detected by a detector. The output of the detector is sampled and held at a time instant that the control input voltage to the VCO reaches a maximum and also at a time instant that it reaches a minimum, and the difference between them is fed back to the control input of the VCO. In this way, the center frequency of the VCO is controlled so that it becomes equal to the center frequency of the resonator. In the case of a VCO as an FM modulator in an FM-CW radar, the sample-and-hold timing is derived from a clock signal based on which a triangle wave is generated. In the case of a VCO as an FSK modulator, the sample-and-hold timing is obtained by detecting a 0 and a 1 in input data.

Abstract: A method and apparatus for tuning the voltage controlled oscillator (VCO) (110) of a Phase Locked Loop (100) by comparing the VCO (110) voltage control line (116) to reference voltage (V.sub.1). With feedback, the voltage control line (116) is driven to the reference voltage level (V.sub.1).

Abstract: A synthesized oscillation circuit that can relax a limitation of the maximum operational frequency. A mixer (MX), a bandpass filter (BPF), an amplitude limiting amplifier (LIM), a phase detector (PD), a low-pass filter (LPF), and a voltage-controlled oscillator (VCO) are serially connected between a signal input terminal (IN) and a signal output terminal (OUT). The signal output terminal (OUT) is connected the mixer (MX) and the phase detector (PD). The bandpass filter (BPF) has a filtering characteristic which blocks the sum frequency component of the frequency component of an input signal from the signal input terminal (IN) to the mixer (MX) and the frequency component of an output signal from the voltage-controlled oscillator (VCO) to the mixer (MX), but which passes the difference frequency component between them.

Abstract: The system includes various circuit units each having a capacitor and a charging circuit for defining a quantity depending upon the ratio (I/C) between the charging current and the capacitance of the capacitors. In order to compensate automatically for deviations of the actual capacitances from the nominal capacitances due to fluctuations in the parameters of the integrated-circuit manufacturing process, the system has a phase-locked loop which uses one of the circuit units as an adjustable oscillator, and current transducer means which regulates the charging currents of the capacitors of the circuit units in dependence on the regulated charging current of the capacitor of the oscillator, or the error current of the PLL loop.

Abstract: A semiconductor integrated circuit device including input and output registers, a data-processing circuit block disposed between the registers, a first PLL circuit for supplying a first output clock signal to the input register in response to an input clock signal, and a second PLL circuit for supplying a second output clock signal to the output register in response to the input clock signal. The input register transfers a data signal stored therein to the output register in response to the first output clock signal. The output register stores the data signal and transfers it to another device in response to the second output clock signal. The first and second PLL circuits supply the first and second output clock signals to the input and output registers with keeping the phase differences constant, respectively.

Abstract: A digital phase detector which generates low jitter when the phase-locked-loop is in lock. A delay line, combined with an UP/DOWN phase detector causes substantial overlap in the UP and DOWN signals from the detector. When the PLL is in lock, the overlapping signals substantially cancel each other out, minimizing the variations in the output frequency. Two approaches are disclosed: one delaying the UP signal sufficiently to overlap the DOWN signal, the other using a delay and an exclusive OR gate to generate the DOWN signal.

Abstract: A circuit for transmitting data in asynchronous transfer mode includes two phase-locked loops associated with a transmission unit and a reception unit, respectively. Each PLL is provided with a voltage-controlled oscillator formed by an astable multivibrator. The reference current fixing the free oscillating frequency of the multivibrator that is associated with the reception unit corresponds to the frequency adjustment current of the multivibrator that is associated with the transmission unit. Each VCO includes a differential amplifier, connected as a voltage-to-current converter, receiving two voltages corresponding to the phase error of the loop with which it is associated, and providing a frequency adjustment current of its astable multivibrator.

Abstract: A variable divider in which a dividing number setting parameter can be set is provided in a reference oscillator. When a frequency setting parameter is selected so that a DDS will not output a spurious at a specified level or at a level higher than the specified level within an output band of an PLL in response to an output frequency from the PLL, both a conversion function setting parameter for a variable divider in the PLL and a dividing number setting parameter for a variable divider in the reference oscillator are adjusted so that the output frequency and the selected frequency setting parameter are satisfied.

Abstract: A PLL circuit has a feedback loop including a plurality of feedback circuits in parallel and a combining circuit. The feedback circuits receives an output signal of the PLL circuit and produce feedback output signals, respectively. The combining circuit combines the feedback output signals into a feedback signal which is used to be compared to a reference signal. The feedback circuits in parallel each divide a frequency of the output signal by a predetermined number and the combining circuit performs logical OR of the feedback output signals.

Abstract: A frequency detection circuit detects the frequency of a horizontal sync signal, and generates a mode switching signal corresponding to the detected frequency. A voltage-controlled oscillator constituting a PLL circuit has a plurality of oscillation modes obtained by dividing a frequency equal to an integer multiple of the frequency of the horizontal sync signal into a plurality of frequency ranges, and oscillates signals in the respective frequency ranges in accordance with control voltages output from a filter. The oscillation modes of the voltage-controlled oscillator are switched in accordance with the mode switching signal output from the frequency detection circuit. In the voltage-controlled oscillator, since the frequency range in each oscillation mode is narrow, the oscillation gain can be suppressed low, and a deterioration in jitter characteristics can be prevented.

Abstract: The phase-locked loop circuit provided by the present invention has a voltage-controlled oscillating circuit that has a nonlinear characteristic representing the relation between the control voltage applied to the voltage-controlled oscillating circuit and the frequency of a signal generated thereby. With a voltage lower than a predetermined voltage V1 applied to the voltage-controlled oscillating circuit, the rate of change in frequency with a change in control voltage applied to the voltage-controlled oscillating circuit is high. As a result, the loop gain of the phase-locked loop circuit can be changed at a high speed. The phase-locked loop circuit is designed so that, when a forcible pulling-in operation is started after the phase locked state is lost due to removal of an input signal, the control voltage applied to the voltage-controlled oscillating circuit is set at a low potential from the beginning in order to increase the loop gain.

Abstract: A digital phase detector 100 receives a limited input signal 108 and inputs it and a reference oscillation 112 into an EXCLUSIVE NOR gate 102. The output 110 of the EXCLUSIVE NOR gate 102 is input to a gated N-bit counter 104, which produces an N-bit representation of the magnitude of the phase 115 of the signal 108. A sign detector 105 determines the sign of the phase of the signal by sampling the resultant 110 and combines the magnitude of the phase 115 with the sign of the phase to produce a digital numeric representation of the phase of the signal 116.

Abstract: A phase lock loop of a synthesizer (143) is controlled by applying (506) modern optimal control techniques for a predetermined period in a computing engine (222), in response to an error being introduced into a signal of the phase lock loop, and by utilizing (510) classical control techniques for controlling the phase lock loop after the predetermined period.

Abstract: An oscillator supplies a signal of adjustable frequency to drive power ultrasonic actuators. The oscillator frequency is varied and the phase between the voltage and current of the signal is continuously measured. A computer determines the sign of the variation in the absolute value of the phase in the course of successive sampling cycles of predetermined duration and produces therefrom frequency correction signals for the oscillator. A frequency correction is applied to the oscillator in the same direction as the frequency correction applied previously if the variation in absolute value of the phase is negative, and in the opposite direction if the variation in absolute value of the phase is positive. If the variation in absolute value of the phase is zero, a frequency correction of random sign is applied to the oscillator.

Abstract: A horizontal synchronizing signal is applied as a reference signal and a voltage-controlled oscillator outputs a frequency signal on the basis of the frequency of the horizontal synchronizing signal. The period of the frequency signal is divided in accordance with a frequency-dividing value set in advance, the difference in frequency between the frequency-divided frequency signal and the horizontal synchronizing signal and the phase difference between them are obtained, and control is performed in such a manner that the frequency of the signal outputted by the voltage-controlled oscillator is decided in dependence upon the frequency difference. In an interval in which a vertical synchronizing signal turns off and the frequency of the horizontal synchronizing signal fluctuates, the input to the voltage-controlled oscillator is held fixed to prevent a fluctuation in the outputted display clock.

Abstract: A digital phase synchronous circuit includes a phase comparing circuit for outputting a count value according to the result of a phase comparison between an output signal and an externally input reference signal; a frequency regulating circuit for inputting an oscillation signal with a predetermined repetition frequency and controlling the repetition frequency according to the count value to output it as the output signal; and a controlling circuit for controlling the frequency regulating circuit to output the oscillation signal with the predetermined repetition frequency when the input of the reference signal breaks down.

Abstract: Frequency-dividing ratio data for selecting the oscillating frequency of a synthesizer are generated by a shift register, a certain number of switches connected to respective output terminals of the shift register, and an exclusive-OR gate for exclusive-ORing output signals respectively from the switches and feeding an output signal back to an input terminal of the shift register. A memory stores initial settings for the shift register and open and closed states of the switches.

Abstract: An apparatus and method are disclosed for improving the stability of the frequency of vibration of an oscillator signal produced by an oscillator circuit. In a preferred embodiment of the present invention, a quartz crystal resonator is one arm of a bridge which generates a bridge signal which varies in accordance with the vibrating frequency of the resonator. A synchronous demodulator responds to the bridge signal for producing an error signal which is converted into a control signal. A control circuit receives the control signal and changes its reactance when the resonator is no longer vibrating at its unperturbed resonance frequency so that the vibration frequency of the resonator connected to the control circuit is returned to its resonant frequency. An automatic level control circuit is also included for controlling the drive level of the signal exciting the resonator.

Abstract: Apparatus and methods for adjusting an electrical parameter of an electronic device, notably of an active implantable medical device such as a pacemaker or cardiac defibrillator, and an implementing monolithic integrated circuit for conducting the adjustment.

Abstract: A phase-locked-loop (PLL) has a current controlled oscillator (ICO) whose gain varies with its input current. The PLL also contains a charge pump that controls the input current of the ICO and therefore the output frequency of the ICO. The charge pump has a gain that is controlled by the ICO input current in a manner which linearizes the combination of charge pump and ICO. This results in a substantially constant loop gain for a PLL.

Abstract: This is an integrated timing circuit which can be formed on a microprocessor chip. The circuit uses an oscillator having a delay line and a variable delay element. The delay line and the delay element vary together to hold the velocity of signal propagation in the circuit substantially constant. The output, of the oscillator is coupled to one input of a comparator circuit. A series of inverter circuits, each of which has a respective variable delay are connected to the input of the oscillator and to a second input of the comparator circuit such that the comparator circuit senses the difference between the output signal of the inverter series and the output signal of the oscillator circuit to provide an error signal proportional to the sensed difference. A feedback loop is provided, to the variable delay means in said oscillator and to the inverter circuits to correct for the sensed difference, to establish a uniform and stable time standard at the output of the oscillator.

Abstract: A frequency oscillator and a frequency multiplier multiplying the signals from the oscillator contain inherent phase noise. A phase noise canceller removes phase noise, due to both the oscillator and the multiplier, by inserting a delay in one path and comparing phases of the delayed signal and the undelayed signal. This comparison may be either fed back to the tuning port of the oscillator or fed forward to a phase shifter which shakes off the phase noise. The delay may include a delay line, a cavity or any other suitable device which produces a phase shift. The phase noise canceller may also be designed to remove the total phase noise of the system, including additive phase noise from sources other than the oscillator and multiplier. The canceller may be calibrated and may be designed to reduce periodic response thereof.

Abstract: A heater controller for an atomic frequency standard provides accurate and stable temperature control for an assembly, such as a lamp assembly, by regulating a current flow through a heating device so as to maintain a substantially constant heating power output during start-up and by reducing the DC temperature errors of the system during normal operation. The heater controller includes an integrating amplifier which generates an amplified temperature signal based on the temperature of the lamp assembly. The heater controller further includes a device for receiving the amplified signal from the integrating amplifier and establishing a control voltage having an upper limit based on a voltage of the heater power supply.

Abstract: A controllable crystal oscillator of a receiver having a mixer producing an IF signal is controlled by a feedback loop that includes a phase detector. The IF signal is delayed by an odd multiple of .pi./2 and fed to one input of an exclusive-OR circuit, with the other input receiving the IF signal directly. The phase detection signal from the exclusive-OR circuit can be counted and converted to an analog voltage when the oscillator is a voltage controlled oscillator or it can be counted and used as a digital control signal when the oscillator is a data controlled oscillator.

Abstract: A PLL based microprocessor whose frequency may be adjusted by using a microprocessor clock control circuit. The microprocessor clock control circuit comprises a circuit for providing a slew rate limited overdampened PLL that continuously seeks a new frequency, a circuit for selecting a current target frequency for the microprocessor, a circuit for comparing the current target frequency to the current frequency setting of the microprocessor, and a circuit for adjusting the current frequency setting of the microprocessor to match the current target frequency.

Abstract: A frequency source for sequentially generating several output signals of different frequencies, which includes a permanent frequency table, a digitally stored frequency table and a single stabilization circuit for updating the digitally stored frequency table using the permanent frequency table and the output frequency. The source further includes the ability to convert the digitally stored frequency to the generated output frequency; and a clock for synchronizing the updating of the digitally stored frequency table. In certain embodiments the source further includes a sampler for sampling the output signal and a feedback mechanism for feeding back the output signal to the stabilization circuit.

Abstract: An RC oscillator includes an RC network for forming a time constant equal to the RC product. However, this RC time constant is not used in the manner of a typical RC network to set the frequency of oscillation. Instead, the RC oscillator disclosed herein includes a separate oscillator, such as a voltage-controlled oscillator (VCO), and uses the RC time constant to compare with the oscillator-generated period and to adjust the frequency of the overall RC oscillator circuit in accordance with the comparison. The RC oscillator is self-calibrating.

Abstract: A temperature-compensated piezoelectric oscillator includes a voltage-controlled piezoelectric oscillator, a first frequency divider, a second frequency divider, and a controller. The voltage-controlled piezoelectric oscillator has an output frequency controlled by a control voltage and oscillates the output frequency having a center frequency f.sub.0 at an ambient temperature of t.sub.0. The first frequency divider frequency-divides the output frequency from the voltage-controlled piezoelectric oscillator by N to output a first divided output frequency. The second frequency divider frequency-divides the output frequency from the voltage-controlled piezoelectric oscillator by M to output a second divided output frequency. The controller controls the control voltage to be applied to the voltage-controlled piezoelectric oscillator on the basis of a frequency difference between the first and second divided output frequencies upon a variation in ambient temperature of t.sub.

Abstract: An apparatus and method are provided for increasing the effective Q-value of an oscillator so that the required Q-value can be reached with the use of a low Q-value oscillator. In this apparatus and method, the FM noise is measured at the output of the oscillator by an FM detector and the output of the FM detector is fed back to the control input of the oscillator. By using this negative FM feedback, frequency variations in the oscillator output are suppressed by applying a correction signal at the control input of the oscillator. The amount of suppression depends on the loop gain of the FM feedback loop and the amount of suppression is proportional to the loop gain so that the effective Q-value of the oscillator is proportional to the loop gain.

Abstract: A phase-locked loop design is provide that can operate at a plurality of dissimilar supply voltages. By adjusting the frequency range of a PLL based on the power supply voltage, the same PLL design can operate at different supply voltages.