Abstract: A circuit for processing a logic input, including a first comparator capable of comparing the logic input with a first reference voltage and of providing a logic output at a first output logic level if the logic input is higher than the first reference voltage and otherwise at a second output logic level different from the first output logic level. The power supply of the first comparator and the first voltage reference are activated by the logic input.

Abstract: Disclosed is a method for generating an oscillating signal and an oscillator circuit.

Abstract: A low headroom oscillator operates at low supply voltages without the use of monostable circuits or flip flops. The oscillator operates in multiple states which allow for the charging and discharging of the capacitors alternately to enable the proper operating of the oscillator at low supply voltages without locking up.

Abstract: A slope compensation circuit includes an oscillator for generating a first clock signal having a reference frequency, a ramp signal generator for generating a ramp signal having a duty ratio of about 50% or higher based on the first clock signal, and a slope compensation signal generator for outputting a slope compensation current based on the ramp signal.

Abstract: Apparatus includes a single-pin input interface, which is operative to sense a voltage across a capacitor of a Resistor-Capacitor (RC) network in which the capacitor is repetitively charging and discharging so that the voltage oscillates as a function of time. A measurement circuit is coupled to measure time durations in which the capacitor is charging and in which the sensed voltage lies between first and second predefined thresholds. A clock generation circuit is coupled to generate an output clock signal having a frequency, and to adjust the frequency responsively to the measured time durations.

Abstract: There is provided a low-power relaxation oscillator.

Abstract: Noise generation is reduced further. Oscillation control circuit 11 generates a modulation signal modulating oscillation frequency of an oscillation signal generated by oscillation circuit 12 and outputs modulation signal to same. Preferably, the modulation signal fluctuates period of the oscillation signal sequentially. The oscillation circuit 12 is composed of a ring oscillator, for example, and the power supply voltage or power supply current of the ring oscillator is controlled to fluctuate sequentially by the modulation signal output from the oscillation circuit 11. Buffer 14 of charge pump circuit 13 generates signals /? and ? by the oscillation signal and drives capacitors C1 and C2 for supplying a higher voltage than the voltage of the power supply Vcc to gate of N-channel MOSFET Q1.

Abstract: A variable frequency multi-phase oscillator for providing multi-phase signals is disclosed. The variable frequency multi-phase oscillator includes a correlator, a plurality of delay cells, and a NOR circuit. Each delay cell includes a current supply, a capacitor, a comparator, a switch, and a logic unit. The plurality of delay cells generate the multi-phase signals that are phase correlated within a large frequency range. The frequency and duty cycles of the multi-phase signals are adjustable.

Abstract: A clock oscillator system for use in providing the switching regulator duty cycle control in a fixed frequency (no cycle skipping) operation is provided. In one embodiment, the circuit according to the invention uses an analog feedback loop to extend the switch ON time of the clock cycle by controlling the oscillator charging current and, thereby, increase the duty cycle. Preferably, this circuit can achieve very high switching duty cycle and/or very low switching duty cycle in a PWM switching regulator operated in very low drop-out operation when very high duty cycle is required or in other conditions when very low duty cycle is required.

Abstract: An apparatus that may be used to sense capacitance, as well as other functions. The apparatus includes a comparator circuit with hysteresis, a capacitor, and a current driver. The comparator circuit with hysteresis includes a first input and an output. The capacitor is coupled to the first input of the comparator circuit with hysteresis. The current driver is coupled to the output of the comparator circuit with hysteresis and to the capacitor. The current driver reciprocally sources and sinks a drive current through a terminal of the capacitor to oscillate a voltage potential at the terminal of the capacitor between a low reference potential and a high reference potential. The current driver is responsive to the output of the comparator circuit with hysteresis.

Abstract: The present invention provides a pulse width modulation (PWM) circuit comprising an PWM control circuit for setting an output signal to low when a logical level of a oscillation signal at a first input terminal changes from low to high, for resetting the output level to low in response to an effective input signal at a second terminal, a charge and discharge means for charging a first node (node1) when the output stays in low, for discharging the stored charge of node1 when the output stays in high, a comparator (C1) for outputting an output signal to the second terminal according to the first node signal and a first reference signal (Vref0), a discharge current controlling means for the stored charge on the first node, wherein the discharge current controlling means comprises a bias circuit 2 for controlling the discharge current based on constant current.

Abstract: A frequency adjustment circuit that maintains a target frequency even when frequency adjustment data of zapping circuit is changed by an external noise is offered. The frequency adjustment circuit includes a reset signal generation circuit, a frequency adjustment data latch circuit that latches and retains the frequency adjustment data ZP1 and ZP2 generated by a first zapping circuit and a second zapping circuit based on a latch clock ZCLK and a latch clock generation circuit that generates the latch clock ZCLK. The reset signal generation circuit generates a periodic reset signal ZRES that is synchronized with a rise of an enable signal EN generated from an interface circuit. The latch clock generation circuit generates the latch clock ZCLK that is synchronized with a fall of the enable signal EN.

Abstract: A programmable oscillator comprises a capacitor; a current generator couplable to said capacitor that generates a charging current of said capacitor; further comprising at least one resistance coupled to said capacitor; a comparator coupled to said capacitor for comparing a voltage at the terminals of said capacitor with a prefixed reference voltage and for generating an output signal; a first switch, controlled by said output signal, coupled to said capacitor that creates a current path able to facilitate the discharging of said capacitor.

Abstract: The problem of undesired power consumption in an oscillator during “stop” periods of a device is addressed by providing the oscillator in apparatus external to the device, the apparatus including a current sensor sensing current in a line between the apparatus and the device, the line communicating an oscillator “clock” signal. If the device enters a “stop” state the current flow during certain half-cycles of the oscillation is relatively low compared to the current flow in the “no-stop” state. In response to the relatively low current, the apparatus halts oscillation. Later, when the device exits the “stop” state, current flow increases in the line, and the apparatus resumes oscillation, thereby resuming the communication of the clock signal to the device.

Abstract: A continuously tunable function generator comprises a first function generator (10) with a triangle voltage generator including a comparator (24), which controls the commutation of a capacitor (14) from a charging phase to a discharging phase and vice versa in relation to an upper and lower preset amplitude value of the voltage at the capacitor (14). The triangle voltage (50) arising at the capacitor (14) is supplied to a second comparator (32) of another triangle voltage generator. The second comparator (32), commutates a second capacitor (38) of the same capacitance as the first capacitor from the charging phase to the discharging phase and vice versa. A reference voltage corresponding to the mean value of the upper and the lower amplitude value is applied to a second input of the second comparator. The charging currents and the discharging currents are identical, constant, and adjustable for changing the frequency of the triangle voltages.

Abstract: A relaxation oscillator comprising three cascaded operational voltage comparators is described. The on-time of the inventive circuit is established in accordance with a variable input element to the first operational comparator. The off-time is established by an RC network in the input circuit of the second operational comparator. The first and second operational comparators are interconnected so that the turning on or off of the second operational comparator affects the first operational comparator to cause it to also turn on or off.

Abstract: A sawtooth oscillator comprises a differential amplifier and first and second switching transistors driven into opposite conductivity states by the output of the differential amplifier. A charging capacitor is connected between the switching transistors and has one end connected in positive feedback fashion to one input of the differential amplifier.