Relaxation Oscillators Patents (Class 331/143)
  • Patent number: 9748935
    Abstract: Examples of a signal calculator include a voltage multiplier and a time divider. The voltage multiplier copies time information corresponding to a first voltage and generates a third voltage using a second current corresponding to a second voltage during a first period corresponding to the copied time information. The time divider generates an output according to a result of comparing a voltage generated by a first current on the basis of a voltage corresponding to a first time with a second voltage corresponding to a second time.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 29, 2017
    Assignee: Fairchild Korea Semiconductor Ltd.
    Inventors: Taesung Kim, Seunguk Yang, Youngbae Park
  • Patent number: 9678481
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a divided clock signal and a control signal in response to (i) an input clock signal and (ii) a configuration signal. The second circuit may be configured to generate an output clock signal in response to (i) the control signal and (ii) the divided clock signal. The second circuit may add a delay to one or more edges of the output clock signal by engaging one or more of a plurality of capacitances. A number of the capacitances engaged may be selected to reduce jitter on the output clock signal. The capacitances may be used each cycle to calibrate the output clock signal.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: June 13, 2017
    Assignee: INTEGRATED DEVICE TECHNOLOGIES, inc.
    Inventors: Song Gao, Brian Buell, Katherine T. Blinick
  • Patent number: 9645016
    Abstract: A temperature sensor generates a variable voltage whose level decreases linearly as a temperature increases, and compares the variable voltage with first and second reference voltages to generate first and second temperature codes to measure the temperature.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: May 9, 2017
    Assignee: SK hynix Inc.
    Inventor: Hyun Sik Jeong
  • Patent number: 9584132
    Abstract: Provided is a clock generator that includes a comparator in which characteristics of two input signals vary over time. A voltage controller, having a resistor and at least one constant current source, generates a direct current (DC) voltage proportional to an output current of the constant current source and a resistance value of the resistor. The comparator compares a ramp voltage generated by the voltage controller with the DC voltage.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: February 28, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Jin Kim, Jihyun Kim, Taeik Kim
  • Patent number: 9379691
    Abstract: Disclosed is a method for generating an oscillating signal and an oscillator circuit.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: June 28, 2016
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventor: Martin Feldtkeller
  • Patent number: 9356554
    Abstract: A relaxation oscillator reduces temperature sensitivity and phase noise at low offset frequency by periodically swapping a first current and a second current so that after the first current has been input to a first pair of circuits and the second current has been input to a second pair of circuits, the second current is input to the first pair of circuits and the first current is input to the second pair of circuits.
    Type: Grant
    Filed: July 12, 2014
    Date of Patent: May 31, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kai Yiu Tam, Ali Kiaei, Baher S. Haroun
  • Patent number: 9310775
    Abstract: To provide an analog electronic timepiece which prevents a crystal oscillation circuit from malfunctioning even if a battery voltage is lowered at motor loading. An analog electronic timepiece is equipped with a crystal vibrator, an oscillation circuit, a frequency division circuit, a constant voltage circuit, an output control circuit, and a motor. The analog electronic timepiece is configured in such a manner that the constant voltage circuit has a voltage holding circuit connected between a gate of an output transistor and a power supply terminal, and the oscillation circuit and the frequency division circuit are operated with a constant voltage generated by the constant voltage circuit as a power supply.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: April 12, 2016
    Assignee: SII SEMICONDUCTOR CORPORATION
    Inventors: Makoto Mitani, Kotaro Watanabe
  • Patent number: 9276584
    Abstract: An oscillator includes a compensated current source that adjusts an output current based on process, supply voltage, and temperature (“PVT”) variations of an integrated circuit device. The oscillator generates an output signal having a frequency based, in part, on the output current of the compensated current source. Accordingly, the output signal has a relatively low sensitivity to PVT variations.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: March 1, 2016
    Assignee: ViXS Systems Inc.
    Inventors: Chung Fai Au Yeung, Michael Cave
  • Patent number: 9250696
    Abstract: An apparatus comprises a reference voltage bias generator configured to generate a first reference voltage and a second reference voltage. During a low supply mode, the first reference voltage is equal to a supply voltage potential and the second reference voltage is equal to a ground potential. During a high supply mode, the first reference voltage is equal to a first fraction times the supply voltage potential and the second reference voltage is equal to a second fraction times the supply voltage potential. The apparatus further includes a reference voltage booster coupled to the reference voltage bias generator, wherein the reference voltage booster is configured to generate the first reference voltage and the second reference voltage with increased drive capability.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: February 2, 2016
    Assignee: STMicroelectronics International N.V.
    Inventors: Vinod Kumar, SaiyidMohammadIrshad Rizvi
  • Patent number: 9178497
    Abstract: New and highly stable oscillators are disclosed.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: November 3, 2015
    Assignee: Marvell World Trade Ltd.
    Inventors: Dennis Sinitsky, Tao Shui
  • Patent number: 9154027
    Abstract: A charge pump is regulated based up its output level. The regulation circuitry adjusts the frequency of the pump's clock based on feedback from pump's output. The pump's clock signal is generated by an oscillator whose frequency depends on a reference voltage level. The reference voltage level is dependent upon a regulation signal. In an example, a transistor whose gate is controlled by the regulation level is part of a series of elements in voltage divider, where the reference value is taken from a node of the divider.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: October 6, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Jonathan Huynh, Steve Choi, Jongmin Park
  • Patent number: 9126496
    Abstract: Method for adjusting a state-of-charge within an electrical energy storage device of a hybrid powertrain system includes monitoring a plurality of electrical energy storage device parameters and determining a discharge power capability of the electrical energy storage device based on the monitored plurality of electrical energy storage device parameters. If the discharge capability is less than a first threshold, a state-of charge adjustment mode is activated. The state-of-charge adjustment mode includes increasing a commanded state-of-charge to an elevated state-of-charge to increase the discharge capability to achieve the first threshold and maintaining the commanded state-of-charge at the elevated state-of-charge until the discharge capability achieves the first threshold.
    Type: Grant
    Filed: June 26, 2013
    Date of Patent: September 8, 2015
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Brenton J. Bergkoetter, William L. Aldrich, III, Brian L. Spohn, Todd Michael York, Andrew Meintz
  • Patent number: 9099994
    Abstract: In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: August 4, 2015
    Assignee: Silicon Laboratories Inc.
    Inventors: Axel Thomsen, Pavel Konecny, Xiaodong Wang
  • Patent number: 9019026
    Abstract: An oscillator module includes a first MOS transistor and a capacitor. The capacitor is coupled between a gate and source of the first MOS transistor. The drain of the first MOS transistor receives a first bias current and generates an oscillating output signal. A switching circuit operates in response to the oscillating output signal to selective charge and discharge the capacitor. A current sourcing circuit is configured to generate the bias current. The current sourcing circuit includes a second MOS transistor which has an identical layout to the first MOS transistor and receives a second bias current. A resistor is coupled between a gate and source of the second MOS transistor. The current sourcing circuit further includes a current mirror having an input configured to receive a reference current passing through the resistor and generate the first and second bias currents.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: April 28, 2015
    Assignee: STMicroelectronics (Shenzhen) R&D Co. Ltd
    Inventor: Hong Wu Lin
  • Patent number: 9019018
    Abstract: An integrated circuit (10) has an internal RC-oscillator (20) for providing an internal clock signal (CLI) having an adjustable oscillator frequency. The integrated circuit (10) further comprises terminals (101, 102) for connecting an external LC tank (30) having a resonance frequency and a calibration circuit (40) which is configured to adjust the oscillator frequency based on the resonance frequency of the LC tank (30) connected during operation of the integrated circuit (10). An internal auxiliary oscillator (46) is connected to the terminals (101, 102) in a switchable fashion and is configured to generate an auxiliary clock signal (CLA) based on the resonance frequency. The calibration circuit (40) comprises a frequency comparator (47) which is configured to determine a trimming word (TRW) based on a frequency comparison of the internal clock signal (CLI) and the auxiliary clock signal (CLA). The LC tank (30) to be connected is an antenna for receiving a radio signal.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: April 28, 2015
    Assignee: ams AG
    Inventor: Ruggero Leoncavallo
  • Patent number: 9007137
    Abstract: An oscillation circuit includes a condenser, a charging/discharging part configured to switch between charging and discharging of the condenser according to a control signal, a comparator configured to compare a voltage of the condenser with a reference voltage and output a comparison result signal, a flip-flop configured to be set or reset according to the comparison result signal, supply an output signal as the control signal to the charging/discharging part, and output the output signal as an oscillation signal, and a current control part configured to control an operating current of the comparator in correspondence with the voltage of the condenser.
    Type: Grant
    Filed: May 10, 2011
    Date of Patent: April 14, 2015
    Assignee: Mitsumi Electric Co., Ltd.
    Inventor: Fumihiro Inoue
  • Patent number: 8994428
    Abstract: A period signal generation circuit including a control voltage generator and a period controller. The control voltage generator selecting one of temperature-dependent voltages to output the selected temperature-dependent voltage as a control voltage. The first and second temperature-dependent voltages varying according to a temperature and the third temperature-dependent voltage is constant regardless of variation of the temperature. The period controller configured to determine an amount of a current discharging from an internal node in response to the control voltage and outputs a periodic signal whose cycle time is determined according to a level of an internal signal induced at the internal node.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: March 31, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hyun Ju Ham
  • Patent number: 8988157
    Abstract: An oscillation circuit includes an RS flip-flop for generating output signals based on a set signal and a reset signal, an electric-charge charge/discharge unit which has first and second capacitors and charges or discharges the first and second capacitors complementarily based on the output signals, a first comparator which compares a first voltage according to electric charge accumulated in the first capacitor and a first reference voltage and outputs the set signal, a second comparator which compares a second voltage according to electric charge accumulated in the second capacitor and the first reference voltage and outputs the reset signal, and a control unit for controlling a timing at which respective voltage levels of the first reference voltage and the first voltage match and a timing at which respective voltage levels of the first reference voltage and the second voltage match according to a frequency of the output signals.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takashi Tokairin
  • Patent number: 8981816
    Abstract: A multi-input voltage-to-frequency conversion circuit, includes: a multi-input operational amplifier amplifying one of multiple voltage signals in response to multiple control signals to generate an amplified voltage; a voltage-to-current converter converting the amplified voltage into a sensed current, and generating an oscillation current based on the sensed current and on an offset voltage that is associated with a predetermined frequency range corresponding to the one of the voltage signals; and a current-controlled oscillator generating, based on the oscillation current, a periodic pulse signal that has a frequency linearly proportional to the magnitude of the one of the voltage signals.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: March 17, 2015
    Assignee: Kun Shan University
    Inventor: Min-Chuan Lin
  • Patent number: 8981858
    Abstract: An apparatus includes a selection device to select a spreading profile from a plurality of spreading profiles, and an oscillation device to generate clock signals having different frequencies over time based on the selected spreading profile. A method includes selecting a spreading profile from a plurality of spreading profiles, and generating clock signals having different frequencies over time based on the selected spreading profile.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: March 17, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: David G Wright, Timothy Williams, Edward L. Grivna, Mohandas Palatholmana Sivadasan
  • Patent number: 8970313
    Abstract: Methods and circuits for CMOS relaxation oscillators are disclosed. A single capacitive element, a single current source and a switching network are utilized. A switching network of the oscillator allows both nodes of the capacitive element to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up, i.e. the inadvertent creation of a low-impedance path. The oscillator requires minimum silicon area, has an improved duty cycle, is particular useful for implementing lower frequency clocks and is enabled for smaller technology nodes, lower than 250 nm, due to lower supply voltage.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: March 3, 2015
    Assignee: Dialog Semiconductor GmbH
    Inventor: Tim Morris
  • Patent number: 8928421
    Abstract: A control circuit for reducing electromagnetic interference is provided. The control circuit includes a periodic signal generator and a modulation controller. The periodic signal generator adjusts a modulation periodic signal generated by the periodic signal generator, according to a feedback modulation signal. The modulation controller is coupled to the periodic signal generator, for receiving the modulation periodic signal, and adjusting a frequency of the received modulation periodic signal according to a plurality of delay periods set according to a plurality of control signals, and generating the feedback modulation signal.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: January 6, 2015
    Assignee: Macroblock, Inc.
    Inventors: Yu-Wen Cheng, Chung-Ta Tsai
  • Patent number: 8928420
    Abstract: A low current single chip oscillator timing circuit which includes a dual mode capacitor circuit having a larger capacitance mode and a smaller capacitance mode having a fixed ratio. The timing circuit also includes an oscillator circuit that uses the dual mode capacitor circuit as a part of its time base wherein the large capacitance mode is operated with low power consumption and as needed includes a circuit that generates a reference pulse, wherein the short pulse and the reference pulse are compared and the result is used for correction to the oscillator frequency to create a feedback loop.
    Type: Grant
    Filed: August 18, 2012
    Date of Patent: January 6, 2015
    Inventor: Dan Raphaeli
  • Patent number: 8922289
    Abstract: An oscillation circuit including a reference voltage generation circuit that adds a proportional-to-absolute-temperature (PTAT) output, which increases in proportion to an absolute temperature, to a complementary-to-absolute-temperature (CTAT) output, which decreases in proportion to an absolute temperature, to generate and output a reference voltage. The oscillation circuit generates an oscillation signal having a desired and fixed frequency.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: December 30, 2014
    Assignee: Spansion LLC
    Inventors: Kazuhiro Mitsuda, Kogi Okada, Suguru Tachibana
  • Patent number: 8922290
    Abstract: An example PWM includes a driver and a two-way oscillator. The oscillator includes, a first frequency adjust current source, a second frequency adjust current source, a capacitor, a switching reference and a comparator. The capacitor integrates a frequency adjust current by charging with the first frequency adjust current source. The capacitor subsequently integrates a second frequency adjust current by discharging with the second frequency adjust current source. The switching reference outputs a first reference voltage and a second reference voltage responsive to an oscillator signal. The comparator compares the output of the switching reference with a voltage on the capacitor. The first and second frequency adjust current sources vary the first and second frequency adjust currents to vary the frequency of the PWM signal to spread energy of switching harmonics over a frequency band and to reduce EMI.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: December 30, 2014
    Assignee: Power Integrations, Inc.
    Inventors: Jonathan Edward Liu, Giao Minh Pham
  • Patent number: 8912855
    Abstract: A relaxation oscillator is provided. A first current source provides a first current. A second current source provides a second current. A resistive element is coupled between the first current source and a ground. A capacitive element is coupled between the second current source and the ground. A comparator has a non-inverting input terminal, an inverting input terminal and an output terminal for outputting a compare result. A clock generator provides a clock signal according to the compare result. A switching unit alternately couples the non-inverting input terminal and the inverting input terminal of the comparator to the resistive element and the capacitive element according to the clock signal.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: December 16, 2014
    Assignee: Mediatek Inc.
    Inventor: Keng-Jan Hsiao
  • Patent number: 8907732
    Abstract: There is provided an oscillation frequency regulating circuit including: a measuring section that performs measurement based on an oscillation frequency of an oscillation circuit; a comparator section that compares a measurement value measured by the measuring section against a set comparison value over a set comparison duration; a setting section that sets a comparison value selected from a plurality of comparison values of different magnitudes and that sets in the comparator section the comparison duration according to the magnitude of the selected comparison value; and a regulation section that, based on the comparison result of the comparator section, regulates the oscillation frequency of the oscillation circuit such that the oscillation frequency that is measured by the measuring section becomes a target oscillation frequency.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: December 9, 2014
    Assignee: Lapis Semiconductor Co., Ltd.
    Inventor: Hirokazu Hosokawa
  • Patent number: 8902008
    Abstract: Aspects of the disclosure provide a circuit. The circuit includes a current generator, a capacitor, a comparator, a switch and a clock generator logic. The current generator is configured to generate a current proportional to a comparator threshold voltage by a ratio. The capacitor is configured to be charged by the current to have a capacitor voltage. The comparator is configured to compare the capacitor voltage with the comparator threshold voltage. The switch is configured to discharge the capacitor based on the comparison. The clock generator logic is configured to generate a clock signal based on the comparison, such that a frequency of the clock signal is a function of the ratio and is independent of the current and the comparator threshold voltage.
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: December 2, 2014
    Assignee: Marvell International Ltd.
    Inventors: Giuseppe De Vita, Alessandro Savo
  • Patent number: 8890630
    Abstract: An oscillator formed from low cost discrete semiconductors and passive devices creates a linear periodic ramp of constant frequency with ramp slope based on an external voltage signal. Parameters are stable over a wide range of temperatures and variations of transistor parameters that normally degrade in extreme environments. The oscillator period can be phase and frequency synchronized to an external clock source over a wide range of frequencies. The oscillator ramp generator phase can be synchronized on a cycle by cycle basis for incorporation in power converters employing spread spectral EMI reduction techniques, multi-converter systems employing clock interleaving for distribution bus filter optimization, and resonant mode converters employing zero voltage switching techniques. Oscillator ramp rate is independent of frequency and can be synchronized to DC (inhibit) for use in ultra low power burst mode power conversion.
    Type: Grant
    Filed: July 18, 2011
    Date of Patent: November 18, 2014
    Assignee: Crane Electronics, Inc.
    Inventor: Rodney Alan Hughes
  • Patent number: 8890629
    Abstract: An oscillator circuit with a comparator is provided, wherein the comparator has a supply input. A supply circuit supplies the comparator with a first current during a first section of an oscillator period of the oscillator circuit and with a second current greater than the first current during a second, different section of the oscillator period.
    Type: Grant
    Filed: July 18, 2012
    Date of Patent: November 18, 2014
    Assignee: Infineon Technologies AG
    Inventor: Josef Niederl
  • Patent number: 8878621
    Abstract: A semiconductor device includes: a resistance R whose resistance value varies in response to a substrate temperature variation; a resistance corrector that is coupled in series with the resistance R and switches its resistance value by a preset resistance step width to suppress a resistance value variation of the resistance R; a first voltage generator for generating a first voltage that varies in response to the substrate temperature; a second voltage generator for generating second voltages Vf1 to Vfn?1 for specifying the first voltage at a point when a switching operation of the resistance value of the resistance corrector is performed; and a resistance switch unit for switching the resistance value of the resistance corrector by comparing the first voltage and the second voltages Vf1 to Vfn?1.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Tomokazu Matsuzaki, Kazutoshi Sako
  • Patent number: 8872593
    Abstract: A technique for calibration of on-chip resistance (R) and capacitance (C) values using an on-board bypass capacitor may include configuring an on-chip switch to selectively couple an on-chip calibration circuit to an on-chip port. The on-chip calibration circuit may include an RC oscillator having an RC time constant (RCTC). The on-board bypass capacitor may be coupled to the on-chip calibration circuit, by using the on-chip port. The on-chip R and C values may be calibrated using the on-chip calibration circuit and the on-board bypass capacitor.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Mohyee Mikhemar, Hooman Darabi
  • Patent number: 8860514
    Abstract: A fractional-N divider supplies a divided clock signal. An adjusted divided clock signal is generated in a digital-to-time converter circuit having a delay linearly proportional to digital quantization errors of the fractional-N divider. The adjusted divided clock signal is generated based on first and second capacitors charging to a predetermined level. The charging of the first and second capacitors is interleaved in alternate periods of the divided clock. The charging of each capacitor with a current corresponding to respective digital quantization errors is interleaved with charging with a fixed current. A first edge of a first pulse of the adjusted divided clock signal is generated in response to the first capacitor charging to a predetermined voltage and a first edge of a next pulse of the adjusted divided clock signal is generated in response to the second capacitor charging to the predetermined voltage.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 14, 2014
    Assignee: Silicon Laboratories Inc.
    Inventors: Colin Weltin-Wu, Yunteng Huang, Manu Seth
  • Patent number: 8860518
    Abstract: A current-feedback operational-amplifier Based Relaxation oscillator provides oscillation based on a current feedback operation amplifier and two external resistors which exhibit a low output impedance terminal. This current-feedback operational-amplifier Based oscillator is used as a component for a capacitive, resistive and capacitive-resistive sensor electronic interfacing circuit.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: October 14, 2014
    Assignee: King Fahd University of Petroleum and Minerals
    Inventors: Muhammad Taher Abuelma'atti, Zainulabideen Jamal Khalifa
  • Patent number: 8860517
    Abstract: An oscillator circuit including a first capacitor provided with a first terminal; a resistor provided with a reference terminal; a first current generator provided with a connection terminal; a second current generator provided with a second connection terminal. Further, the circuit includes a switching matrix between the first and second generators and resistor and the at least one first capacitor.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: October 14, 2014
    Assignee: STMicroelectronics S.R.L.
    Inventor: Mauro Giacomini
  • Patent number: 8830006
    Abstract: An oscillator circuit includes a charge current source and first and second muxes. The first mux has a common node, a discharge node, a control node and a charge node coupled to the charge current source. The control node couples the common node to either the discharge or charge nodes. The second mux has a shared node, a reference node, a control node and a ground node coupled to ground. The second mux control node couples the shared node to either the reference or ground nodes. A capacitor is coupled between the common node and the shared node. A comparator has a non-inverting input coupled to the common node, an inverting input coupled to the reference node, and an output coupled to the first and second control nodes. A discharge current sink couples the discharge node to ground and an oscillator output is provided by the comparator.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: September 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jinglin Zhang, Yali Wang
  • Patent number: 8816788
    Abstract: A frequency generator with frequency jitter is disclosed. The frequency generator comprises a capacitor, a comparing unit, a charging and discharging unit, a delay unit, and a charging and discharging switch unit. The comparing unit is coupled to the capacitor and generates a charging and discharging control signal according to a voltage of the capacitor. The charging and discharging unit is coupled to the capacitor. The delay unit is coupled to the comparing unit and receives a delay signal. The delay unit delays the charging and discharging control signal according to the delay signal to generate a charging and discharging delay signal. The charging and discharging switch unit is coupled to the charging and discharging unit and the delay unit, and charges or discharges the capacitor according to the charging and discharging delay signal.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: August 26, 2014
    Assignee: Analog Vision Technology Inc.
    Inventor: Tzong-Honge Shieh
  • Patent number: 8803619
    Abstract: A relaxation oscillator for generating an output clock signal includes an RC circuit, a self-biased comparator stage, and a logic circuit. The RC circuit generates first and second comparator input signals that are provided to the self-biased comparator stage. The self-biased comparator stage includes first and second input stages and a voltage reference circuit. Each of the first and second input stages in conjunction with the voltage reference circuit forms a comparator, i.e., first and second comparators corresponding to the first and second input stages, respectively. The self-biased comparator stage generates first and second comparator output signals, based on the first and second comparator input signals. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
    Type: Grant
    Filed: January 30, 2013
    Date of Patent: August 12, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anand Kumar Sinha, Sanjay K. Wadhwa
  • Patent number: 8786375
    Abstract: Disclosed is a method for generating an oscillating signal and an oscillator circuit.
    Type: Grant
    Filed: June 9, 2011
    Date of Patent: July 22, 2014
    Assignee: Infineon Technologies Austria AG
    Inventor: Martin Feldtkeller
  • Patent number: 8786377
    Abstract: A variable frequency modulator including a compensation network, first and second pulse control networks and a linearity controller. The compensation network is configured to provide a compensation signal indicative of an output load condition. The first pulse control network is configured to initiate pulses on a pulse control signal and to adjust operating frequency based on changes of the compensation signal. The second pulse control network is configured to terminate the pulses on the pulse control signal based on a predetermined timing parameter. The linearity controller is configured to adjust timing of terminating the pulses based on a predetermined steady state operating frequency and an actual operating frequency to maintain modulator gain at a constant level.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Intersil Americas LLC
    Inventors: M. Jason Houston, Steven P. Laur, Rhys S. A. Philbrick
  • Publication number: 20140197897
    Abstract: New and highly stable oscillators are disclosed.
    Type: Application
    Filed: March 18, 2014
    Publication date: July 17, 2014
    Applicant: Marvell World Trade Ltd.
    Inventors: Dennis SINITSKY, Tao SHUI
  • Patent number: 8773210
    Abstract: A relaxation oscillator for generating an output clock signal includes a RC circuit, a bias generation stage, first and second comparator stages, and a logic circuit. The RC circuit generates first and second comparator input signals that are transmitted to the first and second comparator stages. The bias generation stage generates first and second bias voltages that are provided to each of the first and second comparator stages. The first and second comparator stages generate first and second comparator output signals, respectively, based on the first and second comparator input signals and the first and second bias voltages. The first and second comparator output signals are provided to the logic circuit that generates the output clock signal.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 8, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anand Kumar Sinha, Sanjay K. Wadhwa
  • Patent number: 8766731
    Abstract: The present invention is directed to an oscillator circuit comprising an oscillator input for providing an input signal, a first integrator circuit comprising a first integrator capacitor and a first integrator output, a comparator, a discharge circuit for discharging said first integrator capacitor once per cycle of said oscillator circuit, and an oscillator output for providing an output signal, wherein said oscillator circuit further comprises a second integrator circuit comprising a second integrator capacitor and a second integrator output, and wherein said oscillator circuit is arranged for allowing said input signal to be subsequently integrated by said first and second integrator circuit in an alternating manner, and for providing said integrated output signal of said first and second integrator circuit subsequently to said comparator in said alternating manner.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: July 1, 2014
    Assignee: Anagear B.V.
    Inventors: Petrus Johannes Maria Kamp, Hermanus Johannes Nijrolder
  • Publication number: 20140176250
    Abstract: In an embodiment, a method includes: during a first portion of a cycle of a clock signal generated by an oscillator, pre-charging a first capacitor of a first switched capacitor stage until a first comparator determines that a first node voltage of the first switched capacitor stage is greater than a first reference voltage at a first reference voltage node; applying a second reference voltage to the first reference voltage node; and responsive to a first edge of the clock signal, charging the first capacitor until the first comparator determines that the first node voltage is greater than the second reference voltage at the first reference voltage node.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Axel Thomsen, Pavel Konecny, Xiaodong Wang
  • Patent number: 8742858
    Abstract: Techniques and architectures corresponding to relaxation oscillators having output frequencies that are supply voltage independent are described. In a particular embodiment, an apparatus includes a relaxation oscillator having one or more capacitors and a compensation current circuit coupled to the relaxation oscillator. The compensation current circuit is configured to regulate current provided to the one or more capacitors of the relaxation oscillator in response to changes in a supply voltage provided to the compensation current circuit and to the relaxation oscillator.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies AG
    Inventors: Roberto Nonis, Nicola DaDalt
  • Patent number: 8736387
    Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: May 27, 2014
    Assignee: NXP B.V.
    Inventors: Kevin Mahooti, Min Ming Tarng, Jason Sharma, Hassan Sharghi, Himanshu Sharma, Amjad Nezami
  • Patent number: 8729969
    Abstract: An oscillation circuit includes a threshold voltage extraction module, a positive temperature coefficient voltage generation module, an addition module, a common-source amplifier module, a charge and discharge module, and a clock output terminal. The common-source amplifier module includes a first field effect transistor (FET) and a second FET. The addition module includes a first operational amplifier, a second operational amplifier, a third FET, a fourth FET, a fifth FET, a sixth FET, a first resistor, a second resistor, and a third resistor. The charge and discharge module includes a seventh FET, an eighth FET, a charge and discharge FET, a first switch, a second switch, a first comparator, a second comparator, a first nor gate and a second nor gate. An oscillation system is further provided. The oscillation circuit and the oscillation system of the present invention have simple structures and are easy to implement.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: May 20, 2014
    Assignee: IPGoal Microelectronics (Sichuan) Co., Ltd.
    Inventor: Junwei Huang
  • Patent number: 8723612
    Abstract: A semiconductor trimming circuit includes parallel coupled PMOS devices coupled in parallel with parallel coupled NMOS devices and an additional pair of dummy NMOS devices. The dummy NMOS devices are coupled in parallel with the NMOS devices. A trimming circuit for an internal clock source may be formed with an array of such switches for selecting one or more trimming capacitors of the trimming circuit. Such an array has a low leakage current and permits good trimming linearity.
    Type: Grant
    Filed: September 9, 2012
    Date of Patent: May 13, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Xiuqiang Xu, Jie Jin, Yizhong Zhang
  • Patent number: 8717110
    Abstract: A frequency-jittering apparatuses includes an oscillator and a frequency control circuit. The oscillator generates a signal. When the magnitude of the signal exceeds a magnitude of a reference signal, the oscillator operates substantially in a first state; and when the magnitude of the signal is lower than the magnitude of the reference signal, the oscillator operates substantially in a second state different from the first one. The frequency control circuit varies the reference signal to change the frequency of the signal output from the oscillator.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: May 6, 2014
    Assignee: Leadtrend Technology Corp.
    Inventors: Wen-Chung Yeh, Yi-Lun Shen
  • Patent number: 8692625
    Abstract: An oscillator includes a first capacitor electrically connected to a first charging switch and a first discharging switch, a second capacitor electrically connected to a second charging switch and a second discharging switch, a first chopping circuit having a first input electrically connected to the first capacitor and a second input electrically connected to a reference voltage, a second chopping circuit having a first input electrically connected to the second capacitor and a second input electrically connected to the reference voltage, a first comparator having a first input electrically connected to a first and second output of the first chopping circuit, a second comparator having a first input electrically connected to a first and second output of the second chopping circuit, and control circuitry having a first input electrically coupled to an output of the first comparator and a second input electrically connected to an output of the second comparator.
    Type: Grant
    Filed: January 13, 2012
    Date of Patent: April 8, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Dennis Sinitsky, Tao Shui