L-c Type Oscillators Patents (Class 331/167)
  • Patent number: 10931230
    Abstract: A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a pair of transistors. The pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 10826432
    Abstract: An oscillator circuit (10) for generating quadrature-related first and second oscillation signals having equal frequencies comprises a first oscillation circuit (VCO_I) configured to generate the first oscillation signal having a first controllable frequency, a second oscillation circuit (VCO_Q) configured to generate the second oscillation signal having a second controllable frequency; and a controller (100) configured to enable and disable oscillation of the first and second oscillation circuits (VCO_I, VCO_Q) and to control the first and second controllable frequencies, such that when the oscillation is enabled, the first and second controllable frequencies are controlled to be initially unequal and then to become equal.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: November 3, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Filip Oredsson, Andreas Mårtensson, Sven Mattisson
  • Patent number: 10693416
    Abstract: A system for entraining an oscillator ensemble is disclosed that includes a plurality of oscillators in an entrained phase pattern. The system includes an entrainment device operatively coupled to each non-linear oscillator of the oscillator ensemble, and the entrainment control device is configured to deliver a 2?-periodic control signal v(?) to all oscillators of the plurality of oscillators to induce the entrained phase pattern.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: June 23, 2020
    Assignee: Washington University
    Inventors: Jr-Shin Li, Anatoly Zlotnik
  • Patent number: 10659011
    Abstract: A low noise amplifier is provided. The low noise amplifier includes an input port, an output port, an inverter, a plurality of switched-capacitor units and a feedback inductor. The inverter is electrically connected between the input port and the output port. Each of the plural switched-capacitor units is electrically connected with the inverter in parallel and includes a switch and a capacitor connected in series. The feedback inductor is electrically connected with the inverter in parallel.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: May 19, 2020
    Assignee: DELTA ELECTRONICS INT'L (SINGAPORE) PTE LTD
    Inventors: Kaituo Yang, Chirn Chye Boon, Devrishi Khanna, Jack Sheng Kee
  • Patent number: 10579583
    Abstract: A random number signal generator used for performing dropout or weight initialization for a node in a neural network. The random number signal generator includes a transistor which generates a random noise signal. The transistor includes a substrate, source and drain regions formed in the substrate, a first insulating layer formed over a channel of the transistor, a first trapping layer formed over the first insulating layer, a second insulating layer formed over the first trapping layer, and a second trapping layer formed over the second insulating layer. One or more traps in the first and second trapping layers are configured to capture or release one or more carriers flowing through the channel region. The random noise signal is generated as a function of one or more carrier being captured or released by the one or more traps.
    Type: Grant
    Filed: August 9, 2016
    Date of Patent: March 3, 2020
    Assignee: International Business Machines Corporation
    Inventors: Chia-Yu Chen, Pierce I-Jen Chuang, Li-Wen Hung, Jui-Hsin Lai
  • Patent number: 10574183
    Abstract: A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alberto Valdes-Garcia, Bodhisatwa Sadhu
  • Patent number: 10559419
    Abstract: An inductor arrangement has a first inductor structure having one or more inductors at least partially on a first layer and a second inductor structure having one or more inductors at least partially on a second layer. The inductors are arranged such that currents induced by an external magnetic field are substantially cancelled in at least one of the first inductor structure and the second inductor structure. The, or each, inductor of the second inductor structure overlaps, at least partially, the, or each, inductor of the first inductor structure. An oscillator circuit having an inductor arrangement is also presented.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: February 11, 2020
    Assignee: Dialog Semiconductor B.V.
    Inventors: Thomas Dekker, Mark Oude Alink
  • Patent number: 10476484
    Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.
    Type: Grant
    Filed: January 15, 2018
    Date of Patent: November 12, 2019
    Assignee: pSemi Corporation
    Inventor: Tero Tapio Ranta
  • Patent number: 10418938
    Abstract: A voltage-controlled oscillator, including a voltage-controlled LC resonator including at least one first output node; an amplifier including at least one first dual-gate MOS transistor including first and second gates, coupling the first output node to a second node of application of a reference potential; and a regulation circuit capable of applying to the second gate of the first transistor a bias voltage variable according to the amplitude of the oscillations of a signal delivered on the first output node of the oscillator.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: September 17, 2019
    Assignee: COMMISSARIAT Á L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Baudouin Martineau, José-Luis Gonzalez Jimenez, Aurélien Larie
  • Patent number: 10374549
    Abstract: Variable frequency oscillators allowing wide tuning range and low phase noise is disclosed. In an illustrative embodiment, a first transistor has a first terminal (e.g. collector) connected to a reference voltage, and a second terminal (e.g. emitter) connected to a first terminal of a first current source and to ground. The first transistor further has a third terminal connected to a first inductor and to a first capacitor connected to the emitter of the first transistor and also to a second capacitor connected to ground. A second transistor is similarly constructed. In order to achieve a variable frequency oscillation between the emitters of the two transistors, a variable tank capacitor is connected between the inductors, forming a circuit connecting in series all passive components composing the LC tank, masking most of parasitic capacitances.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: August 6, 2019
    Assignee: SDRF EURL
    Inventors: Biagio Bisanti, Eric Duvivier, Lorenzo Carpineto, Stefano Cipriani, Francesco Coppola, Gianni Puccio, Rémi Artinian, Francois Marot, Vanessa Bedero, Lysiane Koechlin
  • Patent number: 10291179
    Abstract: An oscillator includes an oscillator circuit and a voltage circuit. The oscillator circuit includes a first transistor. The voltage circuit is configured to, in a small signal mode, provide a voltage swing at a source of the first transistor, a gate-to-source voltage of the first transistor being associated with whether the oscillator is able to generate an oscillator signal.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 14, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Chao-Chieh Li, Robert Bogdan Staszewski
  • Patent number: 10224872
    Abstract: A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alberto Valdes-Garcia, Bodhisatwa Sadhu
  • Patent number: 10008774
    Abstract: A method and apparatus for processing a terahertz frequency electromagnetic beam are disclosed. For example, the method receives the terahertz frequency electromagnetic beam via a metamaterial having a plurality of addressable magnetic elements, where a resonant frequency of each of the plurality of addressable magnetic elements is capable of being programmably changed via an adjustment, and activates selectively a subset of the plurality of addressable magnetic elements to manipulate the terahertz frequency electromagnetic beam.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: June 26, 2018
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: David Michael Britz, Robert Raymond Miller, II
  • Patent number: 9948281
    Abstract: Methods and devices providing Positive Logic biasing schemes for use in a digitally tuning capacitor in an integrated circuit device are described. The described methods can be used in integrated circuits with stringent requirements in terms of switching time, power handling, noise sensitivity and power consumption. The described devices include DC blocking capacitors arranged in series with stacked switches coupled to RF nodes. The stacked FET switches receive non-negative supply voltages through their drains and gates during the ON and OFF states to adjust the capacitance between the two nodes.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: April 17, 2018
    Assignee: Peregrine Semiconductor Corporation
    Inventor: Tero Tapio Ranta
  • Patent number: 9917548
    Abstract: A voltage controlled oscillator (VCO), a method of designing a voltage controlled oscillator, and a design structure comprising a semiconductor substrate including a voltage controlled oscillator are disclosed. In one embodiment, the VCO comprises an LC tank circuit for generating an oscillator output at an oscillator frequency, and an oscillator core including cross-coupled semiconductor devices to provide feedback to the tank circuit. The VCO further comprises a supply node, a tail node, and a noise by-pass circuit connected to the supply and tail nodes, in parallel with the tank circuit and the oscillator core. The by-pass circuit forms a low-impedance path at a frequency approximately twice the oscillator frequency to at least partially immunize the oscillator core from external noise and to reduce noise contribution from the cross-coupled semiconductor devices.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: March 13, 2018
    Assignee: International Business Machines Corporation
    Inventors: Alberto Valdes-Garcia, Bodhisatwa Sadhu
  • Patent number: 9673756
    Abstract: The invention, according to various embodiments described herein, relates to a phase-locked loop with a phase detector and a controlled oscillator. The controlled oscillator provides a varactor. The varactor is embodied using MEMS technology. According to the invention, the control bandwidth of the phase-locked loop is larger than the mechanical resonant frequency of the varactor.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: June 6, 2017
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Gerhard Kahmen
  • Patent number: 9582028
    Abstract: Circuits for distributing a global clock signal to all clock sinks on a chip for synchronous operation comprises 1) a plurality of synchronous clock areas (SCA), each SCA having a Time-Average-Frequency Direct Period Synthesis (TAF-DPS) clock source for generating a function clock, said TAF-DPS clock source has frequency synthesis and phase adjustment capabilities on its output of function clock; 2) a network for distributing a low frequency global clock signal to said plurality of synchronous clock areas, said global clock signal is used as reference for said TAF-DPS clock sources in all SCAs; 3) a plurality of clock sinks in each SCA, said clock sinks are driven by said function clock generated from said TAF-DPS clock source. Methods of distributing a low frequency global clock signal to all clock sinks in a chip for synchronous operation are also disclosed.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: February 28, 2017
    Inventor: Liming Xiu
  • Patent number: 9559702
    Abstract: A circuit comprises an oscillator including a differential tank circuit, an oscillator carrier, and an active device. A phase difference between the oscillator carrier and a device current of the active device is adjusted to reduce upconversion of flicker noise of the oscillator. The circuit includes a common-mode reactance circuit configured to provide an intentionally introduced common-mode inductance, common-mode capacitance, or both, The common-mode reactance circuit is configured to adjust at common-mode impedance of the oscillator. A method comprises adjusting a phase difference between an oscillator carrier of an oscillator and a device current of an active device of the oscillator. The adjusted phase difference is selected to reduce upconversion of flicker noise generated in the oscillator. Adjusting the phase difference includes adjusting a common-mode impedance of the oscillator.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: January 31, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventor: Konstantinos Manetakis
  • Patent number: 9543927
    Abstract: A device comprises a first capacitor block comprising a plurality of first capacitors connected in a first configuration, a second capacitor block comprising a plurality of second capacitors connected in the first configuration, a third capacitor block comprising a plurality of third capacitors connected in a second configuration, a fourth capacitor block comprising a plurality of fourth capacitors connected in the second configuration, a first switch connected between the first capacitor block and the second capacitor block, a second switch connected between the third capacitor block and the fourth capacitor block, a third switch connected between the first capacitor block and the fourth capacitor block and a fourth switch connected between the third capacitor block and the second capacitor block.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: January 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Feng Wei Kuo
  • Patent number: 9432013
    Abstract: An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 30, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Ian Juso Dedic, David Timothy Enright
  • Patent number: 9374056
    Abstract: A device or system for transmission and reception for voice or data communication applications. The device or system is capable of duplex operation and adapted to operate in an environment using a plurality of frequency bands. The present disclosure also relates to a communication means including a transmitter and receiver arrangement and to antennas.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: June 21, 2016
    Assignee: Intel Deutschland GmbH
    Inventors: Oluf Bagger, Bernd Adler, Mikael Bergholz Knudsen, Michael Wilhelm
  • Patent number: 9337806
    Abstract: An electronic device includes an inductive element, and variable capacitors. Each variable capacitor includes: first and third capacitors, both having a first terminal electrically connected to a first terminal of the inductive element; and second and fourth capacitors, both having a first terminal electrically connected to a second terminal of the inductive element. A first switch circuit electrically connects or isolates a second terminal of the first capacitor to/from a second terminal of the second capacitor. A second switch circuit electrically connects or isolates a second terminal of the third capacitor to/from a second terminal of the fourth capacitor. A third switch circuit electrically connects or isolates the second terminal of the first capacitor to/from the second terminal of the fourth capacitor. A fourth switch circuit electrically connects or isolates the second terminal of the third capacitor to/from the second terminal of the second capacitor.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Ying-Ta Lu, Hsien-Yuan Liao
  • Patent number: 9333034
    Abstract: A control system for electrosurgical apparatus in which the energy delivery profile of both RF EM radiation and microwave EM radiation delivered to a probe is set based on sampled voltage and current information of RF energy conveyed to the probe and/or sampled forward and reflected power information for the microwave energy conveyed to and from the probe. The energy delivery profile for the RF EM radiation is for tissue cutting (without requiring a sharp blade) and the energy delivery profile for the microwave EM radiation is for haemostasis or sealing or coagulation or ablation of tissue. The RF EM radiation and microwave EM radiation may be applied separately or simultaneously.
    Type: Grant
    Filed: December 7, 2011
    Date of Patent: May 10, 2016
    Assignee: CREO MEDICAL LIMITED
    Inventor: Christopher Paul Hancock
  • Patent number: 9209784
    Abstract: Switchable capacitive elements are disclosed, along with programmable capacitor arrays (PCAs). One embodiment of the switchable capacitive element includes a field effect transistor (FET) device stack, a first capacitor, and a second capacitor. The FET device stack is operable in an open state and in a closed state and has a plurality of FET devices coupled in series to form the FET device stack. The first capacitor and the second capacitor are both coupled in series with the FET device stack. However, the first capacitor is coupled to a first end of the FET device stack while the second capacitor is coupled to a second end opposite the first end of the FET device stack. In this manner, the switchable capacitive element can be operated without a negative charge pump, with decreased bias swings, and with a better power performance.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: December 8, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Christian Rye Iversen, Marcus Granger-Jones
  • Patent number: 9185820
    Abstract: Radio frequency system (250) which includes a first and second sub-assembly (100, 200), each formed of a plurality of layers of conductive material (504, 508, 516) disposed on a substrate (102) and arranged in a stack. The stacked layers form signal processing components (108, 110) and at least one peripheral wall (104, 204) surrounding a walled area (118, 218) of each substrate. The second sub-assembly is positioned on the first sub-assembly with a first walled area of a first substrate aligned with a second walled area of a second substrate.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: November 10, 2015
    Assignee: Harris Corporation
    Inventor: John E. Rogers
  • Patent number: 9041477
    Abstract: An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and an inductive unit. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The inductive unit is coupled to the first cross-coupled transistor pair at the first output nodes and coupled to the second cross-coupled transistor pair at the second output nodes. The inductive unit generates mutual magnetic coupling between one of the first output nodes and one of the second output nodes and between the other of the first output nodes and the other of the second output nodes.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: May 26, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ying-Ta Lu, Hsien-Yuan Liao, Chi-Hsien Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chewn-Pu Jou
  • Publication number: 20150137863
    Abstract: An alternation voltage- or current generator comprises a first switch driving output network whose frequency can be tuned. The tuneable network comprises a first Inductor that is coupled with a first capacitor. A second inductor and/or at least a second capacitor and/or at least a series circuit of a third inductor and a third capacitor which is coupled via at a second switch to the network. The second switch is controlled by a controlled delay (PWM) which is synchronized by a sign change of current and/or voltage in the network.
    Type: Application
    Filed: January 8, 2015
    Publication date: May 21, 2015
    Inventor: Markus Rehm
  • Patent number: 9024696
    Abstract: An injection locking oscillator (ILO) comprising a tank circuit having a digitally controlled capacitor bank, a cross-coupled differential transistor pair coupled to the tank circuit, at least one signal injection node, and at least one output node configured to provide an injection locked output signal; a digitally controlled injection-ratio circuit having an injection output coupled to the at least one signal injection node, configured to accept an input signal and to generate an adjustable injection signal applied to the at least one injection node; and, an ILO controller connected to the capacitor bank and the injection-ratio circuit configured to apply a control signal to the capacitor bank to adjust a resonant frequency of the tank circuit and to apply a control signal to the injection-ratio circuit to adjust a signal injection ratio.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: May 5, 2015
    Assignee: Innophase Inc.
    Inventors: Xi Li, Yang Xu
  • Patent number: 9019017
    Abstract: A digitally controlled oscillator has a high-order ?? modulator configured to be of at least an order higher than a first order and configured to input a digital control signal and output a pseudorandom digital output signal, a first-order ?? modulator configured to input the pseudorandom digital output signal and generate a control pulse signal including a pulse width corresponding to the pseudorandom digital output signal, a low pass filter configured to pass a low frequency component of the control pulse signal, and an oscillator configured to generate a high-frequency output signal whose frequency is controlled based on the control pulse signal outputted by the low pass filter so as to be a frequency corresponding to the digital control signal.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: April 28, 2015
    Assignees: Fujitsu Limited, Fujitsu Semiconductor Limited
    Inventors: Win Chaivipas, Masazumi Marutani, Daisuke Yamazaki
  • Patent number: 8994467
    Abstract: A digitally-controlled oscillator (DCO) includes a first capacitor array and a second capacitor array responsive to an integer part and a fractional part of a digital control word, respectively. The mismatch measurement of the DCO includes a first settling phase and a second settling phase. In the first settling phase, the first capacitor array is fixed to have one capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to a target value. In the second settling phase, the first capacitor array is fixed to have another capacitive value, and the second capacitor array is adjusted for making the DCO frequency locked to the same target value. The capacitor mismatches are estimated according to characteristic values derived from the digital control word adaptively adjusted in the first setting phase and the second setting phase.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: March 31, 2015
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Wen-Chang Lee, Shih-Chi Shen, Chii-Horng Chen, Xiaochuan Guo
  • Patent number: 8994463
    Abstract: A push-push oscillator circuit with a first oscillation branch with a first active device and a first tank adapted to provide a signal having a fundamental frequency f0, a second oscillation branch with a second active device and a second tank symmetrical to the first oscillation branch and adapted to provide a signal having the fundamental frequency f0. Output branches are coupled to the first oscillation branch and the second oscillation branch to provide signals having the second harmonic frequency 2f0 of the fundamental signal based on the signals having the fundamental frequency f0 and/or to provide signals having the fundamental frequency f0; The push-push oscillator circuit further comprises at least one terminal branch with a terminal adapted to provide a component of a differential signal having the second harmonic frequency 2f0 or the fundamental frequency f0. The at least one terminal branch comprises a RF stub.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: March 31, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Yin Yi, Hao Li, Saverio Trotta
  • Patent number: 8975977
    Abstract: LC tank and ring-based VCOs are disclosed that each include a differential pair of transistors for steering a tail current generated by a current source responsive to a bias voltage. A biasing circuit generates the bias voltage such that a transconductance for the transistors in the differential pairs is inversely proportional to a resistance.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: March 10, 2015
    Inventor: Mohammad Ardehali
  • Patent number: 8975936
    Abstract: An integrated circuit includes a plurality of resonant clock domains of a resonant clock network. Each resonant clock domain has at least one clock driver that supplies a portion of clock signal to an associated resonant clock domain. The resonant clock network operates in a resonant mode with inductors connected to pairs of resonant clock domains at boundaries between the resonant clock domains. Each inductor forms an LC circuit with clock load capacitance in the pair of resonant clock domains to which the inductor is connected.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: March 10, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Visvesh S. Sathe, Samuel D. Naffziger
  • Patent number: 8970314
    Abstract: With some embodiments, a VCO (voltage controlled oscillator) operates at an integer multiple (N) above a desired transmission frequency. In accordance with one embodiment, a chip is provided with a VCO to generate a signal and a frequency dividing circuit to provide a reduced frequency version of the signal to a transmit mixer. The transmit mixer is followed by a power amplifier that is on the same die as the VCO. The power amplifier is to generate an OFDM output transmission.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Pankaj Goyal, Christopher Hull
  • Patent number: 8957738
    Abstract: A voltage controlled oscillator including an RF output terminal and a DC control terminal, an active circuit, and a resonant circuit interconnected with the active circuit and including a plurality of series resonators each having an electrically variable capacitance and fixed inductor; the active circuit includes at least one transistor having an operating current density which is approximately 35% or less of the peak fT operating current density and/or the active circuit includes a multi-transistor bank disposed in at least two separate sections, each pair of sections spaced apart to provide improved thermal uniformity among the transistors without substantially increasing parasitic impedance among them for providing an improved lower phase noise output at said RF output terminal.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: February 17, 2015
    Assignee: Hittite Microwave Corporation
    Inventors: Michael Koechlin, John Chiesa, Christopher O'Neill, Ekrem Oran, John Poelker, Cemin Zhang
  • Publication number: 20150022190
    Abstract: Circuits for inductive position sensor are described.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Inventors: Gordon Brandt Taylor, Steven E. Beard
  • Patent number: 8928418
    Abstract: Systems and methods for reducing process sensitivity in integrated circuit (“IC”) fabrication. An integrated circuit structure is provided that includes a first integrated circuit device having at least one parameter influenced by process variation in a first manner. The integrated circuit structure further includes a second integrated device having the least one parameter influenced by the process variation in a second manner. The first manner is opposite of the second manner. The second integrated device is configured to offset or reduce the influence of the process variation on the at least one parameter in the first integrated circuit device.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Herschel A. Ainspan, Anthony R. Bonaccio, Ramana M. Malladi
  • Patent number: 8928423
    Abstract: A narrow band receiver or transceiver for processing electrical signals. The narrow band receiver or transceiver includes an amplifier, a voltage controlled oscillator and a tuning assembly comprising at least one control loop for tuning of the voltage controlled oscillator. At least a gain control of the amplifier is coupled to the control loop for simultaneously tuning the output amplitude of the voltage controlled oscillator and the gain of the amplifier. A compensation of the effect of variation on the gain of the amplifier, which includes an LC tank circuit, is performed by using an information in another LC tank circuit of the voltage controlled oscillator in the control loop.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: January 6, 2015
    Assignee: EM Microelectronic-Marin S.A.
    Inventors: Armin Tajalli, Marc Morin
  • Patent number: 8922288
    Abstract: An oscillator circuit comprising first and second resonator terminals for connecting to respective terminals of a resonator. The oscillator circuit also comprises a first inverting amplifier connected between the first and second resonator terminals in a first mode of operation; and a back to back pair of second inverting amplifiers connected between the first and second resonator terminals in a second mode of operation. There is also provided a controller configured to compare an operational parameter of the oscillator circuit to a switchover threshold, and switch the oscillator circuit from the first mode of operation to the second mode of operation when the operational parameter exceeds the switchover threshold.
    Type: Grant
    Filed: February 22, 2013
    Date of Patent: December 30, 2014
    Assignee: NXP, B.V.
    Inventors: Johannes Hubertus Antonius Brekelmans, Reinier Hoogendoorn, Nenad Pavlovic
  • Patent number: 8912857
    Abstract: A phase locked loop system, comprises: a voltage controlled oscillator circuit, comprising a first plurality of switchable varactors for selecting a frequency band of the VCO, that has a gain that changes with frequency band, and a second plurality of switchable varactors for varying the gain in the selected band. The PLL system has a PLL feedback circuit comprising a switching device for switching the feedback circuit to an open loop state wherein a plurality of predefined tuning voltages can be applied to the VCO; a frequency measurement device for measuring the synthesized VCO frequency; and a control unit operable to determine the gain with respect to the synthesized frequency and the tuning voltages.
    Type: Grant
    Filed: April 18, 2008
    Date of Patent: December 16, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hugues Beaulaton, Thierry Cassagnes, Stéphane Colomines, Didier Salle
  • Patent number: 8896390
    Abstract: A circuit of inductance/capacitance (LC) voltage control oscillator (VCO) includes an LC VCO unit, a peak detector and a processing unit. The LC VCO unit receives a current control signal and outputs an oscillating voltage signal. The peak detector receives the oscillating voltage signal to obtain an averaged voltage value. The processing unit receives the averaged voltage value to accordingly output the current control signal and feedback to the LC VCO unit. The processing unit also detects whether or not the averaged voltage value has reached to a saturation state and a corresponding critical current. After the current control signal reaches to the critical current, the current control signal is set within a variance range near the critical current.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventor: Chih-Hung Chen
  • Patent number: 8896389
    Abstract: The present disclosure relates to an oscillation circuit including a differential negative resistance element, a resonance circuit connected to the differential negative resistance element, and a stabilization circuit connected in parallel with the negative resistance element to suppress parasitic oscillation. The stabilization circuit includes a variable shunt resistor and an adjusting device for adjusting the shunt resistor.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: November 25, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yasushi Koyama, Ryota Sekiguchi
  • Patent number: 8890633
    Abstract: According to an example embodiment, a device includes a resonant circuit configured and arranged to provide a peak current flow at a resonance frequency. A trimming circuit provides variable impedances to the resonant circuit and thereby changes the resonance frequency for the resonant circuit. A driver circuit is configured to generate a trimming signal that oscillates at a desired frequency. A switch circuit couples and decouples the driver circuit to the resonant circuit for driving the resonant circuit with the trimming signal. An amplitude detection circuit detects amplitudes for signals generated in response to the trimming signal being connected to the resonant circuit. A processing circuit correlates detected amplitudes from the amplitude detection circuit with different impedance values of the variable trimming circuit.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: November 18, 2014
    Assignee: NXP B.V.
    Inventor: Sven Simons
  • Patent number: 8884708
    Abstract: The present invention provides a digitally controlled oscillator device capable of realizing a reduction in DNL. The digitally controlled oscillator device includes, for example, an amplifier circuit block, coil elements and a plurality of unitary capacitor units coupled in parallel between oscillation output nodes. Each of the unitary capacitor units is provided with capacitive elements, and a switch which selects whether the capacitive elements should be allowed to contribute as set parameters for an oscillation frequency. The switch is driven by an on/off control line extending from a decoder circuit. The on/off control line is shielded between the oscillation output nodes by a shield section.
    Type: Grant
    Filed: October 13, 2012
    Date of Patent: November 11, 2014
    Assignee: Renesas Mobile Corporation
    Inventor: Takahiro Nakamura
  • Patent number: 8884713
    Abstract: This invention compensates for the unintentional magnetic coupling between a first and second inductor of two different closely spaced inductors separated by a conversion circuit. A cancellation circuit formed from transistors senses the magnetic coupling in the first inductor and feeds a current opposite to the induced magnetic coupling captured by the second inductor such that the coupled magnetic coupling can be compensated and allows the first and second inductors to behave independently with regards to the coupled magnetic coupling between the first and second inductors. This allows the distance between the first and second inductors to be minimized which saves silicon area. In addition, the performance is improved since the overall capacitance in both circuits can be decreased. This cancellation technique to reduce the magnetic coupling between two closed placed inductively loaded circuits allows the design of a more compact and faster performing circuit.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: November 11, 2014
    Assignee: Tensorcom, Inc.
    Inventor: KhongMeng Tham
  • Patent number: 8884718
    Abstract: A substantially temperature-independent LC-based oscillator uses bias control techniques. Temperature independence may be achieved by controlling the harmonic frequency content of the output of the oscillator by controlling the amplitude. Amplitude control may be achieved by inserting a control mechanism in the feedback loop of the oscillator.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: November 11, 2014
    Assignee: Si-Ware Systems
    Inventors: Nabil M. Sinoussi, Mohamed M. Weheiba, Ahmed A. Helmy, Ahmed H. A. Razek, Ayman Ahmed
  • Patent number: 8878614
    Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 4, 2014
    Assignee: MegaChips Corporation
    Inventors: Wenjing Yin, Anand Gopalan
  • Patent number: 8874631
    Abstract: A random number generation apparatus includes: a random noise generation element comprising a source region and a drain region, a tunnel insulation film, a gate electrode, and a charge trap portion provided between the tunnel insulation film and the gate electrode and being capable of trapping charges, random noise being generated in a drain current flowing between the source region and the drain region on the basis of charges trapped in the charge trap portion; a random number conversion circuit for converting random noise generated from the random noise generation element to a random number; a first test circuit for performing a random number test to test quality of the random number output from the random number conversion circuit; and an initialization circuit for pulling out charges in the charge trap portion of the random noise generation element to the semiconductor substrate through the tunnel insulation film and thereby initializing the charge trap portion.
    Type: Grant
    Filed: July 17, 2009
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mari Matsumoto, Tetsufumi Tanamoto, Shinichi Yasuda
  • Patent number: 8866558
    Abstract: A standing wave oscillator includes a cross-coupled differential transistor pair having a pair of input terminals and a pair of output terminals; and a resonant circuit coupled to the input terminals of the cross-coupled differential transistor pair. The resonant circuit includes: a capacitance between the input terminals of the cross-coupled differential transistor pair; and a differential dual-mode coplanar waveguide (CPW) having opposite differential ends thereof connected to respective input terminals of the cross-coupled differential transistor pair. CPW ground lines of the differential dual-mode coplanar waveguide each have a first end thereof connected to the first supply voltage and have a second end thereof floating or unterminated.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: October 21, 2014
    Assignee: Her Majesty the Queen in Right of Canada, as Represented by the Minister of Industry, Through the Communications Research Centre Canada
    Inventors: Ming Li, Khelifa Hettak, Rony E. Amaya, Adrian Momciu, Luc A. Desormeaux, Valek Szwarc
  • Patent number: 8860516
    Abstract: A piezoelectric oscillator includes: a piezoelectric resonator element having a piezoelectric substrate and an excitation electrode formed on a surface of the piezoelectric substrate; a semiconductor circuit element provided with an oscillation circuit for oscillating the piezoelectric resonator element and having a first insulating film formed on a principal surface; a package for airtightly housing the semiconductor circuit element and the piezoelectric resonator element; and a protruding section having at least of a thin film circuit component formed on the first insulating film and connected to the oscillation circuit; and a second insulating film formed on the first insulating film and covering the thin film circuit component. In the oscillator, the piezoelectric resonator element is fixed to an upper surface of the protruding section.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: October 14, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Shinji Nishio