With Synchronizing, Triggering Or Pulsing Circuits Patents (Class 331/172)
  • Patent number: 9716468
    Abstract: Circuitry capable of performing fractional clock multiplication by using an injection-locked oscillator is described. Some embodiments described herein perform fractional clock multiplication by periodically changing the injection location, from a set of injection locations, where the injection signal is injected and/or by periodically changing a phase, from a set of phases, of the injection signal that is injected into the ILO.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: July 25, 2017
    Assignee: RAMBUS INC.
    Inventors: Masum Hossain, Farshid Aryanfar, Mohammad Hekmat, Reza Navid
  • Patent number: 9691316
    Abstract: Provided is a display device including a timing controller configured to output a clock synchronizing signal for a clock data recovery operation, and a plurality of source driving chips configured to perform the clock data recovery operation in response to the clock synchronizing signal, wherein each of the source driving chips includes a filter unit configured to determine whether the first and second detection signals are activated or deactivated in response to a voltage level of the clock synchronizing signal and to output an operation signal according to a comparative result of the first and second detection signals, and an internal clock generator configured to perform the clock data recovery operation in response to the activation state of the operation signal.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: June 27, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Kihyun Pyun, Tongill Kwak
  • Patent number: 9083424
    Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: July 14, 2015
    Assignee: University of Washington Through its Center for Commercilization
    Inventors: Brian Patrick Otis, Jagdish Narayan Pandey
  • Patent number: 9013240
    Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: April 21, 2015
    Assignee: Beken Corporation
    Inventors: Jiazhou Liu, Dawei Guo
  • Patent number: 8981854
    Abstract: A clock distributor includes a first oscillator and a second oscillator, to each of which a signal controlling an oscillation frequency is input and to one of which a clock is input; a wiring portion that connects the first oscillator and the second oscillator; a first conversion element that converts an output from the first oscillator into electric current, and outputs a result to a first connection portion connecting to the wiring portion; a second conversion element that converts voltage of the first connection portion into electric current, and outputs a result to the first oscillator; a third conversion element that converts an output from the second oscillator into electric current, and outputs a result to a second connection portion connecting to the wiring portion; and a fourth conversion element that converts voltage of the second connection portion into electric current, and outputs a result to the second oscillator.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: March 17, 2015
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8975973
    Abstract: A voltage controlled oscillation circuit oscillates at an oscillation frequency corresponding to a control voltage. Injection locked oscillation circuits oscillate at an oscillation frequency corresponding to an output signal from the voltage controlled oscillation circuit. A mixer circuit performs a frequency conversion based on output signals from the injection locked oscillation circuits. A synchronization determiner determines the synchronous status between the injection locked oscillation circuits in accordance with an output signal from the mixer circuit. The injection locked oscillation circuits synchronize with each other at a frequency that is an integral multiple of the oscillation frequency of the voltage controlled oscillation circuit.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: March 10, 2015
    Assignee: Panasonic Corporation
    Inventor: Junji Sato
  • Patent number: 8902007
    Abstract: A clock distributor includes unit circuit parts each including an oscillator, a first element configured to convert output voltage of the oscillator into a current, a second element having a voltage current conversion characteristic of an opposite phase to that of the first element, the second element being feedback connected to the first element and the oscillator, a third element configured to convert output voltage of the oscillator into a current, a fourth element having a voltage current conversion characteristic of an opposite phase to that of the third element, the fourth element being feedback connected to the third element and the oscillator; a wiring part to connect a connection part of the first and second elements of a unit circuit part to a connection part of the third and fourth elements of another unit circuit part; and a synchronization circuit connected to the oscillator of a unit circuit part.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: December 2, 2014
    Assignee: Fujitsu Limited
    Inventors: Yasumoto Tomita, Hirotaka Tamura
  • Patent number: 8878620
    Abstract: An improved arbitrary waveform generator has a waveform memory for storing digitized waveforms, a waveform playout for playing out desired ones of the digitized waveforms as analog waveforms and a sequencer for controlling the waveform playout, the sequencer providing indications of the desired waveform for playout and a desired starting sample position for the desired waveform. The sequencer includes a tracking mechanism for the desired waveform so that the desired waveform is phase coherent when playout is interrupted and restarted later according to programming of the sequencer.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: November 4, 2014
    Assignee: Tektronix, Inc.
    Inventor: Timothy E. Sauerwein
  • Patent number: 8860513
    Abstract: An apparatus comprises a ring oscillator comprising a plurality of delay cells connected in cascade, a main injection apparatus comprising a plurality of main buffers, wherein the main buffers receive a reference clock from their inputs and the outputs of the main buffers are coupled to respective inputs of the delay cells and a replica injection apparatus comprising a plurality of replica buffers, wherein the replica buffers receive the reference clock from their inputs and the replica buffers are configured such that the replica buffers are tri-stated and each output is connected to ground when the ring oscillator operates in an injection-locked mode and each output is connected to ground through a capacitor when the ring oscillator operates in a calibration mode.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 14, 2014
    Assignee: Futurewei Technologies, Inc.
    Inventor: Euhan Chong
  • Patent number: 8826061
    Abstract: A method of implementing a system time in an electronic device using a timer is disclosed. The method comprises storing a first count reset value in the electronic device; increasing a count value; comparing the first count reset value with the count value at a first particular time; resetting the count value when the count value is the same as the first count reset value at the first particular time; and generating an interrupt request signal when the count value is reset.
    Type: Grant
    Filed: September 9, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Lae Park
  • Patent number: 8729974
    Abstract: A crystal oscillator circuit is configured to output an oscillation signal. A bias circuit responds to control signal to generate a bias current for application to the crystal oscillator circuit. A current generator generates a sense current from the control signal. The sense current is compared to a reference current by a comparator circuit. The comparator circuit generates a ready signal in response to the comparison. The ready signal is indicative of whether the oscillation signal output from the crystal oscillator circuit is ready for use by other circuitry. The reference current may be generated by a circuit which replicates the bias circuit.
    Type: Grant
    Filed: May 4, 2012
    Date of Patent: May 20, 2014
    Assignee: STMicroelectronics S.r.l.
    Inventors: Giulio Zoppi, Raffaele Iardino
  • Patent number: 8689035
    Abstract: An interface board includes a synchronizer that synchronizes a first time that is a time of the interface board to a base time based on a master synchronization signal that is supplied by an external master time source and that defines the base time. The interface board also includes a comparator that compares a phase of a first synchronization signal that synchronizes to the first time with a phase of a shared synchronization signal sent by an interface controller that controls the interface board, and a notifier that notifies another interface board of a comparison result of the comparator.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: April 1, 2014
    Assignee: Fujitsu Limited
    Inventors: Naoya Matsusue, Kanta Yamamoto
  • Patent number: 8674776
    Abstract: An oscillator circuit includes a resonator (SAW resonator), an amplifier circuit, and a switching element (NMOS switch). The amplifier circuit has a feedback path from one end to the other end of the resonator, a first inductance element (elongated coil) provided in the feedback path, and a variable capacitance element (variable capacitance diode) provided in the feedback path in series with the first inductance element. The switching element is provided in parallel to a circuit part including the first inductance element and the variable capacitance element.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: March 18, 2014
    Assignee: Seiko Epson Corporation
    Inventor: Masataka Nomura
  • Patent number: 8624684
    Abstract: A power-oscillator-starting circuit for an electronic high frequency induction-heater driver. The induction-heater driver, upon receipt of a turn-on signal, generates a high frequency alternating current, wherein the alternating current through an induction-heater coil is magnetically coupled to an appropriate loss component for a variable-spray fuel-injection system. The induction-heater driver uses a power oscillator that is started and restarted as is appropriate based on a threshold current limit referenced to the supply voltage of the induction-heater driver.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: January 7, 2014
    Assignee: Continental Automotive Systems, Inc
    Inventor: Perry Czimmek
  • Patent number: 8570109
    Abstract: A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: October 29, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Taek-Sang Song, Dae-Han Kwon, Dae-Kun Yoon
  • Patent number: 8570108
    Abstract: An injection-locked oscillator circuit includes a master oscillator, a slave oscillator, and an injection lock control circuit. The slave oscillator is decoupled from the master oscillator (for example, due to an unlock condition). When the slave is free running, its oscillating frequency is adjusted (for example, as a function of a supply voltage). After an amount of time, the slave is to be relocked to the master (for example, due the unlock condition no longer being present). The slave oscillating frequency is made to be slightly lower than the master oscillating frequency. The slave is then only recoupled to the master upon detection of an opposite-phase condition between the master oscillator output signal and the slave oscillator output signal. By only recoupling the slave to the master during opposite-phase conditions, frequency overshoots in the slave oscillating frequency are avoided that may otherwise occur were the recoupling done during in-phase conditions.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: October 29, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Ashwin Ragunathan, Marzio Pedrali-Noy, Sameer Wadhwa
  • Patent number: 8542069
    Abstract: A method for trimming a cycle time of an adjustable oscillator to match a Controller Area Network-bus (CAN-bus) operating with a predetermined bit time includes determining a measured number of cycles of an adjustable oscillator between a first signal and a second signal within a CAN frame transmitted on a CAN-bus; determining an information about a present cycle time of the adjustable oscillator using the measured number of cycles and a nominal number of cycles per bit time; and trimming a cycle time of an adjustable oscillator to match the CAN-bus operating with a predetermined bit time based on the determined information.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: September 24, 2013
    Assignee: Infineon Technologies AG
    Inventors: Ursula Kelling, Arndt Voigtlaender
  • Patent number: 8456246
    Abstract: A quadrature VCO includes a first oscillator unit and a second oscillator unit. Each of the first and second oscillator unit is composed of a DC bias source, a complementary cross-coupled pair, an LC resonator unit, a frequency-doubling sub-harmonic coupler unit, and a ground terminal. When the LC resonator units of the first and second oscillator units are operated, four signals of different phases can be outputted via the output terminals. In this way, the output phase difference of the two oscillator units can keep 180 degrees and allow the two oscillator units to mutually inject signals to generate quadrature output signals.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: June 4, 2013
    Assignee: National Chung Cheng University
    Inventors: Shuenn-Yuh Lee, Liang-Hung Wang, Yu-Heng Lin
  • Patent number: 8446224
    Abstract: A circuit interconnection structure for synchronizing a network of oscillators placed on a semiconductor substrate. One such structure comprises a first synchronizing circuit electrically coupled to a second synchronizing circuit through tunable delay circuits. Also disclosed are methods to tune oscillators placed in different regions of a circuit having multiple clock domains by estimating the relative slack of a first group of signals within the circuit with regard to the period of a first clock domain, and estimating the relative slack of the second group of signals within the circuit with regard to the period of second clock domain, wherein the estimating is performed at process and operational corners that cover the variability of the circuit at different speed conditions, then calculating tuning values for the oscillator delays for each region such that the oscillator delay slack matches the worst relative slack of the signals of the same region.
    Type: Grant
    Filed: July 12, 2011
    Date of Patent: May 21, 2013
    Assignee: eSilicon Corporation
    Inventors: Jordi Cortadella, Luciano Lavagno, Emre Tuncer
  • Patent number: 8427242
    Abstract: A method for generating an UWB pulses based on LC oscillator topology. Fast turn on of the oscillator is achieved by creating large asymmetry in a normally symmetrical topology which is used in a typical differential type oscillator. One method for achieving large asymmetry is activating one branch of a differential pair of branches for a short duration before activating both branches in a normal operation. The bandwidth of the pulse is controlled by modifying the duration of the oscillator activation. Fast turn on and turn off is essential for high bandwidth generation. The method is adaptable for generating binary phase shift keying (BPSK) modulation. Selecting the activated branch of a fully symmetrical topology controls the output phase and creates two possibilities which differ exactly by 180 degrees. In a preferred embodiment, all the pulse generator components are on-clip leading to a low cost solution. The circuit can generate high power pulses directly on a load.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: April 23, 2013
    Assignee: Zebra Enterprises Solutions Corp.
    Inventors: Dani Raphaeli, Guy Shasha
  • Patent number: 8368480
    Abstract: Phase locked loop circuits are provided, in which a phase locked loop module includes a voltage controlled oscillator to generate an oscillation signal with an output frequency according to a control voltage, and a gain calibration module triggers the phase locked loop module to induce a frequency variation characterized by a delta function in the output frequency and calculates a gain of the voltage controlled oscillator according to a phase error caused by the frequency variation in the output frequency.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: February 5, 2013
    Assignee: Mediatek Inc.
    Inventor: Ping-Ying Wang
  • Patent number: 8319567
    Abstract: An oscillator synchronization system employs two oscillators, each of which includes an integrator which provides a ramping signal at its output, a comparator which receives the ramping signal and a reference signal at respective inputs and toggles an output when the ramping voltage crosses the reference signal, and a one-shot circuit that generates the integrator's reset signal when triggered. The system is preferably arranged such that the oscillators can be operated independently, in which case each oscillator's one-shot is triggered by its own comparator output, or synchronously, in which case each oscillator's one-shot is triggered by the other oscillator's comparator output—with the ramp signal of each oscillator operating to reset the integrator of the other oscillator. The oscillators are typically out-of-phase when synchronized, with the phase difference varying with the magnitude of the reference signals applied to the comparators.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: November 27, 2012
    Assignee: Analog Devices, Inc.
    Inventor: Jonathan Mark Audy
  • Patent number: 8250399
    Abstract: Aspects of the disclosure provide a network device. The network device includes a first port coupled to a first device to communicate with the first device, and a clock wander compensation module. The first port recovers a first clock based on first signals received from the first device. The clock wander compensation module includes a global counter configured to count system clock cycles based on a system clock of the network device, and a first port counter configured to count first clock cycles based on the recovered first clock. Further, the first port transmits a first pause frame to the first device based on the global counter and the first port counter.
    Type: Grant
    Filed: January 7, 2010
    Date of Patent: August 21, 2012
    Assignees: Marvell International Ltd., Marvell Israel (M.I.S.L.) Ltd.
    Inventors: Tal Mizrahi, Carmi Arad, Martin White, Tsahi Daniel
  • Patent number: 8232844
    Abstract: Disclosed herein is a synchronous oscillator including at least one injection circuit having an injection signal input terminal, an internal clock signal input terminal, and a clock output terminal, and at least one delay circuit cascaded to the injection circuit.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: July 31, 2012
    Assignee: Sony Corporation
    Inventor: Kenichi Maruko
  • Patent number: 8228126
    Abstract: A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.
    Type: Grant
    Filed: April 17, 2008
    Date of Patent: July 24, 2012
    Assignees: Mediatek Inc., National Taiwan University
    Inventors: Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu
  • Patent number: 8193870
    Abstract: The present invention is a method and system for compensation of frequency pulling in an all digital phase lock loop. The all digital phase lock loop can utilize a multi-phase oscillator including latches with substantially all of the latches paired with a corresponding dummy cell. The dummy cells can have impedance characteristics, such as variable capacitance values which correspond to the variable capacitance value of the latches such that the sum of the two variable capacitance values remains substantially constant, even when the polarity of the reference clock signal changes. The dummy cells can be, for example, variable capacitors or dummy latches. The phase lock loop can also include a multiplying unit. The multiplying unit can receive a reference clock signal and generate a frequency multiplied reference clock signal.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: June 5, 2012
    Assignee: Panasonic Corporation
    Inventors: Koji Takinami, Richard Strandberg, Paul Cheng-Po Liang
  • Patent number: 8102217
    Abstract: An oscillator creates a reference voltage based on a pulse signal corresponding to an oscillation output of a crystal oscillation circuit and controls a supply voltage to the crystal oscillation circuit according to the reference voltage. A control signal creating circuit creates a control signal based on the pulse signal and reference voltage generating circuits that control the reference voltage based on the control signal. The control signal creating circuit creates a low-level control signal when the pulse signal is in a low level, creates a high-level control signal when the pulse signal is in a high level, and prevents transition of the control signal from the high level to the low level.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: January 24, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroyuki Aoki
  • Patent number: 8089321
    Abstract: Four stochastic resonators 20-1 to 20-4 outputting a pulse signal in accordance with a stochastic resonance phenomenon are unidirectionally coupled in a ring-like form to constitute a fluctuation oscillator 10. When a signal output from each of the stochastic resonators 20-1 to 20-4 is successively transmitted in the stochastic resonators 20-1 to 20-4 coupled in a ring-like form, the output timings at each stochastic resonator 20 are synchronized with each other due to a cooperation phenomenon between the stochastic resonators 20-1 to 20-4, so that each stochastic resonator 20 is self-excited to oscillate at a constant period of time.
    Type: Grant
    Filed: August 21, 2008
    Date of Patent: January 3, 2012
    Assignee: Osaka University
    Inventors: Yasushi Hotta, Teruo Kanki, Naoki Asakawa, Toshio Kawahara, Tomoji Kawai, Hitoshi Tabata
  • Patent number: 8085103
    Abstract: Some embodiments of the present invention provide a system that implements a resonant oscillator circuit. This resonant oscillator circuit includes: a first inductor, a second inductor, a first capacitance, and a second capacitance, wherein the first and second inductors are configured to operate with the first and second capacitances to produce resonant oscillations which appear at a first phase output and a second phase output. The system also includes a startup circuit which is configured to start the resonant oscillator circuit in a state where: the first phase output is at a peak voltage; the second phase output is at a base voltage; and currents through the first and second inductors are substantially zero. By starting the resonant oscillator circuit in this state, the oscillations commence without a significant startup transient.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: December 27, 2011
    Assignee: Apple Inc.
    Inventor: William C. Athas
  • Patent number: 8085104
    Abstract: An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a number of waves of the output signal within a predetermined period is smaller than a predetermined value, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate.
    Type: Grant
    Filed: July 10, 2009
    Date of Patent: December 27, 2011
    Assignee: Phison Electronics Corp.
    Inventors: Yu-Tong Lin, Yun-Chieh Chen
  • Patent number: 8072273
    Abstract: A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in integrated form, or in any combination, and includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer.
    Type: Grant
    Filed: October 8, 2010
    Date of Patent: December 6, 2011
    Assignee: NEL Frequency Controls, Inc.
    Inventors: Roman Boroditsky, Jorge Gomez
  • Patent number: 8058935
    Abstract: An apparatus comprises a structure, an array of oscillator units, a plurality of waveguides in the structure, and a synchronizing cavity located within the structure. The array of oscillator units has a plurality of rows and a plurality of columns associated with the structure. Oscillator units in a row within the array of oscillator units are directly coupled to each other. The plurality of waveguides is configured to couple the array of oscillator units to the synchronizing cavity. The synchronizing cavity is configured to cause the array of oscillator units to operate at substantially a common frequency.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: November 15, 2011
    Assignee: The Boeing Company
    Inventors: Jonathan James Lynch, Perry A. Macdonald
  • Patent number: 8055931
    Abstract: A method is provided for switching between two oscillator signals within an alignment element. In accordance with the method, one of the two oscillator signals one is selected as a first master signal in order to provide an output stepping signal at an output of the alignment element. The method comprises introducing a virtual stepping signal when a switch between the two oscillator signals occurs or when a failure in the first master signal is detected. The method further comprises sending the virtual stepping signal to the output of the alignment element in the event of a switch until an alignment with a new master signal is completed.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Ralf Ludewig, Thuyen Le, Tilman Gloekler, Willm Hinrichs
  • Patent number: 8049570
    Abstract: An electrical/magnetic current sensing system includes a first collection mechanism configured to convert an electric field into surface charge, a second collection mechanism comprising a magnetic reactive material, and a sensor coupled to the first and second collection mechanisms. The sensor comprises an odd number, greater than or equal to three, of unidirectionally-coupled non-linear over-damped bi-stable elements. Each element comprises a resistive load, an operational transconductance amplifier (OTA) with a bipolar junction transistor differential pair, a cross-coupled OTA, and a non-linear OTA. Each element may comprise fully differential inputs and outputs. The sensor may be contained in a microchip or on a printed circuit board. A resident time difference readout device may be connected to the sensor, and may be configured to perform a power spectral density calculation. The sensor may include a resistance to voltage circuit connected between the second collection mechanism and the elements.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: November 1, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Visarath In, Patrick Longhini, Yong (Andy) An Kho, Joseph D. Neff, Antonio Palacios, Norman Liu
  • Patent number: 8026771
    Abstract: A driver device that forms an oscillation loop with a vibrator and causes the vibrator to produce driving vibrations includes a current-voltage converter that converts a current that flows through the vibrator into a voltage, an output circuit that causes the vibrator to produce the driving vibrations based on a signal that is converted into a voltage with respect to a given voltage, and a high-pass filter that is provided in the oscillation loop between the current-voltage converter and the output circuit. The driver device causes the vibrator to produce the driving vibrations while changing a reference potential of the high-pass filter, and then causes the vibrator to produce the driving vibrations while fixing the reference potential.
    Type: Grant
    Filed: November 26, 2007
    Date of Patent: September 27, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Masahiro Kanai, Naoki Yoshida, Eitaro Otsuka
  • Patent number: 8001410
    Abstract: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.
    Type: Grant
    Filed: November 4, 2008
    Date of Patent: August 16, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Feng Lin
  • Patent number: 7994870
    Abstract: An apparatus includes a filter and a gain control circuit. The filter receives and filters an input signal and provides an output signal in a first mode and operates as part of an oscillator in a second mode. The gain control circuit varies the amplitude of an oscillator signal from the oscillator in the second mode, e.g., by adjusting at least one variable gain element within the oscillator to obtain a target amplitude and/or non rail-to-rail signal swing for the oscillator signal. The apparatus may further include a bandwidth control circuit to adjust the bandwidth of the filter in the second mode. The bandwidth control circuit receives the oscillator signal, determines a target oscillation frequency corresponding to a selected bandwidth for the filter, and adjusts at least one circuit element within the filter to obtain the target oscillation frequency.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: August 9, 2011
    Assignee: QUALCOMM, Incorporated
    Inventors: Cheng-Han Wang, Tzu-wang Pan
  • Patent number: 7949126
    Abstract: A bipolar pulse forming transmission line module and system for linear induction accelerators having first, second, third, and fourth planar conductors which form a sequentially arranged interleaved stack having opposing first and second ends, with dielectric layers between the conductors. The first and second planar conductors are connected to each other at the first end, and the first and fourth planar conductors are connected to each other at the second end via a shorting plate. The third planar conductor is electrically connectable to a high voltage source, and an internal switch functions to short at the first end a high voltage from the third planar conductor to the fourth planar conductor to produce a bipolar pulse at the acceleration axis with a zero net time integral. Improved access to the switch is enabled by an aperture through the shorting plate and the proximity of the aperture to the switch.
    Type: Grant
    Filed: June 17, 2008
    Date of Patent: May 24, 2011
    Assignee: Lawrence Livermore National Security, LLC
    Inventor: Mark A. Rhodes
  • Patent number: 7929919
    Abstract: A system is provided, the system includes a phase-locked loop (PLL) that multiplies a reference clock input to generate a communication link clock signal. The system also includes a transmitter/receiver (TX/RX) module coupled to the PLL, the TX/RX module is configured to transmit and receive data based on the communication link clock signal. The system also includes a divider coupled to the PLL, the divider receives the communication link clock signal and outputs a PLL-adjusted reference clock that approximates the reference clock input. The PLL-adjusted reference clock is used to generate at least one other communication link clock signal.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: April 19, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Justin Coppin
  • Patent number: 7902926
    Abstract: An embodiment of a communication system is provided, in which a high frequency oscillator generates a first high frequency signal upon receipt of no disable signal. The first high frequency signal is commonly shared by at least two modules. Each module coupled to the high frequency oscillator operates in either busy or idle mode, wherein the module operates at the first high frequency signal when in busy mode, and asserts a request signal when in idle mode. A disablement unit, coupled to the first and second modules, asserts the disable signal to the high frequency oscillator when all of the request signals are asserted, thereby forcing the high frequency oscillator to cease the generation of the first high frequency signal.
    Type: Grant
    Filed: April 20, 2009
    Date of Patent: March 8, 2011
    Assignee: Mediatek Inc.
    Inventors: Ti-Wen Yuan, Chung-Shine Huang
  • Patent number: 7881894
    Abstract: One delay circuit is inserted in open loop inside a clock recovery circuit for improving the accuracy of clock recovery. One oscillator signal ?(0) to ?(2i?1) is provided with a basic Step of Time. A rational number of Step of Time corresponding to a bit-duration is measured inside a received flow of bits. The oscillator signal ?(0) to j(2i?1) is transformed into a clock signal CK having active edges of said clock signal in phase with at least one oscillator signal ?(0) to ?(2i?1), two consecutive active edges being separated by a time duration proportional to the integer part of the number of Step of Time. A time delay is computed proportional to the fractional part of the number of Step of Time. The next active edge of the clock signal CK is delayed of said computed delay.
    Type: Grant
    Filed: June 10, 2006
    Date of Patent: February 1, 2011
    Assignees: Gemalto SA, STMicroelectronics, SA
    Inventors: Robert Leydier, Alain Pomet, Benjamin Duval
  • Publication number: 20100253301
    Abstract: A first capacitor is arranged such that the electric potential at a first terminal is fixed. A first discharging circuit discharges the first capacitor at a timing that corresponds to a cyclic synchronization signal received from an external circuit. A first comparator compares the voltage at a second terminal of the first capacitor with a predetermined threshold voltage, and generate a judgment signal that corresponds to the comparison result. A charging circuit generates a charging current the current value of which is adjusted according to the level of the judgment signal at a timing that corresponds to the synchronization signal, and supplies the charging current thus generated to the first capacitor.
    Type: Application
    Filed: March 25, 2010
    Publication date: October 7, 2010
    Applicant: ROHM CO., LTD.
    Inventors: Kenji NAKADA, Nobuaki UMEKI
  • Patent number: 7791420
    Abstract: A circuit includes a voltage-controlled oscillator (VCO), which includes a voltage input node having an input voltage; and a start-up circuit. The start-up circuit includes a first current path and a second current path. The first current path has a first current and is configured so that the first current increases in response to a decrease in the input voltage and decreases in response to an increase in the input voltage. The second current path has a second current and is configured so that the second current decreases in response to the decrease in the input voltage and decreases in response to the increase in the input voltage. The VCO further includes a third current path combining a first proportion of the first current and a second proportion of the second current into a combined current; and a current-controlled oscillator (CCO) including an input receiving the combined current and outputting an AC signal.
    Type: Grant
    Filed: December 9, 2008
    Date of Patent: September 7, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hung Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Min-Shueh Yuan
  • Patent number: 7787575
    Abstract: A method and system for synchronizing an input signal for a power system. The method comprises: extracting from the input signal, three substantially equidistant samples from a fundamental component of the input signal; determining a frequency (f1), an amplitude (A1), and a phase-difference (?Diff) of the input signal from the three equidistant samples and a tracking signal corresponding to a steady-state of the fundamental component of the input signal characterized by a frequency (fTS) and an amplitude (ATS) with a phase-difference that is the phase angle between the tracking signal and the input signal; and generating and outputting a frequency, amplitude, and phase-difference signals corresponding to the determined frequency (f1), amplitude (A1), and phase-difference (?Diff) of the input signal to one or more components of the power system.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: August 31, 2010
    Inventors: Francis P. Dawson, Hamid Shokrollah Timorabadi
  • Patent number: 7786816
    Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: August 31, 2010
    Assignee: Rambus Inc.
    Inventors: William J. Dally, Ramin Farjad-Rad, John W. Poulton, Thomas H. Greer, III, Hiok-Tiaq Ng, Teva J. Stone
  • Patent number: 7750748
    Abstract: A Method and an apparatus for distributing a clock signal are disclosed. The apparatus for distributing a clock signal includes a pair of flat plates, a variable inductor and a connection channel. The pair of flat plates includes a clock flat plate having at least one of clock signal extraction points and a reference flat plate arranged in parallel to the clock flat plate. The inductor is connected between the pair of flat plates, and the connection channel is configured to connect electrically the at least one of clock signal extraction points to an external circuit. The inductor may be adjusted to have an inductance for generating a resonance signal of a target frequency from the pair of flat plates.
    Type: Grant
    Filed: May 31, 2007
    Date of Patent: July 6, 2010
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jongbae Park, Jeonghyeon Cho, Joungho Kim
  • Patent number: 7741923
    Abstract: A transistor voltage-controlled oscillator (VCO) and a frequency synthesizer having the transistor VCO are provided. The frequency synthesizer adopts a divide-by-five injection-locked frequency divider, which includes a five-stage inverter ring oscillating frequency dividing circuit for reducing the operating frequency of the oscillating signal from the VCO, thus decreasing power consumption due to counting operation of the frequency synthesizer. The transistor VCO includes three transistor switching capacitor sets connected in parallel to one another to form a parallel structure. The gates of the transistor switching capacitor sets are connected to respective operating voltage sources, so as to switch the status of the corresponding transistor switching capacitor set, which in turn adjusts the harmonic frequency generated by the VCO, thereby allowing the VCO to generate a corresponding operating frequency with enough bandwidth.
    Type: Grant
    Filed: March 14, 2008
    Date of Patent: June 22, 2010
    Assignee: National Taiwan University
    Inventors: Ping-Yuan Deng, Jean-Fu Kiang
  • Patent number: 7741921
    Abstract: A Trigger-Mode Distributed Wave Oscillator that provides accurate multiple phases of an oscillation and a method of use of the same. An auxiliary oscillator triggers an oscillation on independent conductor loops or rings forming a differential transmission medium for the oscillation wave. Once the oscillation wave is triggered, the auxiliary oscillator can be powered down to turn it off, and the wave can sustain itself indefinitely through active amplifying devices which can compensate for losses in the conductors.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: June 22, 2010
    Assignee: Waveworks, Inc.
    Inventor: Damir Ismailov
  • Publication number: 20100123523
    Abstract: A standing wave oscillator (SWO) is formed from a microstrip transmission line or a stripline transmission line having a closed-loop single signal trace. Using the microstrip transmission line or stripline transmission line, the SWO can be formed with bends and in complex shapes, which are not so easily realized or possible using coplanar stripline (CPS) transmission lines. Simulation results demonstrate that the microstrip and stripline transmission line based SWOs provide superior operational characteristics (e.g., higher quality factors (Qs)) compared to a CPS transmission line based SWO of similar size and geometry.
    Type: Application
    Filed: November 17, 2008
    Publication date: May 20, 2010
    Inventors: Richard Walsworth, Koji Takinami
  • Patent number: 7671640
    Abstract: A direct injection-locked frequency divider circuit with inductive-coupling feedback architecture is proposed, which is designed for integration to a high-frequency circuit system with a high operating frequency such as 24 GHz (gigahertz), for providing a frequency-dividing function. The proposed frequency divider circuit comprises an injection-locked oscillator (ILO) circuit module and a pair of buffer-stage circuits, wherein the ILO circuit module further includes a signal-injection circuit, a cross-coupled switching circuit, and a variable-capacitance tuning circuit. The proposed circuit architecture is characterized by the circuit arrangement of a direct-injection architecture and an inductive-coupling feedback architecture by coupling the inductive elements of the buffer-stage circuits to the inductive elements of the variable-capacitance tuning circuit in the ILO circuit module.
    Type: Grant
    Filed: June 23, 2008
    Date of Patent: March 2, 2010
    Assignee: National Taiwan University
    Inventors: Wei-Yang Lee, Jean-Fu Kiang