Abstract: A system includes control circuitry configured to control an output signal. The control circuitry and/or various other sources of undesirable signal components may corrupt the control signal used by the control circuitry to correct the output signal. Conditioning circuitry may effect current-domain repair on the control circuitry by providing feedback-based conditioning actuation, including comparator overdrive, to the control circuitry.

Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.

Abstract: Provided is a relaxation oscillating circuit, which comprises a charging circuit, a discharging circuit, a switch circuit, a charging-discharging capacitor and an output circuit. The charging circuit comprises a first current source and a first isolating transistor. The discharging circuit comprises a second current source and a second isolating transistor. The switch circuit comprises a main charging transistor and an auxiliary charging transistor arranged as mirror and a main discharging transistor and an auxiliary discharging transistor arranged as mirror. The main charging transistor and the main discharging transistor are alternately conducted. According to a voltage of the charging-discharging capacitor, the output circuit outputs a clock signal and a control signal.

Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

Abstract: A method and apparats for undervoltage detection and correction is disclosed. An IC includes sensors implemented in various functional circuit blocks. The sensors are implemented using ring oscillators, and may be characterized by a polynomial. The sensors are used to monitor a supply voltage provided to a corresponding functional unit. The sensors provide information indicative of the voltage on the supply voltage node over successive clock cycles. Comparison circuitry may be used to compare the detected voltage to one or more voltage thresholds, while delta comparison circuitry may be used to determine a slope, or rate of change of the voltage. Based on comparisons performed by the comparison circuitry and the delta comparison circuitry, control circuitry may determine if one or more voltage correction actions are to be taken in order to bring the voltage on the supply node into a specified range.

Abstract: A feedback module for preventing voltage controlled oscillator (VCO) runaway in a phase locked loop (PLL) circuit can include a first, a second, and a third input to receive a first output signal from a PLL circuit, a reference signal, and a first control signal. The feedback module may also include a feedback circuit to generate a second control signal, the second control signal being coupled to an input of the PLL circuit, wherein the feedback circuit generates the second control signal by comparing a number of cycles of the first output signal to a first threshold, and a number of cycles of the reference signal to a second threshold.

Abstract: An oscillator and a semiconductor integrated circuit device with an internal oscillator capable of compensating the temperature characteristics even when there is a large parasitic capacitance too large to ignore directly between the output terminals of the oscillator. In an oscillator containing an inductance element L, and a capacitive element C, and an amplifier each coupled in parallel across a first and second terminal, the amplifier amplifies the resonance generated by the inductance element and capacitive element and issues an output from the first terminal and the second terminal, and in which a first resistance element with a larger resistance value than the parasitic resistance of the inductance element between the first terminal and the second terminal, is coupled in serial with the capacitive element between the first terminal and the second terminal.

Abstract: A power generation and transmission system, including: a wind turbine having an electrical generator (12) producing AC electrical power at a production frequency; a converter connected to the electrical generator (12) and configured to convert the AC electrical power to a transmission frequency below a grid frequency; an insulated transmission cable (18) connected to the converter and disposed at least partly submarine or subterranean; and a synchronous frequency converter (24) remote from the wind turbine and configured to receive the AC electrical power from the insulated transmission cable (18) and to convert it to the grid frequency for supply to a grid.

Abstract: An oscillator that includes a first source current leg and first sink current leg to source current and sink current, respectively, during a startup mode of oscillator operation. The oscillator includes a second source current leg and a second sink current leg to source current and sink current, respectively, during a second mode of oscillator operation.

Abstract: An injection locked pulsed oscillator includes a voltage controlled oscillator (VCO) responsive to an injection signal. The injection locked pulsed oscillator includes at least one enable circuit responsive to a first enable signal to enable output pulses from the VCO. The injection locked pulsed oscillator also includes timing circuit responsive to a pulse repetition frequency signal and is configured to provide the injection signal to phase lock the VCO and provide the first enable signal delayed from the injection signal to shape a width of the output pulses from the VCO.

Abstract: An oscillator system includes a first oscillator, a second oscillator, and a changeover component. The first oscillator is configured to generate a first signal at a selected frequency. The second oscillator is configured to generate a second signal at about the selected frequency. The changeover component is configured to generate a changeover output signal according to the first signal and the second signal.

Abstract: A method is provided for implementing a timer using a floating-gate transistor. The method includes: injecting a charge into a floating-gate transistor at an initial time, where a gate terminal of the floating-gate transistor is comprised of polysilicon encased by an insulating material; creating lattice imperfections at boundary of the polysilicon to cause leakage from the floating-gate transistor; measuring current read out from the floating-gate transistor at a time subsequent to the initial time; and determining an amount of time between the initial time and the subsequent time using the measured current.

Abstract: A pulse generator includes an oscillation circuit that generates a burst signal oscillated for ultrawideband band and a generation circuit that generates a trigger signal that causes oscillation by the oscillation circuit to be started.

Abstract: A method includes providing an oscillator having a field effect transistor connected with a resonant circuit. The field effect transistor has a gate electrode coupled to a source of gate voltage, a source electrode, a drain electrode and a graphene channel disposed between the source electrode and the drain electrode and electrically connected thereto. The method further includes biasing the graphene channel via the gate electrode into a negative differential resistance region of operation to cause the oscillator to generate a frequency signal having a resonant frequency f0. There can be an additional step of varying the gate voltage so as to bias the graphene channel into the negative differential resistance region of operation and out of the negative differential resistance region of operation so as to turn on the frequency signal and to turn off the frequency signal, respectively.

Abstract: A Force-Mode Distributed Wave Oscillator (FMDWO) that provides accurate multiple phases of an oscillation, a Force Mode Distributed Wave Antenna as a radiating element, a Force-Mode Distributed Oscillator Amplifier (FMDOA) and an array of amplifiers capable of operating as a beam forming phased-array antenna driver. Two distinct force mode mechanisms, one delay-based and the other geometry-based, utilizing inverter amplifiers, inject an oscillation on independent conductor loops or rings via transmission lines forming a differential transmission medium for the oscillation wave. Once the oscillation wave is initiated through the forcing mechanisms, the oscillations continue uninterrupted independent of any external triggering.

Abstract: An oscillating circuit for determining a resonant frequency of an electro-mechanical oscillating device and for driving the electro-mechanical oscillating device at the determined resonant frequency includes a driving circuit and a start-up, impetus injection circuit. The driving circuit is configured to receive one or more reference signals and further configured to provide a driving signal related to the reference signals to the electro-mechanical oscillating device. The start-up, impetus injection circuit is operably coupled to the electro-mechanical oscillating device and configured to selectively provide a start-up excitation signal to the electro-mechanical oscillation device. The start-up, impetus injection circuit is activated upon start-up of the oscillating circuit to drive the electro-mechanical oscillation device and the driving circuit determines a resonant frequency by measuring a parameter related to the resonant frequency of the electro-mechanical oscillating device.

Abstract: Systems and methods for generating pulsed output signals that employ a gated RF oscillator circuit having an output that is switchably grounded through the emitter of a transistor and including feedback from the output of the circuit to the base of the transistor to create oscillations and to allow a digital input pulse of a desired length to control the start and stop of oscillations created by the transistor.

Abstract: A system for managing a reference clock signal includes an XO; a signal buffer coupled to the XO and configured to drive a reference clock signal generated by the XO; and a first IC coupled to the signal buffer. The first IC includes an XO input buffer configured to receive the reference clock signal, to switch between an enabled, operational state and a disabled state, and to have a first operational impedance while in the enabled state; an impedance equivalence circuit configured to be in an enabled, operational state when the XO input buffer is in its disabled state and vice versa and to have a second operational impedance while in the enabled state that is equivalent to the first operational impedance; and a control mechanism configured to switch the XO input buffer and the impedance equivalence circuit between the enabled state and the disabled state.

Abstract: In accordance with some embodiments of the present disclosure, an oscillator may include a crystal resonator and a squaring circuit coupled to the crystal resonator and configured to convert a sinusoidal signal produced by the crystal resonator to a square-wave signal, the squaring circuit comprising a bias circuit configured to transmit a selected bias voltage for the squaring circuit, the selected bias voltage selected from a plurality of potential bias voltages. In accordance with this and other embodiments of the present disclosure, an oscillator may include a crystal resonator, an inverter coupled in parallel with the crystal resonator, and a programmable voltage regulator coupled to the inverter. The programmable voltage regulator may be configured to supply a first supply voltage to the inverter during a startup duration of the oscillator, and supply a second supply voltage to the inverter after the startup duration, wherein the second supply voltage is lesser than the first supply voltage.

Abstract: A semiconductor integrated circuit capable of reliably detecting oscillation stop of a vibrator-type oscillation circuit and reliably restarting the oscillation circuit when oscillation stop is detected is provided. The semiconductor integrated circuit includes one or more main oscillation circuits configured to generate a main clock signal by a vibrator, a ring oscillator configured to always operate independently of the main oscillation circuit, a main clock detection circuit configured to monitor the main clock signal on the basis of an output clock signal of the ring oscillator and to determine an operation state of the main oscillation circuit, and an switch circuit configured to switch a combination of elements making up the main oscillation circuit in response to a detection result of the main clock detection circuit.

Abstract: A variable injection-strength injection-locked oscillator (ILO) is described. The variable injection-strength ILO can output an output clock signal based on an input clock signal. The variable injection-strength ILO can pause, restart, slow down, or speed up the output clock signal synchronously with respect to the input clock signal in response to receiving power mode information. Specifically, the variable injection-strength ILO can be operated under relatively strong injection when the input clock signal is paused, restarted, slowed down, or sped up.

Abstract: An oscillating signal generating device includes an oscillating circuit and a control circuit. The oscillating circuit includes: a resonator having a first terminal and a second terminal for generating an oscillating signal, a resistive element having a first terminal coupled to the first terminal of the resonator, and a second terminal coupled to the second terminal of the resonator, and an oscillating start-up circuit having an input terminal coupled to the first terminal of the resonator and an output terminal coupled to the second terminal of the resonator. The control circuit generates a control signal to change the oscillating start-up circuit into a disable mode from an enable mode when the oscillating circuit generates an oscillating output signal under an operation mode, and outputs the oscillating signal generated by the resonator as the oscillating output signal of the oscillating circuit.

Abstract: According to an exemplary embodiment, a high amplitude oscillation generator includes an LC tank circuit, a gain stage, a dynamic bias circuit, a bias current source, and a dynamic bias circuit receiving a current source feedback voltage and outputting a gain stage bias voltage. The dynamic bias circuit adjusts the gain stage bias voltage in response to a change in the current source feedback voltage after a start up of the LC tank circuit. The dynamic bias circuit thereby increases an amplitude of oscillations produced by the oscillation generator. The dynamic bias circuit can include an error amplifier, the error amplifier generating the gain stage bias voltage responsive to the current source feedback voltage. The current source feedback voltage can change with a voltage drop across the bias current source. The current source feedback voltage can also be received from an output of the oscillation generator.

Abstract: A pulse generator includes an oscillation circuit that generates a burst signal oscillated for ultrawideband band and a generation circuit that generates a trigger signal that causes oscillation by the oscillation circuit to be started.

Abstract: A SAR ADC includes a DAC including a first set of capacitors each having a first end connected to a common node, and a second end, and a first set of switches each connecting the second end of a respective one of the capacitors to a first reference voltage. The SAR ADC further includes a second set of capacitors each having a first end connected to the common node and a second end that receives an input to be converted when the common node is connected to ground. The SAR ADC further includes a second set of switches that selectively connect the second end of a first capacitor of the second set of capacitors to ground when the input is disconnected from the second ends of the second set of capacitors and when the common node is disconnected from ground during a first of a plurality of successive approximations.

Abstract: A method for generating an UWB pulses based on LC oscillator topology. Fast turn on of the oscillator is achieved by creating large asymmetry in a normally symmetrical topology which is used in a typical differential type oscillator. One method for achieving large asymmetry is activating one branch of a differential pair of branches for a short duration before activating both branches in a normal operation. The bandwidth of the pulse is controlled by modifying the duration of the oscillator activation. Fast turn on and turn off is essential for high bandwidth generation. The method is adaptable for generating binary phase shift keying (BPSK) modulation. Selecting the activated branch of a fully symmetrical topology controls the output phase and creates two possibilities which differ exactly by 180 degrees. In a preferred embodiment, all the pulse generator components are on-clip leading to a low cost solution. The circuit can generate high power pulses directly on a load.

Abstract: An oscillating circuit for determining a resonant frequency of an electro-mechanical oscillating device and for driving the electro-mechanical oscillating device at the determined resonant frequency includes a driving circuit and a start-up, impetus injection circuit. The driving circuit is configured to receive one or more reference signals and further configured to provide a driving signal related to the reference signals to the electro-mechanical oscillating device. The start-up, impetus injection circuit is operably coupled to the electro-mechanical oscillating device and configured to selectively provide a start-up excitation signal to the electro-mechanical oscillation device. The start-up, impetus injection circuit is activated upon start-up of the oscillating circuit to drive the electro-mechanical oscillation device and the driving circuit determines a resonant frequency by measuring a parameter related to the resonant frequency of the electro-mechanical oscillating device.

Abstract: A clock and data recovery circuit is disclosed and comprises a gated voltage-controlled oscillator (GVCO), a PLL unit, a phase-controlled frequency divider, a multiplexer, a matching circuit and a double-edge-triggered D flip-flop (DDFF). The GVCO receives a data signal and a reference voltage to generate first and second clock signals. The PLL unit receives a reference clock signal and generates the reference voltage to adjust the first and second clock signals at the vicinity of the predetermined frequency. The phase-controlled frequency divider receives and divides the first clock signal by N to output a third clock signal. The multiplexer controlled by a selection signal receives and outputs the second or the third clock signal. The matching circuit receives the data signal and the selection signal to match the delays therebetween. The DDFF receives the output signals from the matching circuit and the multiplexer, and outputs a recovered data signal.

Abstract: An oscillation circuit, and a semiconductor device incorporating same, include: an oscillation unit with a plurality of inverters and configured to perform signal transmission between first and second nodes of the inverters such that each of the inverters performs an oscillation operation to generate clock signals having different phases when a control signal is activated, and latch a clock signal of the second node and cut off the signal transmission between the first and second nodes to stop the oscillation operations of the inverters when the control signal is deactivated; and a control unit to activate the control signal when an oscillation enable signal is activated, and deactivate the control signal using one of a clock signal output from an inverter connected to the second node and clock signals of which the phases lag that of a clock signal of the first node, when the oscillation enable signal is deactivated.

Abstract: Disclosed is an oscillator in which current consumption relating to oscillation is reduced. The oscillator comprises: an amplifier to an input and output of which a piezoelectric oscillator and a feedback resistor are connected in parallel, and which is constituted by a CMOS logic inverter circuit; and a control circuit, which is constituted by a CMOS logic circuit, for clamping input/output levels of the amplifier and halting oscillation before oscillation start-up, unclamping the input/output levels at beginning of oscillation start-up and supplying a pulse signal to an output terminal of the amplifier a prescribed period of time after the beginning of oscillation start-up.

Abstract: An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a number of waves of the output signal within a predetermined period is smaller than a predetermined value, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate.

Abstract: An oscillator that increases the accuracy of an output frequency, without using a charge pump, has an oscillation circuit, first and second voltage supply circuits, and a calibration value generation circuit. The first voltage supply circuit includes a resistor and a capacitor, the resistance and capacitance of which are determined so that a first voltage reaches a reference voltage within a reference time. The second voltage supply circuit includes first and second switching means, which perform switching when receiving pulse signals corresponding to the frequency of the oscillation circuit to raise the second voltage. A calibration value generation circuit provides the oscillation circuit with a calibration value that lowers the frequency when the second voltage reaches the reference voltage before the first voltage and raises the frequency when the second voltage reaches the reference voltage after the first voltage.

Abstract: A synchronized clock system, for use with an electronic system having several system nodes requiring a synchronized clock signal. The clock system may be formed in either discrete form or in integrated form, or in any combination, and includes a first synch bus and a second synch bus, isolated from the first synch bus, and at least one pair and preferably several pairs of SXO modules connected to the busses in alternating fashion. Each of the system nodes is connected at a different one of any number of arbitrarily selected connection points anywhere along the first bus. The points along the busses at which the SXO modules are connected are spaced roughly equidistantly apart. The system nodes are connected to the bus by means of signal conditioning circuits, which may include correction circuits, an amplifier, a frequency multiplier, a logic translator and a fan buffer.

Abstract: A relaxation oscillator includes a capacitor connected to a comparator input, current sources switched to supply power to the capacitor based on an output of the comparator, and a duplicate integrator shifting a voltage on the capacitor to offset a propagation delay through the comparator. The duplicate integrator includes current sources and a capacitor matching and switched in tandem with those within the relaxation oscillator, plus an additional current source, and is selectively switched into connection with the comparator input. By canceling the comparator propagation delay, the oscillator output frequency can be stably controlled through selection of resistive and capacitive values, using cheaper technology and tolerating large temperature, voltage and process variations.

Abstract: Provided are an oscillatory circuit based on a metal-insulator transition (MIT) device that can generate a simple and very high oscillating frequency using the MIT device, and a method of driving the oscillatory circuit. The oscillatory circuit includes the MIT device that comprises an MIT thin film and an electrode thin film connected to the MIT thin film and in which an abrupt MIT is generated due to an MIT generating voltage, a resistor that is serially connected to the MIT device, an electric al power source limiting the maximum amount of an applied current and applying a direct current constant voltage to the MIT device, and a light source irradiating electromagnetic waves on the MIT device, wherein the oscillating properties are generated by irradiating the electromagnetic waves using the light source.

Abstract: Provided are an MIT device-based oscillation circuit including a power source, an MIT device and a variable resistor, in which a generation of an oscillation and an oscillation frequency are determined according to a voltage applied from the power source and a resistance of the variable resistor, and a method of adjusting the oscillation frequency of the oscillation circuit. The MIT device includes an MIT thin film and an electrode thin film connected to the MIT thin film, and generates a discontinuous MIT at an MIT generation voltage, the variable resistor is connected in series to the MIT device, and the power source applies a voltage or an electric current to the MIT device. The generation of an oscillation and an oscillation frequency are determined according to the voltage applied from the power source and the resistance of the variable resistor.

Abstract: The present invention is a Chip Scale Atomic Clock (CSAC)-enabled Time and Frequency Standard (CTFS) architecture. The CTFS architecture includes a microcontroller, a Time Compensated Crystal Oscillator (TCCO) circuit which is connected to the microcontroller, and a Chip Scale Atomic Clock (CSAC) which is connected to the microcontroller. The microcontroller is configured for selectively causing the CTFS to provide a TCCO circuit-based output frequency when the CTFS has not locked to a predetermined atomic resonance, and is further configured for causing the CTFS to provide a CSAC-based output frequency when the CTFS has locked to a predetermined atomic resonance.

Abstract: A driver device that forms an oscillation loop with a vibrator and causes the vibrator to produce driving vibrations includes a current-voltage converter that converts a current that flows through the vibrator into a voltage, an output circuit that causes the vibrator to produce the driving vibrations based on a signal that is converted into a voltage with respect to a given voltage, and a high-pass filter that is provided in the oscillation loop between the current-voltage converter and the output circuit. The driver device causes the vibrator to produce the driving vibrations while changing a reference potential of the high-pass filter, and then causes the vibrator to produce the driving vibrations while fixing the reference potential.

Abstract: A multi-phase ultra-wideband signal generator uses differential pulse oscillators. The multi-phase ultra-wideband signal generator using differential pulse oscillators includes N pulse oscillators for generating pulse signals based on a supply of power, and further comprises N inverting amplification units for outputting inverted amplified signals of output signals of the N pulse oscillators when a number of pulse oscillators is at least two, wherein, when the number of pulse oscillators is an even or odd number, the pulse oscillators are arrayed such that they have a connection form in which output terminals OUT(+) and OUT(?) of a relevant pulse oscillator are connected to output terminals OUT(+) and OUT(?) of a next pulse oscillator through a relevant inverting amplification unit, and the connection form is consecutively applied to the pulse oscillators.

Abstract: Embodiments of the present invention include a low phase noise oscillator circuit using a current-reuse technique to reduce power consumption and improve phase noise, where the oscillator circuit comprises a first VCO coupled to a second VCO, and the outputs of the first and second VCOs are coupled with passive elements, such as capacitors. The overall power consumption of both the first and second VCOs is about the same as a single VCO. Furthermore, the phase noise is lowered by around 3 dB. Thus, the phase noise performance is improved without increasing the power consumption of the oscillator circuit.

Abstract: A phase locked loop circuit includes an oscillator part configured to generate a reference signal by amplifying a signal generated by an oscillator, and a phase locked loop part configured to include a filter that outputs a control signal to a clock transmitting circuit that generates a clock signal in accordance with a phase difference between the reference signal and a feedback signal, wherein a drive capability of the oscillator part is controlled in accordance with the control signal.

Abstract: A variable frequency oscillating circuit has an oscillating circuit that undergoes an oscillation operation. The oscillating circuit has at least one inverter and at least one capacitor forming a circuit in a ring oscillator configuration. A current circuit outputs a current based on a frequency control signal controlling a frequency of a clock signal output from the oscillating circuit. A pulse generating circuit generates a pulse when the frequency control signal is switched from low to high and from high to low. The oscillating circuit stops an oscillation operation by stopping a charge/discharge operation of the at least one capacitor when the pulse is generated by the pulse generating circuit.

Abstract: Disclosed is a logarithmic detector comprising: an amplifier element; means for setting a frequency of operation of the detector; and a controller, wherein an input signal to the amplifier element is arranged to cause an oscillation in the amplifier element, and the controller is operable to sense a pre-determined threshold, indicative of oscillation and, in response to sensing said threshold, to interrupt the oscillation of the amplifier such that the frequency of said interruption is proportional to the logarithm of the power of the input signal.

Abstract: An adaptive intelligent electronic horn (100) comprises a mechanical soniferous apparatus (112), an electromagnetic coil (106), a driver circuit (104) and an oscillating circuit (102). A sensor (110) is provided between the mechanical soniferous apparatus (112) and the oscillating circuit (102). An on-off ratio adjusting circuit (108) is provided at the input end of the oscillating circuit (102). The sensor (110) measures the oscillation frequency of the mechanical soniferous apparatus (112) and feedbacks the measured oscillation frequency signal to the oscillating circuit (102). The on-off ratio adjusting circuit (108) controls a pulse width of an oscillation signal from the oscillating circuit (102) based on a voltage of power supply and/or an ambient temperature. The oscillating circuit (102) outputs corresponding oscillation signal to the driver circuit (104) based on the oscillation frequency signal received from the sensor (110) and/or the control signal from the on-off ratio adjusting circuit (108).

Abstract: A circuit arrangement for detecting voltage changes, comprising supply terminals configured to apply a first potential and a second potential, a first oscillator and a second oscillator, which are operated with the first potential and the second potential, a voltage dependence of the frequency of the first oscillator differing from a voltage dependence of the frequency of the second oscillator, a first evaluation circuit configured to evaluate the frequency of the first oscillator and a second evaluation circuit configured to evaluate the frequency of the second oscillator, and a comparison circuit configured to compare a value based on the evaluated frequencies of the first oscillator and of the second oscillator with a predetermined threshold value, and to output a voltage change signal indicating an impermissible voltage change between the first potential and the second potential depending on the result of the comparison.

Abstract: Ring oscillator circuitry is provided. The ring oscillator circuitry may include a loop of inverters. A control gate may be interposed in the loop to control operation of the loop. The control gate may be activated using a ring oscillator trigger signal. During application of the trigger signal, the trigger signal may become degraded due to circuit parasitics. Trigger signal conditioning circuitry may be used to remove noise from the degraded trigger signal. A version of the trigger signal that has been conditioned by the trigger signal conditioning circuitry may be applied to a control input of the control gate. The trigger signal conditioning circuitry may include a low pass filter, a hysteresis circuit, and a two-stage buffer. The two-stage buffer may be formed from transistors with the same characteristics as the transistors in the inverters of the ring oscillator loop.

Abstract: An oscillation circuit, a driving circuit thereof, and a driving method thereof are provided. The driving circuit generates a second enable signal according to an output signal of an oscillator and a first enable signal. The second enable signal is transmitted to the oscillator. When a wave number of the output signal is smaller than a predetermined value during a predetermined period, the driving circuit adjusts a voltage level of the second enable signal. A voltage level of the first enable signal is equal to an enable voltage level. Through variations in voltage levels of the second enable signal, the oscillator is triggered to oscillate.

Abstract: An oscillation driver circuit that drives a physical quantity transducer includes a one-input/two-output comparator. The one-input/two-output comparator includes a shared differential section that compares a voltage signal input from a drive current/voltage conversion amplifier circuit with a given voltage, a first output section that receives a signal output from the differential section, variably adjusts a voltage amplitude of the received signal, and outputs the resulting signal, and a second output section that receives the signal output from the differential section, and outputs a synchronous detection reference signal of which the voltage amplitude is fixed.

Abstract: A differential crystal oscillator circuit uses a bias transistor to generate a bias voltage from a bias current. The bias voltage is supplied to the control terminals of a differential pair of transistors. The differential transistors operate to produce a differential output between corresponding end terminals thereof, which is provided to a reference crystal oscillator to establish an oscillation frequency at the differential output.

Abstract: A circuit can include an amplifier having at least a first junction field effect transistor (JFET) of a first conductivity type with a source coupled to a first power supply node, and a drain coupled to an amplifier output node. A first variable bias circuit can be coupled between the drain and at least one gate of the first JFET. The first variable bias circuit can alter a direct current (DC) bias to the first JFET according a potential at the amplifier output node. A first bias impedance can be coupled between the drain of the first JFET and a second power supply node. The circuit can also include a non-linear transmission line (NLTL) coupled between the amplifier output and a gate of the first JFET. The NLTL being configured to propagate an electrical soliton.