Abstract: According to an exemplary embodiment, a high amplitude oscillation generator includes an LC tank circuit, a gain stage, a dynamic bias circuit, a bias current source, and a dynamic bias circuit receiving a current source feedback voltage and outputting a gain stage bias voltage. The dynamic bias circuit adjusts the gain stage bias voltage in response to a change in the current source feedback voltage after a start up of the LC tank circuit. The dynamic bias circuit thereby increases an amplitude of oscillations produced by the oscillation generator. The dynamic bias circuit can include an error amplifier, the error amplifier generating the gain stage bias voltage responsive to the current source feedback voltage. The current source feedback voltage can change with a voltage drop across the bias current source. The current source feedback voltage can also be received from an output of the oscillation generator.

Abstract: A gain control circuit, suitable for controlling the amplitude of a voltage-controlled oscillator, includes a duty cycle detector, an analog-to-digital converter, and a function generator. The gain control circuit provides a digitally enabled negative feedback loop. The duty cycle detector generates an estimate of the amplitude. The function generator receives a target amplitude as well as a digital representation of the estimate of the amplitude. The function generator calculates a modified estimate and periodically compares the same to the target value to generate a control word. The control word is arranged to enable current sources in the voltage-controlled oscillator.

Abstract: The present invention is a method for reducing phase noise in oscillator signals. For example, the oscillator may be a low phase noise MEMS-based oscillator and may include a resonator (ex.—a MEMS resonator). Further, the resonator of the oscillator may be operated near a bifurcation point. Still further, the MEMS resonator may be parametrically pumped in such a way so as to redistribute the quadrature signal noise (ex.—phase noise) to in-phase noise (ex.—amplitude noise).

Abstract: Reducing a gain of a VCO, which may be used in a serdes system, includes using an oscillator replicating the VCO. The oscillator frequency varies according to PVT conditions of circuit elements of the oscillator, which affect a speed of the circuit elements. A first circuit receives an output of the oscillator to produce a current that varies inversely proportionally to the oscillator frequency. A second circuit injects the current into a power supply line of the VCO. Thus, high VCO frequencies can be attained. By reducing the gain of the VCO, thermal noise contribution of the loop resistor and the loop capacitor required for desired loop bandwidth are reduced. During fast corner conditions, minimal current is injected into the VCO. During slow corner conditions, high current is injected into the VCO. These help keep VCTRL of the PLL loop close to a mid-rail operating region.

Abstract: Some embodiments regard a method comprising: generating a current according to a movement of the MEMS device; the movement is controlled by a control signal; generating a peak voltage according to the current; and adjusting the control signal when the peak voltage is out of a predetermined range.

Abstract: A crystal oscillator clock circuit which facilitates switching its output between an internally generated clock signal and an externally generated clock signal. A feedback loop detects the presence of an externally generated clock signal applied to an output pin of a crystal oscillator circuit and powers down the internally generated clock signal. As a result, the crystal oscillator clock circuit simply passes the externally generated clock signal as its output signal.

Abstract: An oscillator comprises an inverter, with a resonator connected between an input and an output of the inverter. A transistor external to the inverter is connected in a current mirror mode with a transistor of the inverter so that the inverter's transistor copies the current of the external transistor. The external transistor has its drain terminal connected to the gate terminals of the inverter's transistor and of the external transistor. A current source is connected to the gate terminal of the inverter's transistor, and a switch is connected between the drain and gate terminals of the external transistor. Circuitry controls the switch so as to open the connection between the drain and gate terminals of the external transistor at the beginning of a start-up phase of the oscillator.

Abstract: There is provided an oscillator circuit including: a current source; a resonant unit; an oscillation amplification unit connected to the current source while being connected in parallel to the resonant unit; a feedback resistor connected in parallel to the oscillation amplification unit; a bypass resistor having a resistance lower than a resistance of the feedback resistor; a switch unit connected between the feedback resistor and the bypass resistor, and configured to switch to the feedback resistor or the bypass resistor; and a control unit configured to control the switch unit such that a current from the current source is bypassed to the bypass resistor during a predetermined oscillation starting period, and to control the switch unit such that the current from the current source flows to the feedback resistor after the predetermined oscillation starting period has ended.

Abstract: A disclosed current source circuit includes a current mirror circuit having two enhancement-type MOS transistors, a depletion-type MOS transistor configured to be connected to a drain of one of the two enhancement-type MOS transistors and to function as a constant current source, and a resistor configured to have a negative temperature property and be connected to a source of the one of the two enhancement-type MOS transistors.

Abstract: A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connected to the input of the VCO buffer and the gate of a p-type metal-oxide-semiconductor field effect (PMOS) transistor. The circuit further includes a first switch connected to the first capacitor and the gate of the PMOS transistor. The circuit also includes a third capacitor connected to the input of the VCO buffer. The circuit further includes a fourth capacitor connected to the input of the VCO buffer and the gate of an n-type metal-oxide-semiconductor field effect (NMOS) transistor. The circuit also includes a second switch connected to the third capacitor and the gate of the NMOS transistor.

Abstract: Disclosed is a semiconductor integrated circuit device that includes a ring oscillator circuit, performs a proper oscillation operation, and expands the range of oscillation frequency variation. The ring oscillator circuit includes, for instance, plural differential amplifier circuits. MOS transistors are respectively added to input nodes of a differential pair of the differential amplifier circuits. Further, gate control circuits are incorporated to control the gates of the MOS transistors, respectively. The gate control circuits cause the MOS transistors to function as an amplitude limiter circuit in mode 3, exercise control to turn off the amplitude limiter circuit in mode 2, and use the amplitude limiter circuit to start oscillation in mode 1.

Abstract: An apparatus for generating an oscillating signal including an oscillator configured to generate the oscillating signal, a controller configured to generate a control signal that controls a characteristic (e.g., amplitude or frequency) of the oscillating signal, and a power supply configured to supply power to the oscillator as a function of the control signal. The power supply may be configured to supply power to the oscillator as a function of the amplitude or frequency of the oscillating signal to improve power efficiency.

Abstract: Disclosed herein is a delay circuit for a low power ring oscillator. The delay circuit includes: a pair of N type transistors that receive first differential input signals Vin1+ and Vin1?; a pair of P type transistors that receive second differential input signals Vin2+ and Vin2?; a differential output terminal that outputs differential output signals Vout+ and Vout? generated from the pair of N type transistors and the pair of P type transistors; an N type detector that supplies a body voltage to the pair of N type transistors; and a P type detector that supplies a body voltage to the pair of P type transistors.

Abstract: With some embodiments, a VCO (voltage controlled oscillator) operates at an integer multiple (N) above a desired transmission frequency. In accordance with one embodiment, a chip is provided with a VCO to generate a signal and a frequency dividing circuit to provide a reduced frequency version of the signal to a transmit mixer. The transmit mixer is followed by a power amplifier that is on the same die as the VCO. The power amplifier is to generate an OFDM output transmission.

Abstract: A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein the amplitude control unit is configured to determine the amplitude of a VCO output signal based on a voltage present on the tail node. The amplitude control unit may also be configured to generate a bias voltage based on the amplitude of the VCO output signal and a target voltage. The bias control circuit may be coupled to receive the bias voltage from the amplitude control unit and may be further configured to adjust the voltage on the tail node based on the received bias voltage.

Abstract: Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first reference signal having a resonant frequency, with the reference resonator having a first temperature dependence; and a plurality of switchable circuits, with at least one switchable circuit providing a second temperature dependence opposing the first temperature dependence to maintain the resonant frequency within a predetermined variance over a temperature variation.

Abstract: An exemplary fast start-up crystal oscillator with reduced start-up time. The exemplary oscillator reduces the start-up time (i.e., the time taken to attain sustained stable oscillations after the power is turned on) by increasing the negative resistance of a circuit. Increasing the negative resistance increases the rate of growth of the oscillations, thereby reducing start-up time. The exemplary crystal oscillator includes a gain stage with negative resistance. A crystal with shunt capacitance is placed in the feedback loop of the gain stage. A buffer is coupled to the gain stage such that it blocks the crystal shunt capacitance from loading the gain stage, effectively increasing the negative resistance of the gain stage. Further, an oscillation detection and control circuit is coupled between the crystal and the gain stage. The oscillation detection and control circuit connects the buffer during start-up, and disconnects the buffer once an oscillation signal attains sustained stable oscillations.

Abstract: A semiconductor device having a phase-locked loop (“PLL”) (100) drives a VCO (114) of the PLL circuit with a first control voltage (VCTRL) produced by a loop filter (112) when a first clock signal (clk_ref) is present. The VCO produces an output frequency while the PLL circuit is operating off the first clock signal. When the first clock signal is lost (ref_lost), a control voltage maintenance circuit (120) produces a second control voltage maintaining the VCO output frequency. In one device, the control voltage maintenance circuit includes a phase-frequency detector (104) that can operate off of either the clock reference signal or a master clock signal. In an alternative device, the control voltage maintenance circuit includes a voltage generator (334, 362) that produces a generated voltage that drives the loop filter when lock is lost.

Abstract: A PLL circuit includes a phase detector, a loop filter (LF), a voltage-controlled oscillator (VCO), and a frequency divider. The phase detector compares a phase of a signal Fs which is input from outside with a phase of a signal Fo/N which is input from the frequency divider. The loop filter generates a signal Vin by removing alternating current components from a signal input from the phase detector. The voltage-controlled oscillator outputs a signal Fo based on the signal Vin input from the loop filter. The frequency divider converts the signal Fo output from the voltage-controlled oscillator into Fo/N (frequency division by N), and outputs it to the phase detector.

Abstract: A system for providing voltage and current regulator sources based on a oscillator having variable loop gain is described. Only when the oscillator loop gain is at least the value of one does the oscillator oscillate. The oscillator's ability to oscillate is controlled by the one or more variable impedance or gain devices. Negative feedback of the voltage or current output level is used to control the loop gain of the oscillator circuit.

Abstract: Exemplary embodiments of the invention provide a reference signal generator having a controlled quality (“Q”) factor. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, which generates a first reference signal having a resonant frequency, and a plurality of reactance modules couplable to the reference resonator. Each reactance module comprises one or more reactance unit cells, and each reactance unit cell comprises a reactance element coupled in series to a switching element. In exemplary embodiments, the reactance element is a capacitor having a predetermined unit of capacitance, and the switching element is a transistor having a predetermined resistance when in an off state. The ratio of capacitance to resistance is substantially constant for all reactance modules of the plurality of reactance modules.

Abstract: The fundamental breakthrough in green technology are the Varactor Free Amplitude Controlled Oscillator VFACO and the planar EMI-Free Planar Inductor. The VFACO makes the fine tune for oscillation frequency. It has the frequency compensation over temperature. It doesn't have the VCO self-modulation-induced phase noise. It is phase-noiseless. It is high-Q and high stability. It increases the communication capacity. The EMI-Free Planar Inductor is the backbone of the platform of green technology. The platform of green technology contains the Xtaless ClockChip, Inductorless PMU & PA and ESDS-PCB to provide the green technology for green chip design. Especially for the 4th generation wireless communication, the Inductorless PMU & PA are the most important green technology. The Xtaless ClockChip adopts the most advanced self-compensation Amplitude controller. The ESDS-PCB has the minimum Via assignment algorithm to make the optimum pin assignment for the platform of green technology.

Abstract: A method and circuitry for calibrating the gain of a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a comparator configured to provide a first indication if the VCO gain is not within the specified gain range, and a second indication if the VCO is within the specified gain range. The circuit further includes a control unit configured to, upon occurrence of at least a first cycle of a clock signal, cause adjustment of the VCO gain responsive to receiving the first indication. For each one or more successive cycles of the clock signal, the control unit is configured to cause corresponding adjustments of the VCO gain until the comparator provides the second indication. The control unit is configured to discontinue adjustments to the VCO gain responsive to receiving the second indication.

Abstract: A voltage-controlled variable frequency oscillation circuit, includes: an oscillation circuit section including a resonance circuit which includes a coil and a variable capacitance element, and a negative resistance circuit; and a first resistor connected between the oscillation circuit section and a first one of a pair of terminals of a power supply.

Abstract: A differential oscillation circuit according to the present invention is a differential oscillation circuit including a feedback loop circuit. The differential oscillation circuit includes: delay, circuits, cascade-connected one after another on the feedback loop circuit, each delay circuit configured to delay paired differential input signals which the delay circuit receives, and to output the delayed differential signals as paired differential output signals; and an oscillation activation detector circuit configured to detect whether the oscillation circuit is in an oscillation activation state or in a stable state, and to output a detection signal indicating a result of the detection. Furthermore, on the basis of the detection signal outputted from the oscillation activation detector circuit, each of the delay circuits controls output current values of the differential output signals. This circuit configuration enables the speeding up of the oscillation frequency of the circuit.

Abstract: A low jitter and wide-range frequency synthesizer for low voltage operation includes a detector to generate a detection signal based on a logic level difference between an input signal and a feedback signal, a charge pump to generate a control signal based on the detection signal, a filter to generate a tuning signal based on the control signal, a bias circuit to generate a first bias signal and a second bias signal based on the tuning signal, a controllable oscillator to generate a differential output signal based on the first and the second bias signals, a differential to single ended converter to convert the differential output signal into an output signal, and a programmable frequency divider to generate the feedback signal based on the output signal.

Abstract: A crystal oscillator emulator integrated circuit includes a first temperature sensor configured to sense a first temperature of the crystal oscillator emulator integrated circuit. The memory is configured to (i) store calibration parameters and (ii) select at least one of the calibration parameters based on the first temperature. A semiconductor oscillator is configured to generate an output signal, wherein (i) the output signal has a frequency and an amplitude and (ii) the frequency is based on the at least one of the calibration parameters. An amplitude adjustment module is configured to (i) compare the amplitude to a predetermined amplitude and (ii) generate a control signal to adjust the amplitude based on the comparison.

Abstract: There is provided an oscillator circuit including: a current source; a resonant unit; an oscillation amplification unit connected to the current source and connected in parallel to the resonant unit; a feedback resistor connected in parallel to the oscillation amplification unit; a switch unit having a first end connected to the current source side of the oscillation amplification unit; a replica circuit connected between a second end of the switch unit and a ground side of the oscillation amplification unit and having a configuration identical to a configuration of the oscillation amplification unit; and a level detecting unit that detects an input voltage of the oscillation amplification unit, and, when the detected input voltage is higher than a bias voltage level at a time of oscillation, cause the switch unit to allow a current from the current sources to bypass through the replica circuit.

Abstract: An amplitude control circuit (100) can include a peak level detect circuit (102) that generates a peak voltage signal (Vpeak?) based on a peak level of signal Xosc. An amplitude bias control circuit (104) can generate a bias voltage Vbc that can correspond to a peak amplitude of a received oscillator signal Xosc, and can change according to variations in a transistor threshold voltage due to process, operating conditions and voltage.

Abstract: An apparatus for generating an oscillating signal including an oscillator configured to generate the oscillating signal, a controller configured to generate a control signal that controls a characteristic (e.g., amplitude or frequency) of the oscillating signal, and a power supply configured to supply power to the oscillator as a function of the control signal. The power supply may be configured to supply power to the oscillator as a function of the amplitude or frequency of the oscillating signal to improve power efficiency.

Abstract: This invention includes a bias origination section configured to originate an original bias voltage; a comparison section configured to compare the original bias voltage and a comparison voltage, and output a comparison result; a resistive divider section composed by a resistance circuit including a variable resistor section having a resistor and a switch, and configured to generate the comparison voltage; a bias decision control section configured to determine bias decision data for controlling a resistance value of the variable resistor section so as to bring the comparison voltage close to the original bias voltage, based on a comparison result of the comparison section; and a storage section configured to hold the bias decision data and also output the comparison voltage as a bias voltage by controlling a resistance value of the variable resistor section based on the held bias decision data, thereby generating a low-noise bias with a small area.

Abstract: A self-biased PLL includes a first charge pump and a second charge pump, an output terminal of the first charge pump is connected with a discharge-charge capacitor to output a control voltage, an output terminal of the second charge pump is connected with an output terminal of a bias generator for outputting a first bias voltage equal to the control voltage, wherein, a current output from the first charge pump is equal to a value obtained through dividing the production of a first constant with a bias current of a voltage control oscillator by a frequency division factor of a frequency divider; a current output from the second charge pump is equal to a value obtained through dividing the bias current of the voltage control oscillator by a second constant; and a multiple relation exists between an output resistance of the bias generator and an equivalent resistance of a differential buffer delay stage in the voltage control oscillator.

Abstract: This invention discloses a clock generator capable of automatically adjusting output clock when process, voltage, or temperature variation occurred. The clock generator comprises a current generator, for generating a first current and a second current according to a control voltage; a oscillator, coupled to the current generator, for generating a clock signal according to the first current; and a voltage adjuster, coupled to the current generator and the oscillator, for adjusting the control voltage according to the clock signal and the second current; wherein, when the signal frequency of the clock signal changed, the voltage adjuster correspondingly adjusts the control voltage so as to adjust the first current.

Abstract: Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, a control voltage generator adapted to provide a temperature-dependent control voltage; and a plurality of variable reactance modules. The reference resonator generates a first reference signal having a resonant frequency, and each reactance module is adapted to modify a corresponding reactance in response to the control voltage to maintain the resonant frequency substantially constant or within a predetermined variance over a predetermined temperature range. A frequency controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator.

Abstract: There is provided an atomic force microscope (AFM) with increase the speed and sensitivity of detection of the resonant frequency shift in a cantilever. An AFM (1) extracts a reference signal and a phase shift signal from a detection signal from a displacement sensor of the cantilever. The reference signal is restrained from a phase change in accordance with the resonant frequency shift. The phase shift signal has a phase shifted in accordance with the resonant frequency shift. The AFM (1) determines the phase difference of the phase shift signal from the reference signal, as the resonant frequency shift. The AFM (1) may detect the phase difference between a plus-minus inversion point on the reference signal and a corresponding plus-minus inversion point on the phase shift signal. The AFM (1) may adjust phase before phase detection. The phase adjustment may move the detection point for the resonant frequency shift defined on the oscillation waveforms to the plus-minus inversion point.

Abstract: Disclosed is an oscillator circuit, comprising a crystal oscillator, an amplifier having an input and an output coupled across the crystal oscillator, a comparator having a reference input and an input coupled to the crystal oscillator and a pole network coupled between the comparator and the amplifier.

Abstract: Disclosed is an oscillator including a reference voltage generator generating a reference voltage, and a logic combination circuit generating complementary first and second internal clock signals in response to the reference voltage and complementary first and second output voltages. One of the first and second output voltages—the one going high—is provided to the logic combination circuit before the other one of the first and second output voltages—the one going low.

Abstract: A gain circuit of an oscillator circuit includes an inverter portion having an input IN and an output OUT arranged for connection to an external feedback circuit comprising a pi network. A feedback member having a first resistive element is coupled between the input IN and output OUT. An offset sense and correction block (OSCB) is configured to detect a dc offset potential difference between said input IN and output OUT and to reduce the offset potential by supplying a current to said input IN.

Abstract: This oscillation circuit includes a triangular wave generation circuit that generates a triangular wave signal corresponding to an outputted clock signal, a comparison circuit that generates a clock signal corresponding to a comparison of the triangular wave signal with a first reference voltage and a second reference voltage, a current adjusting circuit that adjusts the value of adjusted current according to the power supply voltage for the comparison circuit, and a reference voltage generation circuit that generates the first reference voltage and the second reference voltage having a voltage differential that corresponds to the value of the adjusted current. The current adjusting circuit increases the adjusted current when the power supply voltage for the comparison circuit rises, and reduces the adjusted current when the power supply voltage drops.

Abstract: Systems and methods are provided. In this regard, a representative system incorporates a crystal oscillator circuit and a digital automatic level control circuit. The digital automatic level control circuit is operative to: convert an oscillation amplitude of the crystal oscillator circuit to a proportional DC voltage; convert the DC voltage to a corresponding digital code representation; and adjust bias current and oscillator loop gain such that a desired oscillation amplitude is set.

Abstract: A low spur phase-locked loop (PLL) architecture is provided. A frequency-synthesizing PLL that includes a differential Kvco gain linearization circuit with adjustable DC offset is used to reduce clock jitter. The free-running oscillation frequency of the VCO of the PLL is centered near the desired frequency using programmable loads to minimize the required control voltage range. The PLL uses a differential architecture that includes a charge pump that compensates for variations in Kvco and a LC tank oscillator with differential controlled varactor. The differential PLL architecture demonstrates that the reference spur can be well controlled to below ?80 dBc.

Abstract: Provided is a low voltage frequency synthesizer using a boosting method for a power supply voltage of a charge pump. The low voltage frequency synthesizer includes a phase/frequency detector (PFD) that receives and compares a reference frequency and a feedback frequency to output a comparison signal, a charge pump that receives the comparison signal to output a current corresponding to the comparison signal, a low-pass filter (LPF) that generates a voltage corresponding to the output current of the charge pump, a voltage controlled oscillator (VCO) that receives the voltage of the LPF, amplifies the voltage to generate a boosting voltage, and outputs a frequency corresponding to the received voltage, and a DC converter that receives the boosting voltage of the VCO, converts the boosting voltage into a DC voltage, and applies the DC voltage as a power supply voltage of the charge pump.

Abstract: Described is a circuit comprising an oscillator, an amplifier unit and a control unit. The amplifier unit is coupled to the oscillator and to the control unit; and the control unit is arranged to regulate a load capacitance to the oscillator at startup.

Abstract: Systems and methods for distributing a clock signal are disclosed. In some embodiments, systems for distributing a clock signal include a plurality of resonant oscillators, each comprising an inductor; and a differential clock grid that distributes the clock signal. The differential clock grid is coupled to the plurality of resonant oscillators and the clock signal, and the inductances of the inductors are configured such that a resonant frequency of the plurality of resonant oscillators is substantially equal to the frequency of the clock signal.

Abstract: A gain control system comprises a reference stage, a bias replication stage, an operational amplifier, an automatic gain control block, a gain stage, and a crystal oscillator in one embodiment. A negative feedback loop is formed by portions of the operational amplifier, the replica biasing stage, the gain stage, and the automatic gain control stage. The negative feedback loop operatively controls an amplitude of oscillation in the crystal oscillator. The automatic gain control block produces output currents at reference levels in proportion to an input current source. The output current reference levels provide a corresponding yet independent scaling of currents in the bias replication stage and the gain stage. By the scaling capabilities provided a high common mode of voltage is provided between the crystal oscillator and the voltage reference section while stable oscillating characteristics are provided over a broad frequency range.

Abstract: A circuit for a voltage controlled oscillator (VCO) buffer is described. The circuit includes a first capacitor connected to an input of the VCO buffer that is connected to a VCO core. The circuit also includes a second capacitor connected to the input of the VCO buffer and the gate of a p-type metal-oxide-semiconductor field effect (PMOS) transistor. The circuit further includes a first switch connected to the first capacitor and the gate of the PMOS transistor. The circuit also includes a third capacitor connected to the input of the VCO buffer. The circuit further includes a fourth capacitor connected to the input of the VCO buffer and the gate of an n-type metal-oxide-semiconductor field effect (NMOS) transistor. The circuit also includes a second switch connected to the third capacitor and the gate of the NMOS transistor.

Abstract: An oscillator, a driving circuit and an oscillation method are provided. The driving circuit and a crystal are coupled in parallel to generate a clock signal. The driving circuit includes a buffer unit and a control unit. The buffer unit is coupled in parallel to the crystal, and used to amplify an oscillation signal outputted from the crystal to generate the clock signal. The control unit is coupled to the buffer unit, and used to generate a control signal to the buffer unit. The control unit determines a voltage level of the control signal by detecting whether the clock signal or the oscillation signal satisfies an oscillation condition of the crystal, so as to control a gain value of the buffer unit. Therefore, noise of different frequency bands loaded into the clock signal can be avoided.

Abstract: An oscillator circuit and system are provided having a peak detector that can determine a peak voltage value from the oscillator. The peak voltage value can then be compared against a predetermined voltage value by a controller coupled to the peak detector. The comparison value is then used to change a bias signal if the peak voltage value is dissimilar from the predetermined voltage value. A variable capacitor or varactor can be formed from a transistor and is coupled to the oscillator for receiving the bias signal upon a varactor bias node. The bias signal is used to regulate the capacitance within the varactor as applied to the oscillator nodes. Another controller can also be coupled to the peak detector to produce a second bias signal if the peak voltage is dissimilar from a second predetermined voltage value. The second bias signal can then be forwarded into an amplifier having a variable gain to regulate the gain applied to the oscillator.

Abstract: Systems and methods for insuring successful initiation of a resonating micro-electro mechanical systems (MEMS). An example system includes a resonating sensor, a drive device, a charge amplifier, and a voltage gain circuit. At start up, the charge amplifier and voltage gain circuit receives signals from the resonating sensor, compensates this signal for DC offsets, and generates a clock signal for the drive, thus placing the resonating sensor in a steady state operating mode. The circuit includes a plurality of gain switches that are toggled to produce a glitch in the signal associated with the received signal. The glitch overcomes the DC offset. A comparator generates the clock signal for the drive device if a signal associated with the received signal exceeds a reference signal.

Abstract: An oscillator device having an oscillation system including an oscillator and a resilient supporting member, a driving member configured to supply a driving force to the oscillation system based on a driving signal, a detecting member configured to detect at least an oscillation amplitude of the oscillator, a driving amplitude control unit configured to control at least a driving amplitude of the driving signal, and a driving frequency control unit configured to control a driving frequency of the driving signal to be supplied to the driving member, wherein, in a state in which the driving amplitude control unit controls the driving amplitude of a driving signal so that the oscillation amplitude to be detected becomes equal to a target value, and on the basis of information including driving frequencies in different driving states being driven with driving signals of these driving frequencies as well as the controlled driving amplitude, the driving frequency control unit acquires, as a resonance frequency of t