With Particular Source Of Power Or Bias Voltage Patents (Class 331/185)
  • Patent number: 11196429
    Abstract: Locking time for a phase-locked loop is decreased by selectively controlling a division value of the feedback divider during the first division cycle to reduce the initial phase error. The division value of the feedback divider during the first division cycle is selectively set such that the locking phase relationship between the two phase detector input signals is achieved at the end of the first division cycle.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: December 7, 2021
    Assignee: NXP USA, Inc.
    Inventors: Stefano Dal Toso, Mathieu Perin
  • Patent number: 10938380
    Abstract: A bias current circuit is disclosed. The bias current circuit includes a number of current sources that can selectively be coupled to a bias current node or an auxiliary node. The bias current may be provided through the bias current node. During a trimming operation, a control circuit may selectively couple particular ones of the current sources to the bias current node, in accordance with a desired bias current. Other ones of the current sources may be coupled to the auxiliary node, through which an auxiliary current is provided. Upon completing the trimming operation, the control circuit may cause the auxiliary current to be reduced to zero.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: March 2, 2021
    Assignee: Apple Inc.
    Inventors: Mohammadhasan Fayazi, Pablo Moreno Galbis, Stanley Bo-Ting Wang
  • Patent number: 10771014
    Abstract: An oscillator bias stabilization circuit and method for biasing the circuit is disclosed. The bias stabilization circuit includes a plurality of resistive dividers responsive to a control signal in the circuit. The plurality of resistive dividers are selectably connectable in the circuit to provide an adaptable equivalent resistance in response to a control signal while keeping a bias voltage produced by the circuit substantially constant as the loop gain of an oscillator is varied. The plurality of resistive dividers are coupled to a node in the oscillator that establishes the bias voltage.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: September 8, 2020
    Assignee: Arm Limited
    Inventor: Alexandru Aurelian Ciubotaru
  • Patent number: 10694124
    Abstract: The present technique relates to an image pickup element and an electronic apparatus which enable a higher-quality image to be obtained. An image pickup element includes an input sense portion configured to produce a noise correction signal portion includes a first transistor and a second transistor configuring a current mirror circuit, a switch provided between a gate of the first transistor and a gate of the second transistor, and a capacitive element one electrode of which is connected between the switch and the gate of the second transistor on an output side of the current mirror circuit, and the other electrode of which is connected to the predetermined power source.
    Type: Grant
    Filed: March 3, 2017
    Date of Patent: June 23, 2020
    Assignee: Sony Corporation
    Inventors: Tatsuki Nishino, Yosuke Ueno, Yusuke Moriyama, Shizunori Matsumoto
  • Patent number: 10145868
    Abstract: A self-referenced on-die voltage droop detector generates a reference voltage from the supply voltage of an integrated circuit's power distribution network, and compares this reference voltage to the transient supply voltage in order to detect voltage droops. The detector responds to detected occurrences of voltage droop with low latency by virtue of being located on-die. Also, by generating the reference voltage from the integrated circuit's power domain rather than using a separate reference voltage source, the detector does not introduce noise and distortion associated with a separate power domain.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: December 4, 2018
    Assignee: AMPERE COMPUTING LLC
    Inventors: Yan Chong, Luca Ravezzi, Alfred Yeung, Hamid Partovi
  • Patent number: 9985615
    Abstract: An on-chip true noise generator including an embedded noise source with a low-voltage, high-noise zener diode(s), and an in-situ close-loop zener diode power control circuit. The present invention proposes the use of heavily doped polysilicon and silicon p-n diode(s) structures to minimize the breakdown voltage, increasing noise level and improving reliability. The present invention also proposes an in-situ close-loop zener diode control circuit to safe-guard the zener diode from catastrophic burn-out.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: May 29, 2018
    Assignee: International Business Machines Corporation
    Inventors: Kai D. Feng, Ping-Chuan Wang, Zhijian Yang, Emmanuel Yashchin
  • Patent number: 9953687
    Abstract: An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.
    Type: Grant
    Filed: October 21, 2016
    Date of Patent: April 24, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John J. Wuu, Ryan Freese, Russell J. Schreiber
  • Patent number: 9876979
    Abstract: An example current generator may include a low dropout regulator (LDO) coupled to receive a reference voltage and provide a reference current in response, where the LDO adjusts a current level of the current reference in response to a calibration signal. A current controlled oscillator coupled to receive a reference current copy from the LDO and generate an oscillating signal in response, where a period of the oscillating signal is based at least in part on a level of the reference current copy. A pulse generator coupled to provide an adjustable pulse signal. A counter coupled to determine a number of periods of the oscillating signal occurring during a duration of the pulse signal, and provide a control signal indicative of such, and a digital calibration circuit coupled to receive the control signal and provide the calibration signal to the LDO in response.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: January 23, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chun-Hsiang Chang, Yu-Shen Yang, Yingkan Lin, Liping Deng
  • Patent number: 9401699
    Abstract: A phase locked loop includes a voltage-controlled oscillator and a current mirror circuit that supplies a drive current to the voltage-controlled oscillator. The current mirror circuit includes a filter between a bias current generator and current mirror transistor. The filter includes a first and a second switch driven in unison with a small duty cycle.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: July 26, 2016
    Assignee: STMicroelectronics International N.V.
    Inventor: Amit Katyal
  • Patent number: 9337157
    Abstract: A miniature passive structure for electrostatic discharge (ESD) protection and input/output (I/O) matching for a high frequency integrated circuit is provided. The miniature passive structure includes at least one shunt stub and at least one load line. The shunt stub(s) each provide a corresponding ESD discharge path. The load line(s) are coupled to the shunt stub(s) and provide loading effects for the shunt stub(s).
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: May 10, 2016
    Assignee: Nanyang Technological University
    Inventors: Kai Xue Ma, Yang Lu, Jiangmin Gu, Kiat Seng Yeo
  • Patent number: 9306495
    Abstract: A device includes a first pin configured to connect to a first terminal of a resonator, a second pin configured to connect to a second terminal of a resonator, a gain stage having a first terminal electrically connected to the first pin, and a voltage drop circuit. The voltage drop circuit includes a first transistor having an input terminal electrically connected to a second terminal of the gain stage, and a second transistor having an input terminal electrically connected to an output terminal of the first transistor, and an output terminal electrically connected to the second pin.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Guan-Yu Chen, Wen-Yang Hsu
  • Patent number: 9024697
    Abstract: The invention relates to a method for operating control equipment (1) of a resonance circuit (2), wherein the control equipment (1) comprises at least two circuit elements (8, 9) connected in series, in particular each comprising a recovery diode (13, 14) connected in parallel, between which a connection (6) of the resonance circuit (2) is connected. According to the invention, the circuit elements (8, 9) are actuated as a function of the voltage detected at the connection (6). The invention further relates to control equipment (1) of a resonance circuit (2).
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: May 5, 2015
    Assignee: Robert Bosch GmbH
    Inventor: Jochen Kuehner
  • Patent number: 9007140
    Abstract: The present invention provides a digitally controlled, current starved, pulse width modulator (PWM). In the PWM of the present invention, the amount of current from the voltage source to the ring oscillator is controlled by the proposed header circuit. By changing the header current, the pulse width of the switching signal generated at the output of the ring oscillator is dynamically controlled, where the duty cycle can vary between 50% and 90%. A duty cycle to voltage converter is used to ensure the accuracy of the system under process, voltage, and temperature (PVT) variations. The proposed pulse width modulator is appropriate for dynamic voltage scaling systems due to the small on-chip area and high accuracy under process, voltage, and temperature variations.
    Type: Grant
    Filed: January 8, 2014
    Date of Patent: April 14, 2015
    Assignees: University of South Florida, University of Rochester
    Inventors: Selcuk Kose, Eby G. Friedman
  • Patent number: 8994460
    Abstract: A method and a phase locked loop (PLL) circuit for implementing compact current mode logic inductor capacitor voltage controlled oscillator for high speed communications, and a design structure on which the subject circuit resides are provided. The PLL circuit includes a current mode logic (CML) inductor capacitor (LC) Voltage Controlled Oscillator (VCO). The PLL circuit includes a reference circuit generates a virtual ground node for biasing noise sensitive components, providing level shifted VCO increment and decrement tuning values from a phase detector coupled by a respective resistor to tune a varactor of the LC VCO, and providing a loop filter function. The virtual ground node tracks a logic power supply noise, incurring no jitter penalty, and eliminating the need for a separate power supply for the PLL circuit.
    Type: Grant
    Filed: November 13, 2012
    Date of Patent: March 31, 2015
    Assignee: International Business Machines Corporation
    Inventors: Grant P. Kesselring, James D. Strom, Kenneth A. Van Goor, Kennedy K. Cheruiyot
  • Patent number: 8988159
    Abstract: There is provided an oscillator capable of lowering the power supply voltage without degrading the phase noise, while employing the conventional circuit configuration. According to one aspect of the present invention, there is provided an oscillator comprising: an oscillation circuit; a bias generation circuit for generating a bias signal to drive the oscillation circuit; and a booster circuit for boosting a power supply voltage to generate a boosted voltage for driving the bias generation circuit. In addition, the oscillation circuit, the bias generation circuit, and the booster circuit are provided in a single IC chip, and the booster circuit may receive the power supply voltage VDD from the power supply arranged at the exterior of the IC chip.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: March 24, 2015
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Haruhiko Maru
  • Patent number: 8988153
    Abstract: A low voltage ring oscillator circuit can have a frequency variation that depends on process variations of insulated gate field effect transistors (IGFETs) of a first conductivity type without substantially being affected by process variations to IGFETs of a second conductivity type. A ring oscillator stage may include an inverter including only IGFETs of the first conductivity type. The inverter may be coupled to a boot circuit that boosts the gate potential of a first IGFET of the first conductivity type with a timing such that IGFETs of the second conductivity type in the boot circuit do not affect the frequency variations of the ring oscillator circuit.
    Type: Grant
    Filed: March 9, 2013
    Date of Patent: March 24, 2015
    Assignee: SuVolta, Inc.
    Inventor: Richard S. Roy
  • Patent number: 8975977
    Abstract: LC tank and ring-based VCOs are disclosed that each include a differential pair of transistors for steering a tail current generated by a current source responsive to a bias voltage. A biasing circuit generates the bias voltage such that a transconductance for the transistors in the differential pairs is inversely proportional to a resistance.
    Type: Grant
    Filed: May 8, 2012
    Date of Patent: March 10, 2015
    Inventor: Mohammad Ardehali
  • Patent number: 8975974
    Abstract: A wide frequency, low voltage oscillator includes multiple delay elements, in which each delay element includes two inverters coupled through a latching element into a differential-type configuration. Two current-source PMOS devices bias the latching element in a high-gain region at low-voltage. By coupling these current-source PMOS devices into the delay elements, the start-up voltage of the latching element is reduced. Each delay element is also biased using a replica bias circuit that scales the supply/control voltage of the oscillator and provides the scaled supply/control voltage to control the lower rail of oscillation amplitude. By coupling the replica bias circuit to the lower rail, the lower rail of the oscillation amplitude follows the changes to the supply/control voltage.
    Type: Grant
    Filed: March 1, 2012
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventor: Sameer Wadhwa
  • Patent number: 8975976
    Abstract: A power management apparatus and method for maintaining a substantially constant duty cycle of a reference clock signal in a multi-power oscillator, includes a first output power transistor in electrical parallel with a series arrangement of a second output power transistor and a switch, and a crystal oscillator capacitively coupled to a common gate of the first and second output power transistors, wherein a level of the reference clock signal power output is a normal power level when the switch is open and the level of the reference clock signal power output is a higher power level when the switch is closed to operate the second output power transistor in parallel with the first output power transistor.
    Type: Grant
    Filed: March 6, 2013
    Date of Patent: March 10, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Jingyu Hu, Michael Naone Farias
  • Patent number: 8970311
    Abstract: In one embodiment, a voltage-controlled oscillator (VCO) is provided having an output signal having a frequency responsive to a tuning signal. The VCO includes: a plurality of inverters coupled to form a loop, each differential inverter having a differential pair of transistors configured to steer a tail current from a current source, the current source sourcing the tail current responsive to a bias voltage, each inverter stage including a plurality of switched-capacitor circuits configured to control a signal delay through the inverter stage response to the tuning signal so as to control the frequency of the output signal; and a bias circuit configured to generate the bias voltage responsive to a reference signal such that an amplitude of the output signal is substantially independent of the output signal frequency and depends upon the reference signal.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 3, 2015
    Inventor: Mohammad Ardehali
  • Patent number: 8963650
    Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
  • Patent number: 8912854
    Abstract: Embodiments of the present invention provide a design structure and method for compensating for a change in frequency of oscillation (FOO) of an LC-tank VCO that includes a first node; second node; inductor; first capacitive network (FCN) that allows the design structure to obtain a target FOO; compensating capacitive (CCN) network that compensates for a change in the design structure's FOO; second capacitive network (SCN) that allows the design structure to obtain a desired FOO; a filter that supplies a voltage to the SCN and is coupled to the SCN; a transconductor that compensates for a change in the design structure's FOO; and a sub-circuit coupled to the SCN that generates and supplies voltage to the CCN sufficient to allow the CCN to compensate for a reduction in the design structure's FOO. The first and second nodes are coupled to the inductor, FCN, CCN, SCN, and sub-circuit.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: December 16, 2014
    Assignee: International Business Machines Corporation
    Inventors: Herschel A. Ainspan, Ram Kelkar, Anjali R. Malladi, Ramana M. Malladi
  • Patent number: 8912853
    Abstract: A dynamic level shifter circuit and a ring oscillator implemented using the same are disclosed. A dynamic level shifter may include a pull-down circuit and a pull-up circuit. The pull-up circuit may include an extra transistor configured to reduce the current through that circuit when the pull-down circuit is activated. A ring oscillator may be implemented using instances of the dynamic level shifter along with instances of a static level shifter. The ring oscillator may also include a pulse generator configured to initiate oscillation. The ring oscillator implemented with dynamic level shifters may be used in conjunction with another ring oscillator implemented using only static level shifters to compare relative performance levels of the static and dynamic level shifters.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventors: James E. Burnette, Greg M. Hess, Shinye Shiu
  • Patent number: 8896387
    Abstract: In one embodiment, a voltage controlled oscillator (VCO) is provided. The VCO includes a tank circuit. Also, the VCO includes a first pair of transistors. The drains of the first pair of transistors are coupled to the tank circuit and the gates of the first pair of transistors are cross-coupled with the drains of the first pair of transistors. The first pair of transistors each have a first threshold voltage. The VCO further includes a second pair of transistors. The drains of the second pair of transistors are respectively coupled to the sources of the first pair of transistors and the gates of the second pair of transistors are respectively coupled to the gates of the first pair of transistors, The second pair of transistors each have a second threshold voltage higher than the first threshold voltage.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: November 25, 2014
    Assignee: Marvell International Ltd.
    Inventors: Alessandro Venca, Enrico Sacchi, Sehat Sutardja
  • Patent number: 8896390
    Abstract: A circuit of inductance/capacitance (LC) voltage control oscillator (VCO) includes an LC VCO unit, a peak detector and a processing unit. The LC VCO unit receives a current control signal and outputs an oscillating voltage signal. The peak detector receives the oscillating voltage signal to obtain an averaged voltage value. The processing unit receives the averaged voltage value to accordingly output the current control signal and feedback to the LC VCO unit. The processing unit also detects whether or not the averaged voltage value has reached to a saturation state and a corresponding critical current. After the current control signal reaches to the critical current, the current control signal is set within a variance range near the critical current.
    Type: Grant
    Filed: June 13, 2012
    Date of Patent: November 25, 2014
    Assignee: Novatek Microelectronics Corp.
    Inventor: Chih-Hung Chen
  • Patent number: 8890627
    Abstract: A voltage controlled oscillator generating an oscillation signal according to a first control signal without a silent region. The voltage controlled oscillator includes a control signal adjuster and a plurality of delay cells. The control signal adjuster receives the first control signal and generates a second and a third control signal according to the first control signal. The voltage level of the third control signal is higher than that of the second control signal and the voltage level of the second control signal is higher than that of the first control signal. The plurality of delay cells are ring-connected and controlled by the first, the second, and the third control signals to generate the oscillation signal. Each delay cell includes three sets of current generation transistors. The three sets of current generation transistors are separately controlled by the three different control signals.
    Type: Grant
    Filed: July 16, 2013
    Date of Patent: November 18, 2014
    Assignee: Via Technologies, Inc.
    Inventor: Yeong-Sheng Lee
  • Patent number: 8878614
    Abstract: A PLL circuit includes an oscillator, a detection block, an integral path and a proportional path. The oscillator generates an oscillation signal. The detection block detects a phase difference between the oscillation signal and a reference signal and generates an integral signal that represents an integral value of the phase difference and a proportional signal that represents a current value of the phase difference. The integral path includes a regulator that receives the integral signal and supplies a regulated integral signal to the oscillator, and the regulator has a feedback loop including an error amplifier. The proportional path supplies the proportional signal, separately from the integral signal, to the oscillator. The oscillator generates the oscillation signal having an oscillation frequency controlled by both of the regulated integral signal and the proportional signal such that the phase of the oscillation signal is locked to the phase of the reference signal.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: November 4, 2014
    Assignee: MegaChips Corporation
    Inventors: Wenjing Yin, Anand Gopalan
  • Patent number: 8866557
    Abstract: Resistor bias circuitry is included in components of an XTAL oscillator system to reduce 1/f noise. An XTAL oscillator includes a resistor bias circuit attached to the XTAL core. A common mode feedback OP amp connected to the XTAL core also includes a resistor bias circuit. An XTAL oscillator chain includes an XTAL core, common mode feedback OP amp, common mode logic buffer (CML BF), and differential to CMOS converter (D2C) each with resistor bias circuitry.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: October 21, 2014
    Assignee: Broadcom Corporation
    Inventors: Chang-Hyeon Lee, Lindel Kabalican
  • Patent number: 8836444
    Abstract: An illustrative system includes an amplifier operably connected to a phase shifter. The amplifier is configured to amplify a voltage from an oscillator. The phase shifter is operably connected to a driving amplitude control, wherein the phase shifter is configured to phase shift the amplified voltage and is configured to set an amplitude of the phase shifted voltage. The oscillator is operably connected to the driving amplitude control. The phase shifted voltage drives the oscillator. The oscillator is at an internal resonance condition, based at least on the amplitude of the phase shifted voltage, that stabilizes frequency oscillations in the oscillator.
    Type: Grant
    Filed: March 23, 2012
    Date of Patent: September 16, 2014
    Assignee: Uchicago Argonne, LLC
    Inventors: Omar Daniel Lopez, Dario Antonio
  • Patent number: 8816785
    Abstract: An oscillator which oscillates electromagnetic waves includes a negative differential resistance element, a resonator configured to prescribe oscillation frequencies of the electromagnetic waves, a voltage modulation unit configured to modulate the negative differential resistance element, a stabilizing circuit configured to suppress parasitic oscillation, and a bias circuit, including a power supply and a line, used to control an operating point voltage of the negative differential resistance element. The voltage modulation unit is connected to the bias circuit through the stabilizing circuit.
    Type: Grant
    Filed: September 14, 2011
    Date of Patent: August 26, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Ryota Sekiguchi
  • Patent number: 8816790
    Abstract: Oscillators are described that have a highly stable output frequency versus the variation of supply voltage and different operating conditions such as temperature. The concepts are broadly applicable to various types of oscillators. The highly stable output is achieved with the use of self biasing loops. The circuits associated with providing constant harmonic output current can be used with the concept of a phi-null oscillator to further stabilize the output frequency.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: August 26, 2014
    Inventor: Nabil Mohamed Sinoussi
  • Patent number: 8810324
    Abstract: The present invention relates to an oscillating device, which comprises a driving module and an oscillating module. The driving module is used for producing a first driving voltage and a second driving voltage. The oscillating module comprises a first symmetric load circuit, a second symmetric load circuit, and a bias circuit. The first symmetric load circuit and the second symmetric load circuit produce a bias according to the first driving voltage. The bias circuit produces a bias current according to the second driving voltage. The oscillating module produces an oscillating signal according to the first driving voltage and the bias current, where the bias current is proportional to the bias. Thereby, by making the driving signal produced by driving module proportional to the bias of the oscillating module, simple compensation for temperature and process can be performed. Thereby, the frequency can be tuned using a few calibration bits.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: August 19, 2014
    Assignee: Sitronix Technology Corp.
    Inventors: Chih-Te Hung, Cheng-Chung Yeh
  • Patent number: 8803617
    Abstract: Oscillator circuitry having a switching inverting amplifier arranged in a ring oscillator configuration of at least two stages. A bias generator for supplying the amplifiers of neighboring stages, is responsive to an enable signal to supply the amplifiers only when the enable signal is asserted. A first pair of transistors, coupled to an input of one of the amplifiers and the other coupled to an output of the amplifier, the transistors being driven in common by the enable signal such that when the enable signal is deasserted the transistors of the pair are turned on to impose conflicting levels at the input and the output such that the amplifier is forced to switch.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: August 12, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Jin Liang, David Grant, Larry Wofford
  • Patent number: 8797106
    Abstract: Circuits, apparatuses, and methods are disclosed for oscillators. In one such example oscillator circuit, a plurality of delay stages are coupled in series. A variable delay circuit stage is coupled to the plurality of delay stages and is configured to delay a signal through the variable delay circuit stage by a variable delay. The variable delay increases responsive to a rising magnitude of a supply voltage provided to the variable delay circuit stage.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: August 5, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Ming H. Li, Dong Pan
  • Patent number: 8773209
    Abstract: A voltage controlled oscillator module including a VCO unit and a gain adjustment unit is provided. The VCO unit is configured to generate a frequency signal based on a control voltage. The gain adjustment unit is coupled to the VCO unit and configured to receive a first adjustment voltage, a second adjustment voltage, and a reference voltage and accordingly adjusts the control voltage to adjust a frequency value of the frequency signal. The gain adjustment unit includes an adjustment circuit unit and a reference circuit unit. A first voltage-frequency curve of the frequency value of the frequency signal and a voltage value of the first adjustment voltage changes in response to a structure characteristic of the adjustment circuit unit. Furthermore, a frequency generating system and a method for adjusting a signal frequency of the VCO module are provided.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: July 8, 2014
    Assignee: Phison Electronics Corp.
    Inventor: Wei-Yung Chen
  • Patent number: 8766735
    Abstract: An enhanced negative resistance voltage controlled oscillator (VCO) is provided, in which the body of each transistor within a pair of cross-coupled transistors is coupled to the gate of the same transistor through a resistor. The body transconductance is employed to enhance the negative resistance of the cross-coupled pair of transistors. At the same time, a forward body bias voltage reduces the threshold voltage of the cross-coupled pair to allow the VCO to operate at a low power supply voltage. Further, the resistor connected between the body and the drain of each transistor voids the leakage in the substrate, and thus, reduces power consumption of the VCO further. This VCO provides low power operation with enhanced figure of merit without employing any extra inductors besides the inductors that are part of the LC tank.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Pinping Sun, Chengwen Pei
  • Patent number: 8742858
    Abstract: Techniques and architectures corresponding to relaxation oscillators having output frequencies that are supply voltage independent are described. In a particular embodiment, an apparatus includes a relaxation oscillator having one or more capacitors and a compensation current circuit coupled to the relaxation oscillator. The compensation current circuit is configured to regulate current provided to the one or more capacitors of the relaxation oscillator in response to changes in a supply voltage provided to the compensation current circuit and to the relaxation oscillator.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies AG
    Inventors: Roberto Nonis, Nicola DaDalt
  • Patent number: 8742856
    Abstract: The present disclosure is directed to a method and apparatus for providing an output oscillating signal at a desired frequency. In at least one example, the apparatus includes a weak inversion structure configured to set a small reference current. A current mirror configured to provide a replica current based on the small reference current and a tuning word. A ring oscillator is configured to be powered by a supply at a voltage determined based on the replica current. The tuning word is adjustable to change the voltage such that the ring oscillator provides the output oscillating signal at the desired frequency.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: June 3, 2014
    Assignee: Broadcom Corporation
    Inventors: Manolis Frantzeskakis, Georgios Srikas, Henrik Jensen, Yushi Tian, Jianfeng Shi
  • Patent number: 8736387
    Abstract: A reference circuit, an oscillator architecture that includes the reference circuit and a method for operating the reference circuit are described. In one embodiment, the reference circuit includes a voltage reference generator configured to generate a reference voltage and a current reference generator configured to generate a reference current based on the reference voltage. The current reference generator includes a level shifter circuit configured to generate intermediate voltages based on the reference voltage, a first current reference circuit configured to generate intermediate currents based on the intermediate voltages, where the intermediate currents are correlated to the reference voltage, and a second current reference circuit configured to combine the intermediate currents to generate the reference current. Other embodiments are also described.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: May 27, 2014
    Assignee: NXP B.V.
    Inventors: Kevin Mahooti, Min Ming Tarng, Jason Sharma, Hassan Sharghi, Himanshu Sharma, Amjad Nezami
  • Patent number: 8723610
    Abstract: A bias loop is used to program LC tank common mode voltage to allow operation at two different supply voltages VDD (e.g., 2.5V and 1.2V), and two different tank swings. This also allows lower phase noise through optimizing Ids shape allowing class C operation for both voltages. The two different supply voltages allow operation using multiple communication protocols such as 802.11n and 802.11ac within a common VCO circuit. The VCO can form part of a transceiver to provide frequencies in multiple bands.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 13, 2014
    Assignee: Broadcom Corporation
    Inventor: Zhiheng Cao
  • Patent number: 8710930
    Abstract: A differential ring oscillator includes a plurality of delay stages connected in a ring. At least one of the delay stages includes: a current source, arranged to generate a bias current according to a coarse tuning signal; a latching circuit arranged to generate a differential output signal to a next delay stage according to a differential input signal from a previous delay stage; a capacitive array arranged to provide a first capacitance according to a fine tuning signal; and a varactor device arranged to provide a second capacitance according to a controllable signal for locking an oscillating frequency of the differential ring oscillator to a target frequency. The coarse tuning signal and fine tuning signal are arranged for adjusting the oscillating frequency of the differential ring oscillator to, respectively, reach a predetermined frequency range including the target frequency and to approach the target frequency in the predetermined frequency range.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: April 29, 2014
    Assignee: MediaTek Singapore Pte. Ltd.
    Inventors: Chun Geik Tan, Renliang Zheng, Tieng Ying Choke
  • Patent number: 8710929
    Abstract: A system and method are provided for combined generation of I and Q signal references according to a periodic input signal and selective phase interpolation of an output signal with reference thereto. A ring oscillator portion generates an oscillator signal, and includes a plurality of delay stages interconnected in cascade to collectively execute an odd number of signal state inversions within a closed loop. The delay stages establish at respective nodes defined therebetween correspondingly delayed oscillator signal versions, successively shifted in phase by a predetermined phase difference. A signal injection portion selectively applies to at least one node of the ring oscillator portion a current bias according to the periodic input signal, and selectively adjusts each current bias in amplitude. The oscillator signal is thereby frequency locked to the periodic input signal, defining I/Q references with respect to the delayed oscillator signal version established at the current biased node.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: April 29, 2014
    Assignee: Cadence Design Systems, Inc.
    Inventors: Eric Naviasky, Chris Moscone, Rajagopal Vijayaraghavan, Benjamin Louis Heilmann
  • Patent number: 8710937
    Abstract: An apparatus includes a tank circuit of a voltage controlled oscillator. A pair of alternating current coupling capacitors respectively couple the gates of the pair of transistors to the drains of the pair of transistors. A bias circuit is coupled to the gates of the pair of transistors and biases the transistors in accordance with a bias voltage such that the transistors alternatingly turn on during a plurality of peaks of an oscillating signal of the tank circuit and the transistors turn off during a plurality of crossing points of the oscillating signal. A feedback loop may be configured to detect a peak oscillating amplitude of the oscillating signal and adjust a bias voltage of the bias circuit based on the peak oscillating amplitude. Also, a supply capacitor may be coupled to the tank circuit and to the transistors to provide an instantaneous current to the VCO.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: April 29, 2014
    Assignee: Marvell International Ltd.
    Inventor: Sehat Sutardja
  • Patent number: 8710933
    Abstract: A disclosed oscillation circuit includes a constant-voltage generation circuit, an oscillation generation circuit configured to generate an oscillation output, an output circuit including a plurality of parallelly arranged MOSFET circuits, to which a constant voltage generated by the constant-voltage generation circuit is supplied as a supply voltage, output points of the plurality of MOSFET circuits being mutually connected, and a drive circuit configured to drive a selected MOSFET circuit selected in response to a selection input among the plurality of MOSFET circuits by the oscillation output, wherein an output from an unselected MOSFET circuit among the plurality of MOSFET circuits other than the selected MOSFET circuits has a high impedance.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: April 29, 2014
    Assignee: Mitsumi Electric Co., Ltd.
    Inventors: Takayuki Nakamura, Minoru Sakai
  • Patent number: 8710936
    Abstract: A system which starts up and shuts down a resonant oscillator circuit. During start up, the system operates a driving circuit, which is external to the resonant oscillator circuit, wherein the driving circuit uses a first clock signal to control a first phase output of the resonant oscillator circuit. At the same time, the driving circuit uses a second clock signal to control a second phase output of the resonant oscillator circuit, wherein the first and second clock signals have opposite phases. While the first and second phase outputs are being controlled, the system ramps up an input voltage, which is used to power the resonant oscillator circuit, wherein the ramping takes place across multiple initial oscillation periods. During shut down, the system shuts down the resonant oscillator circuit by ramping down the input voltage. Next, the system clamps the first and second phase outputs to a fixed voltage.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: April 29, 2014
    Assignee: Apple Inc.
    Inventors: Catherine S. Chou, William C. Athas, Heather R. Sullens
  • Patent number: 8692622
    Abstract: High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: April 8, 2014
    Assignee: The Regents of the University of California
    Inventors: Michael M. Green, Xiaoyan Gui
  • Patent number: 8692627
    Abstract: An oscillating signal generating device includes: an oscillating circuit arranged to generate an oscillating signal according to a current controlled signal; and a control signal generating circuit coupled to the oscillating circuit, the control signal generating circuit for receiving a first reference voltage and a second reference voltage, the control signal generating circuit operated between the first reference voltage and the second reference voltage, and the control signal generating circuit arranged to generate the current controlled signal according to a voltage input signal; wherein the control signal generating circuit is capable of monotonically generating the current controlled signal according to the voltage input signal when a voltage level of the voltage input signal falls between the first reference voltage and the second reference voltage.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: April 8, 2014
    Assignee: Silicon Motion Inc.
    Inventor: Chih-Hua Chuang
  • Patent number: 8686798
    Abstract: An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated.
    Type: Grant
    Filed: May 3, 2012
    Date of Patent: April 1, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jun Zhang, Xiuqiang Xu
  • Patent number: 8686799
    Abstract: An integrated circuit, a voltage controlled oscillator (VCO) and a phase-locked loop (PLL). In one embodiment, the VCO includes: (1) a voltage tune line configured to receive a tuning voltage for the VCO and (2) an odd number of ring-coupled delay elements. Each of the delay elements includes: (2A) an inverter having a power supply line being coupled to the voltage tune line and (2B) a feedback path having a gain-attenuating transistor with a gate thereof being coupled to the voltage tune line.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: April 1, 2014
    Assignee: Texas Instruments Incorporated
    Inventor: Stanley J. Goldman
  • Patent number: 8686802
    Abstract: A method of configuring a device comprising a MEMS resonator includes initiating operation of the device, estimating a first parameter of the MEMS resonator based on the initiated operation, the first parameter not varying with the bias voltage, monitoring the operation of the device at a plurality of levels of the bias voltage, calculating a second parameter of the MEMS resonator based on the monitored operation, the second parameter varying with the bias voltage, determining an operational level of the bias voltage based on the estimated first parameter and the calculated second parameter, and configuring the device in accordance with the determined operational level of the bias voltage.
    Type: Grant
    Filed: January 16, 2012
    Date of Patent: April 1, 2014
    Assignee: Micrel, Incorporated
    Inventors: Andrew Robert Brown, John Ryan Clark, Wan-Thai Hsu, Graham Yorke Mostyn, William Cochrane Ingle