Abstract: A quadrature detector quadrature-detects an FM signal. An FM detector generates a detection signal by FM detecting an FM signal that has been quadrature-detected. An AFC unit generates a control signal for controlling a frequency of a local oscillation signal used for quadrature detection on the basis of the generated detection signal, and feeds back the control signal to a local oscillator that should output the local oscillation signal. A difference calculator generates a difference signal representing a difference from a reference value on the basis of the generated detection signal. An addition unit adds the generated difference signal and the generated detection signal.

Abstract: In some embodiments, a feedback loop circuit includes a phase detector, first and second charge pumps that are each coupled to receive an output signal of the phase detector, a first low pass filter, a second low pass filter coupled to an output of the second charge pump, a clock signal generation circuit having first and second control inputs, a first switch circuit coupled between the first low pass filter and the second low pass filter, and a second switch circuit coupled to the first low pass filter and the first control input of the clock signal generation circuit.

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract: A dual mode tuner/receiver is disclosed in which both analog and digital signals can be received and processed. A low pass filter allows all channels below a selected frequency enter the circuit. A precisely controlled dual conversion circuit creates an intermediate frequency (IF) signal. An automatic carrier detection circuit monitors the IF signal and determines whether the signal is of analog or digital format and intermediate frequency filters are adjusted based upon the type of signal detected. A coherent oscillator circuit generates in-phase and quadrature reference signals that are used by video and audio detectors for further processing of the IF signal. In-phase and quadrature outputs are provided for digital signals and composite video and audio outputs are provided for analog signals.

Abstract: A method and apparatus for characterizing frequency response of a device under test (DUT) is disclosed. A repeated base bit pattern is received, the base bit pattern including a first transition from a 0-bit to a 1-bit. Then, using bit error rate distribution, multivalue voltage along the first transition is determined. Finally, the multivalued voltages are converted into frequency domain using fast Fourier transform. The apparatus includes a processor and storage with instructions for the processor to perform these operations. Using the present inventive technique, the frequency response of the DUT can be determined using an error performance analyzer such as a BERT.

Abstract: Various circuit techniques employ a transconductance (gm) cell in control loops to implement circuits such as phase locked loops and delay locked loops that are capable of operating at ultra high frequencies with improved precision and noise performance. The gm cell is designed to operate on an analog input signal with a very small swing and more gradual transition edges. These characteristics allow implementation of high frequency circuits and systems including, for example, transceivers for fiber optic channels, disk driver electronics and the like.

Abstract: A 1-port tunable frequency discriminator that is incorporated into a frequency lock loop (FLL) for providing an improved FLL having reduced phase noise and settling times is provided. The invented 1-port tunable delay line discriminator reduces the phase noise generated by VCO's to approximately 105 dBc/Hz at 10 kHz, to better than 120 dBc/Hz at 100 kHz. The invention additionally reduces post tuning drift to less than 10 kHz after one microsecond. A secondary feedback loop, such as a conventional phase lock loop, can be incorporated into the invented FLL for providing phase and frequency coherency. The invention is formed by coupling a voltage controlled oscillator source (VCO) to a microwave signal detector and to an open ended delay line. When a microwave signal generated by the VCO reaches an end of the open ended delay line, a majority of the signal is reflected back along the line.

Abstract: A switched capacitance phase locked loop (PLL) system includes a filter circuit having a scaling channel for scaling the phase error; an integrating channel for integrating the phase error; and a summing device for combining the scaled phase error and the integrated phase error; a voltage controlled oscillator (VCO) responsive to the summing device produces an output; the VCO's gain is proportional to its output clock frequency; the integrating channel includes a switched capacitance integrating circuit for controlling the gain of the integrating channel proportional to the output clock frequency of the VCO and maintaining constant the ratio of, and scaling the product of, the unity gain frequency and the zero frequency of the phase locked loop to keep constant the damping factor and to scale the natural frequency of the phase locked loop with the output clock frequency of the VCO, respectively.

Abstract: A digital programmable loop filter for high frequency control systems applications utilizing a serial processing technique on pulse densities. The loop filter contains a proportional signal path and an integral signal path. A 4-time-slot sequencer time-multiplexes the serial proportional and integral signals to emulate a 1-pole/1-zero filter. An acquisition speed control circuit controls the acquisition time as well as step sizes of the scaler (proportional path) and the integrator (integral path) to provide loop variable programmability.

Abstract: A phase locked loop includes a capture aid circuit to pull the frequency of the oscillator towards the bit frequency of a data signal HF.sub.in consisting of pulses of variable lengths, each length being an integral multiple of a single bit basic length unit. The capture aid circuit includes a pulse length detector for measuring and rounding pulse length to the nearest integral number of basic length units, and determining the difference (.DELTA.RL) between the measured and rounded length value (RL). For small frequency deviations the rounding error (.DELTA.RL) signal is used as a frequency deviation control signal for increasing or decreasing the oscillator frequency. For larger frequency deviations the minimum pulse length will be either more or less than a predetermined number of length units.

Abstract: An improved digital phase locked loop (DPLL) has a fixed bandwidth independent of manufacturing and environmental variations. The DPLL bandwidth is optimized by monitoring the delay propagation, i.e., the "silicon speed", of the module. This information is used by a bandwidth regulator to control the characteristics of the low pass filter in the phase locked loop. The digital phase locked loop is also programmable to allow the user to control the phase shifting of the retiming clock. A phase shift control for a second, slave controlled oscillator is used to retime the received data. This phase shift control allows the user to control the phase shifting of a retiming latch.

Abstract: A wavemeter/frequency locking technique suitable for indirectly locking an optical frequency f.sub.0 to a radio frequency f.sub.1 or for locking the radio frequency to the optical frequency. A beam of optical frequency f.sub.0 is phase modulated by a signal of average frequency f.sub.1 that is itself modulated at frequency f.sub.2. The modulated beam is passed through a filter to a detector to produce a detector output signal that has components at linear integral sums of f.sub.1 and f.sub.2. A pair of control signals are generated that are proportional to the amplitude of two of the components of the detector output signal. These control signals are separately used in a pair of servo loops to separately establish fixed values of f.sub.0 /f.sub.f and f.sub.1 /f.sub.f, where f.sub.f is a characteristic frequency of the filter. A method is presented for stepping the value of f.sub.0 /f.sub.f to another value and measuring f.sub.1 /f.sub.2 at each of these values, thereby enabling the value of f.sub.

Abstract: A phase-locked loop is constituted by a controllable oscillator coupled through a phase detection arrangement and a low-pass filter to receive an input carrier applied to a signal input of the phase detection arrangement. In order to decrease the phase synchronization between a carrier locally generated in the loop and an input carrier, an unwanted DC offset generated during phase detection is reduced. The phase detection arrangement has first, second and third cascade-coupled mixer stages. An auxiliary mixing signal is applied from a signal generator to the first and third mixer stages. An input of one of the first and second mixer stages is coupled to the signal input of the phase detection arrangement and an input of the other of the two last-mentioned stages is coupled to an output of the controllable oscillator. The low-pass filter has a cut-off frequency lower than the fundamental frequency of the auxiliary mixing signal, and the fundamental frequency is lower than the frequency of the input carrier.

Abstract: An AFC circuit may include an oscillator having an output frequency responsive to a derived error signal, a mixer for mixing a received signal with the output of the oscillator to produce an intermediate frequency, and a signal recovery detector for recovering the information carried by the intermediate frequency. An integral loop filter and compensation circuit receives the recovered signal from the detector, provides a compensated recovery signal which is independent of the closed loop frequency response of the AFC circuit, and provides an error signal which controls the oscillator.

Abstract: An automatic local oscillation frequency control apparatus for a television receiver is disclosed, wherein a video intermediate frequency (VIF) signal is applied to an FM discriminator for generating an AFC voltage through a phase shifter comprised of a serial-parallel resonance circuit, and one of the serial resonance frequency and the parallel resonance frequency of the serial-parallel resonance circuit is selected to be a frequency near a picture carrier frequency while the other is selected to be a frequency which is made by subtracting one half of a differential frequency between the picture carrier frequency and a sound carrier frequency from the picture carrier frequency. The present apparatus can attain an automatic frequency control having a wide pull-in range and a wide hold range.

Abstract: A frequency synthesizer having a frequency-locked loop providing any digitally selected output frequency, and means to frequency modulate the selected output frequency at an audio rate. The frequency-locked loop includes a frequency-to-current converter coupled to the output of a voltage-controlled oscillator to provide a current, representing the actual frequency of the oscillator, which is compared with a current representing a desired output frequency. A resulting error signal controls the oscillator center frequency, which can be frequency modulated by an audio-frequency signal.

Abstract: An oscillator or similar device employing a frequency setting SAW element having a piezoelectric substrate and an arrangement of interdigital finger transducers mounted thereon. In one embodiment, two interdigital finger transducers provide surface acoustic wave launching and reception respectively and in another embodiment, two additional transducers form a part of a discriminator circuit. Phase detection either between the electrical connections of the launching and receiving transducers or through the discriminator arrangement generates a feedback control signal which is applied across the ends of the substrate as a stress-controlling signal in a manner to compensate for temperature and other environmental factors which otherwise change the frequency of oscillation.