Abstract: A method for searching a spur in a signal received is described, wherein a fast sweep measurement with a high resolution bandwidth is performed in order to detect at least one spur. Further, a detailed sweep measurement with narrow resolution bandwidth is performed in order to analyze said spur detected. Said narrow resolution bandwidth needed for said detailed sweep measurement of said spur is determined automatically. Further, a device for searching a spur in a signal received is described.

Abstract: A radio frequency heating apparatus includes a printed circuit board on which power-supply noise filter circuit (20) that reduces power-supply noise generated by magnetron (15) and power-supply synchronization detecting circuit (21) that is connected across both terminals of power supply for detecting information on power-supply frequency are mounted. Power-supply synchronization detecting circuit (21) is used as a discharge path for charge accumulated at both ends of capacitor (3) configuring power-supply noise filter circuit (20). This achieves the radio frequency heating apparatus that eliminates the risk of electric shock, reduces power consumption, and reduces the number of components.

Abstract: Provided is an oscillator (100) including a piezoelectric body (70) that has a plurality of protrusions (72) on one surface thereof, a plurality of electrodes (80) that are respectively provided on the plurality of protrusions (72) so as to be separated from each other, and a plurality of electrodes (82) that are provided on the other surface opposite to the one surface of the piezoelectric body (70) so that each of the electrodes faces only one electrode (80). Thus, it is possible to prevent variation in acoustic characteristics from occurring. Therefore, the oscillator capable of improving the acoustic characteristics of an electronic device is provided.

Abstract: A technique to provide hybrid compensation to correct for drifts in a reference frequency output from a digitally-controlled crystal oscillator (DCXO). A first compensation is provided to the DCXO to adjust for overlap or discontinuity of the reference frequency caused by switching capacitors in the capacitor array that controls drift of the reference frequency output. The second compensation is obtained at a phase-locked loop (PLL) that receives the reference frequency signal from the DCXO. The second compensation adjusts the PLL to adjust for variations of the reference frequency that remain after performing compensation in the DCXO.

Abstract: A microwave synthesizer is disclosed that may generate low phase noise and high frequency resolution microwave signals The microwave synthesizer may include a coarse-tuning loop, the coarse-tuning loop may be adopted to generate a first signal with coarsely adjustable frequency. The coarse-tuning loop may have a first voltage controlled oscillator (VCO). An output loop, the output loop may be adopted to generate a second signal with finely adjustable frequency. The output loop may have a second VCO. A frequency mixer may be configured to couple the coarse-tuning loop and the output loop. A frequency mixer may be adopted to subtract the first and second signals. A reference frequency source may be coupled to the coarse-tuning loop and the output loop to provide reference signal for the microwave synthesizer.

Abstract: A frequency synthesiser and oscillator are disclosed for reducing noise in processed signals. The synthesiser and oscillator comprise an array of frequency dividers adapted to receive an input signal, which is derived from a single signal source having a prescribed frequency. The synthesiser and oscillator further comprise at least one frequency multiplier coupled to at least one of the frequency dividers, such that in use, the dividers and the at least one multiplier are operable to generate a plurality of frequencies which are coherent with the prescribed frequency. A regulated power supply is also disclosed comprising a filter and first and second regulators, for reducing noise in the output voltage of the power supply.

Abstract: An oscillation frequency control circuit configured to control a frequency of a second clock signal of an oscillation circuit generating and outputting the second clock signal having a frequency in response to an input control signal is disclosed. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a frequency of a predetermined first clock signal input externally and the frequency of the second clock signal, and generate and output a signal indicating a result of the detection; and a frequency control circuit unit configured to control the frequency of the second clock signal so that the frequency of the second clock signal continually changes back and forth between a predetermined lower limit value and a predetermined upper limit value in response to the output signal from the frequency difference detection circuit.

Abstract: A single side band (SSB) mixer includes an in-phase SSB mixer unit and a quadrature-phase SSB mixer unit. The in-phase SSB mixer unit generates an in-phase output current, and includes a first transformer load in which a portion of a quadrature-phase output current flows. The quadrature-phase SSB mixer unit generates the quadrature-phase output current, and includes a second transformer load in which a portion of the in-phase output current flows. The SSB mixer may be used in a wide frequency band without degrading frequency selectivity.

Abstract: A local oscillator circuit for a signal transmitter or receiver, the circuit comprising: an input for receiving a master oscillating signal from a master oscillator; and signal processing circuitry configured to be clocked by the master oscillating signal to generate a local oscillator signal, the signal processing circuitry being such that the local oscillator signal has substantially no harmonic content at any integer multiple of the frequency of the master oscillator signal, which oscillates at (2n+1)/2 times the frequency of the generated local oscillator signal, with n being a positive integer.

Abstract: A dual-band wideband local oscillation signal generator includes an oscillation unit, a division unit, a poly phase filter (PPF), a switch unit, and a single side band (SSB) mixer. The oscillation unit is configured to generate a positive in-phase (IP) signal, a negative in-phase (IN) signal, a negative quadrature-phase (QN) signal, and a positive quadrature-phase (QP) signal. The division unit is configured to divide frequencies of the IP signal and the IN signal and generate an RF signal. The PPF is configured to receive the IP signal and the IN signals inputted to the division unit, and generate an LO IP signal, an LO IN signal, an LO QP signal, and an LO QN signal. The switch unit is configured to receive the generated LO signals and select a high band frequency signal or a low band frequency signal.

Abstract: Embodiments of the present invention include circuits and methods for improving the spectral purity of mixer circuits. In one embodiment the present invention includes a mixer circuit comprising a first transistor having a gate, a source and a drain, a second transistor having a gate, a source and a drain, a first capacitance coupled between the source of the first transistor and the source of the second transistor and a bias circuit having an input, a first output coupled to the source of the first transistor and a second output coupled to the source of the second transistor. The present invention may be advantageously used in a wireless transmitter application.

Abstract: Techniques for providing voltage-controlled oscillator circuits having improved phase noise performance and lower power consumption. In an exemplary embodiment, a voltage controlled oscillator (VCO) is coupled to a mixer or a frequency divider such as a divide-by-two circuit. The VCO includes a transistor pair with magnetically cross-coupled inductors, and variable capacitance coupled to the gates of the transistor pair. In an exemplary embodiment, a frequency divider is configured to divide the frequency of the differential current flowing through the transistor pair to generate the LO output. In an alternative exemplary embodiment, a mixer is configured to mix the differential current flowing through the transistor pair with another signal. The VCO and mixer or frequency divider share common bias currents, thereby reducing power consumption. Various exemplary apparatuses and methods utilizing these techniques are disclosed.

Abstract: The present invention is a Chip Scale Atomic Clock (CSAC)-enabled Time and Frequency Standard (CTFS) architecture. The CTFS architecture includes a microcontroller, a Time Compensated Crystal Oscillator (TCCO) circuit which is connected to the microcontroller, and a Chip Scale Atomic Clock (CSAC) which is connected to the microcontroller. The microcontroller is configured for selectively causing the CTFS to provide a TCCO circuit-based output frequency when the CTFS has not locked to a predetermined atomic resonance, and is further configured for causing the CTFS to provide a CSAC-based output frequency when the CTFS has locked to a predetermined atomic resonance.

Abstract: There is provided a system for comparing the phase characteristics of three generated clock signals, each having a unique phase relationship with an original clock signal, with the original clock signal and to select a signal based on the proximity of the phase characteristic of the three signals to the original signal. The selection of a clock signal that most closely approximates the original significantly reduces lock time when attempting to synchronize an internal clock with an external clock. Additionally, there is provided a method for comparing three clock signals with an original clock signal and selecting from the three clock signals one that is approximately in phase with the original clock signal.

Abstract: A selectable local oscillator provides an output frequency signal having a selectable frequency within a desired output frequency range. The selectable local oscillator comprises first, second and third signal generators configured to provide first, second and third frequency signals having frequencies in first, second and third input frequency ranges. A first mixer provides a first mixed product signal having an upper sideband and a lower sideband. A frequency selector selects one of the upper and lower sidebands of the first mixed product signal. A second mixer provides a second mixed product signal having an upper sideband and a lower sideband. An output stage selects at least one of the upper and lower sidebands of the second mixed product signal as the output frequency signal.

Abstract: The present invention provides a frequency synthesizer for a wireless communication system. The synthesizer includes an oscillator that generates an electronic signal as well as frequency dividers, frequency selectors and mixers. The signal generated by the oscillator is sequentially divided by the frequency dividers to produce a first group of frequencies, and the selectors and mixers are then capable of mixing the first group of frequencies according to instructions from control bits to produce a second group of frequencies which constitute UWB band frequencies. In this manner, the synthesizer can generate all 14 UWB band frequencies or particular UWB band groups using a single oscillator. One of the frequencies generated by the dividers can also be used as the baseband clock signal without requiring an additional frequency source.

Abstract: Certain aspects of a method and system for simultaneous FM transmission and FM reception using a shared antenna and a direct digital frequency synthesizer (DDFS) may be disclosed. In a FM transceiver that receives FM signals at a frequency f1 and transmits FM signals at a frequency f2, aspects of the method may include generating via a DDFS, a signal corresponding to a difference between f1 and f2 to enable simultaneous transmission and reception of FM signals via shared antenna.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. An input baseband signal is interpolated and upconverted in the digital domain to an IF. The LO operates at a frequency which is a n/m division of the target RF frequency fRF. The IF frequency is configured to ½ of the LO frequency. The upconverted IF signal is then converted to the analog domain via digital power amplifiers followed by voltage combiners. The output of the combiners is band pass filtered to extract the desired replica.

Abstract: There is provided a feedback circuit including: an oscillator generating an oscillation frequency signal; a mixer unit having an input terminal, a feedback terminal, and an output terminal and outputting a frequency signal through the output terminal, the frequency signal obtained by adding or subtracting frequency of a feedback signal, input through the feedback terminal, to or from frequency of the oscillation frequency signal input through the input terminal from the oscillator; a first frequency divider dividing the frequency signal output from the mixer unit at a division ratio of N (N is a multiple of 2) to generate an output signal; and a feedback circuit adjusting the output signal of the first frequency divider for the first frequency divider to output a frequency signal in a desired band and feeding back the adjusted signal to the feedback terminal of the mixer unit.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The signal is input to a synthesizer timed to a rational multiplier of the RF frequency fRF. The signal is then divided to generate a plurality of phases of the divided signal. A plurality of combination signals are generated which are then multiplied by a set of weights and summed to cancel out some undersired products. The result is filtered to generate the LO output signal.

Abstract: According to one exemplary embodiment, a local oscillation generator includes a mixing stage for receiving a primary frequency and one of a number of related frequencies. The local oscillation generator further includes a first transconductance stage to provide a first related frequency to the mixing stage when a first switch selectably enables a first power path in the first transconductance stage. The local oscillation generator further includes a second transconductance stage to provide a second related frequency to the mixing stage when a second switch selectably enables a second power path in the second transconductance stage. The local oscillation generator further includes a number of dividers, where an output of a first divider provides the first related frequency to an input of the first transconductance stage, and where an output of a second divider provides the second related frequency to an input of the second transconductance stage.

Abstract: A novel and useful apparatus for and method of local oscillator (LO) generation with non-integer multiplication ratio between the local oscillator and RF frequencies. The LO generation schemes presented are operative to generate I and Q square waves at a designated frequency while avoiding the well known issue of harmonic pulling. The input signal is fed to a synthesizer timed to a rational multiplier of the RF frequency L/N fRF. The clock signal generated is divided by a factor Q to form 2Q phases of the clock at a frequency of L(N*Q)fRF, wherein each phase undergoes division by L. The phase signals are input to a pulse generator which outputs a plurality of pulses. The pulses are input to a selector which selects which signal to output at any point in time. By controlling the selector, the output clock is generated as a TDM based signal. Any spurs are removed by an optional filter.

Abstract: Device and method for temperature compensation in a clock oscillator using quartz crystals, which integrates dual crystal oscillators. The minimal power consumption is achieved through an efficient use of a processor in charge of the synchronization of the two oscillators. The invention is particularly adapted for the provision of a precise reference clock in portable radiolocalization devices.

Abstract: A frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver is provided. The frequency synthesizing apparatus includes a simple circuit configuration with a single SSB mixer and thus, may synthesize six high frequency signals. Signals to be inputted into the SSB mixer include a first signal and a second signal. The first signal is generated based on a VCO and a PPF. Also, the second signal is selected from a plurality of frequency divided signals which are generated by dividing a signal generated in the VCO via a plurality of dividers.

Abstract: A DPLL circuit is provided for making it possible to inhibit an initial frequency offset during holdover. The DPLL circuit includes a slave oscillator for generating a frequency signal corresponding to the size of a control signal value; a phase difference detection circuit for detecting the difference in phase between the output of said slave oscillator and the inputted reference clock, and outputting a digital signal of the prescribed number of bits corresponding to said detected phase difference; and a holdover unit for generating a correction value based on the output of said phase difference detection circuit, wherein when the holdover is detected, said holdover unit periodically adds the correction value to the output of said phase difference detection circuit to obtain a control value for said slave oscillator.

Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes a voltage control oscillator (VCO) and a mixer. The VCO includes a LC resonance tank and a negative-resistance generator for generating a differential oscillation signal including a first and a second oscillation signals. The LC resonance tank adjusts a VCO reactance and resonates for generating the differential oscillation signal. The negative-resistance generator coupled to the LC resonance tank eliminates an equivalent resistance generated by the LC resonance tank and maintains the VCO to continuously oscillate.

Abstract: A frequency synthesizing apparatus and method having an injection-locked quadrature VCO in an RF transceiver is provided. In the frequency synthesizer, an I signal following a frequency of a high frequency signal that is input using the injection-locked quadrature VCO and a Q signal thereof are simultaneously generated to have an appropriate driving power. Accordingly, the I signal and the Q signal thereof that are generated in the injection-locked quadrature VCO may be utilized as a local signal for frequency up/down-conversion, without being buffered. An output of an SSB mixer may be directly input into the injection-locked quadrature VCO. Also, high frequency signals that are generated in another circuit such as the SSB mixer, a PLL, or a VCO may be selected to be input into the injection-locked quadrature VCO by a selector.

Abstract: A wireless communication device is disclosed wherein isolation buffers couple to respective active circuits or stages of the device to convey test information regarding such active circuits to a test data line from which status information may be collected. The communication device operates in two modes, namely a normal operational mode wherein the isolation buffers effectively short spurious emissions from the active circuits to a ground, and a test mode wherein the isolation buffers may convey test information from a selected active circuit to the test data line. The isolation buffers prevent spurious emissions from escaping the active circuits to which they are coupled and prevent spurious emissions from traveling from active circuit to active circuit over the test data line throughout the wireless device.

Abstract: A local oscillator (LO) generator architecture using a wide tuning range oscillator is disclosed. In one embodiment, a wide tuning oscillator based LO generator system includes a wide tuning range oscillator for generating a signal with a first initial frequency or a second initial frequency in response to a control voltage, a first frequency controlling circuit for converting the first initial frequency of the signal into a final frequency, and a second frequency controlling circuit for converting the second initial frequency of the signal into the final frequency.

Abstract: There is provided a feedback circuit including: an oscillator generating an oscillation frequency signal; a mixer unit having an input terminal, a feedback terminal, and an output terminal and outputting a frequency signal through the output terminal, the frequency signal obtained by adding or subtracting frequency of a feedback signal, input through the feedback terminal, to or from frequency of the oscillation frequency signal input through the input terminal from the oscillator; a first frequency divider dividing the frequency signal output from the mixer unit at a division ratio of N (N is a multiple of 2) to generate an output signal; and a feedback circuit adjusting the output signal of the first frequency divider for the first frequency divider to output a frequency signal in a desired band and feeding back the adjusted signal to the feedback terminal of the mixer unit.

Abstract: An injection-locked frequency divider is provided. The injection-locked frequency divider includes a voltage control oscillator (VCO) and a mixer. The VCO includes a LC resonance tank and a negative-resistance generator for generating a differential oscillation signal including a first and a second oscillation signals. The LC resonance tank adjusts a VCO reactance and resonates for generating the differential oscillation signal. The negative-resistance generator coupled to the LC resonance tank eliminates an equivalent resistance generated by the LC resonance tank and maintains the VCO to continuously oscillate.

Abstract: An oscillating apparatus for outputting an oscillating signal includes a resonant circuit that generates the oscillating signal, an amplifier circuit that amplifies the oscillating signal generated by the resonant circuit, and feeds the amplified oscillating signal back to the resonant circuit, and an output circuit that receives the oscillating signal which is supplied to the amplifier circuit, and outputs the received oscillating signal to outside.

Abstract: A frequency synthesizing apparatus and method for a multi-band radio frequency (RF) receiver is provided. The frequency synthesizing apparatus includes a simple circuit configuration with a single SSB mixer and thus, may synthesize six high frequency signals. Signals to be inputted into the SSB mixer include a first signal and a second signal. The first signal is generated based on a VCO and a PPF. Also, the second signal is selected from a plurality of frequency divided signals which are generated by dividing a signal generated in the VCO via a plurality of dividers.

Abstract: A simple low cost integrated circuit oscillator includes a capacitor coupled to be charged and discharged by first and second current sources. A first voltage follower circuit including a first bipolar transistor having a base is coupled to the capacitor. The first bipolar transistor is biased such that a voltage at an emitter of the first bipolar transistor follows a voltage on the capacitor. A first current path of a current mirror is coupled to the base of the first bipolar transistor. The first current path provides substantially all of a base current received by the base of the first bipolar transistor. A second voltage follower circuit including a second bipolar transistor having a base coupled to a second current path of the current mirror. The second current path provides substantially all of a base current received by the base of the second bipolar transistor.

Abstract: Implementations related to circuits including an oscillator and a switch-mode DC/DC converter are presented herein.

Abstract: A control loop (10) for producing an output signal with a stable nominal frequency is provided. The control loop includes inputs for reference (11) and oscillator (25) output signals, a beat frequency generator (12) for producing a signal with a frequency that is the difference between the oscillator and reference signal frequencies, an ADC (14) to convert the beat frequency to a digital beat frequency signal, an estimator (17) for estimating the frequency or phase of the beat signal, an adder (18) for combining an offset and modulation signal and the estimated frequency or phase of the beat signal into an added signal, and a DAC (23) for generating an analogue control signal for controlling the oscillator output frequency.

Abstract: A fully integrated, programmable mixed-signal radio transceiver comprising a radio frequency integrated circuit (RFIC) which is frequency and protocol agnostic with digital inputs and outputs, the radio transceiver being programmable and configurable for multiple radio frequency bands and standards and being capable of connecting to many networks and service providers. The RFIC includes a tunable resonant circuit that includes a transmission line having an inductance, a plurality of switchable capacitors configured to be switched into and out of the tunable resonant circuit in response to a first control signal, and at least one variable capacitor that can be varied in response to a second control signal, wherein a center resonant frequency of the resonant circuit is electronically tunable responsive to the first and second control signals that control a first capacitance value of the plurality of switchable capacitors and a second capacitance value of the at least one variable capacitor.

Abstract: An apparatus providing a simple low cost integrated circuit oscillator with improved frequency stability over a range of selected frequencies by reducing the impact of process and temperature variations on a base current of bipolar transistor of the integrated circuit oscillator. A circuit includes a capacitor coupled to be alternatingly charged and discharged by first and second current sources. A first voltage follower circuit including a first bipolar transistor having a base is coupled to the capacitor. The first bipolar transistor is biased such that a voltage at an emitter of the first bipolar transistor follows a voltage on the capacitor. A current mirror having first and second current paths is included. The first current path is coupled to the base of the first bipolar transistor. The first current path provides substantially all of a base current received by the base of the first bipolar transistor.

Abstract: The present invention relates generally to communications, and more specifically to a method and apparatus for generating local oscillator signals used for up- and down-conversion of RF (radio frequency) signals. A major problem in the design of modulators and demodulators, if the leakage of local oscillator (LO) signals into the received signal path. The invention presents a number of highly integratable circuits which resolve the LO leakage problem, using regenerative divider circuits acting on oscillator signals which are running at a multiple or fraction of the frequency of the desired LO signal, to generate in-phase (I) and quadrature (Q) mixing signals. Embodiments of these circuits also use harmonic subtraction and polyphase mixers, as well as virtual local oscillator TM (VLO) mixing signals. VLO mixing signals are signal pairs which emulate local oscillator signals by means of complementary mono-tonal and multi-tonal mixing signals.

Abstract: Embodiments of the present invention include mixer circuits and methods with improved spectral purity. In one embodiment the present invention includes a mixer circuit comprising a first transistor having a gate, a source and a drain, a second transistor having a gate, a source and a drain, a first capacitance coupled between the source of the first transistor and the source of the second transistor and a bias circuit having an input, a first output coupled to the source of the first transistor and a second output coupled to the source of the second transistor. The present invention may be advantageously used in a wireless transmitter application.

Abstract: An apparatus and method of controlling an optical signal includes superimposing at least one optical reference signal and the optical signal to obtain at least one interference signal having an actual beat frequency, and pre-selecting one or more of the at least one interference signals using a predetermined bandwidth and a filter characteristic that is asymmetric with respect to an actual frequency of the optical signal, to determine a position of the optical signal relative to the at least one optical reference signal.

Abstract: A method and apparatus providing a simple low cost integrated circuit oscillator with improved frequency stability over a range of selected frequencies by reducing the impact of process and temperature variations on a base current of bipolar transistor of the integrated circuit oscillator. A voltage follower circuit included in an integrated circuit oscillator provided to is injected with a base current provided by a current mirror instead of a capacitor such that variations in the base current of the bipolar transistor over the range of operating temperature do not substantially alter the charge in the capacitor to change the frequency of the oscillator.

Abstract: A system and method for generating a local oscillator (LO) frequency in a zero intermediate frequency (IF) receiver or transmitter is presented. A signal is received from a voltage controlled oscillator (VCO). The signal has a VCO frequency. The VCO frequency is divided by a number N to produce a signal having a divided-down frequency. The signal having the VCO frequency is then mixed with the signal having the divided-down frequency to produce an output signal having an output frequency. Local oscillator leakage is reduced. Thus, the receiver or transmitter may operate in multiple wireless communication bands and modes and meet the associated specifications.

Abstract: An output cycle of a pulse string generated from a pulse generating section (2) is divided by a pulse dividing section (3) and a signal having a cycle which is plural times as great as the cycle of an output pulse is output from the pulse dividing section (3). This signal is input as an interruption request signal to a CPU (1). Consequently, the CPU (1) can execute an interruption processing in a cycle which is plural times as great as the cycle of the output pulse. By the interruption processing, the number of pulses to be output is controlled.

Abstract: A transmit frequency is generated for a transceiver by a controllable oscillator which generates an oscillator frequency, a divider by a factor N, and a mixer stage with a subsequent band filter. Signals with the oscillator frequency and the oscillator frequency divided by the factor N are to the mixer stage to generate an output signal at the transmit frequency.

Abstract: A duty cycle regulator derives from an input clock of arbitrary duty cycle, an output clock having an adjustable duty cycle of similar frequency. The duty cycle regulator includes a bistable circuit for receiving an input clock pulse and providing the output clock, coupled through a feedback loop to an adjustable delay unit having a delay interval equal to an adjustable fraction of the input clock period. When an input clock pulse is received, the bistable circuit is set, providing a high signal to the delay unit, after which the delay interval resets the bistable circuit to provide a low signal. The delay unit includes two charge pumps alternately feeding and draining electric charges into and from a low-pass filter. The delay interval can be adjusted to a desired duty cycle independent of the input clock frequency, by setting the ratio of electric currents through the two charge pumps.

Abstract: A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

Abstract: A technique for adjusting a bias-generator in a phase locked loop after fabrication of the phase locked loop is provided. The technique involves use of an adjustment circuit operatively connected to the bias-generator, where the adjustment circuit is controllable to facilitate a modification of a voltage output by the bias-generator. Such control of the voltage output by the bias-generator allows a designer to achieve a desired phase locked loop performance characteristic after the phase locked loop has been fabricated.

Abstract: A duty-cycle regulation method for deriving an output clock signal having a predetermined duty cycle from an input clock signal having an arbitrary duty cycle. Once the input clock signal is received, an output clock storage element is switched to a first state upon detecting a transition in the input clock signal for driving the output clock signal to a first signal level. The output clock storage element is then switched to a second state after a delay interval equal to a fraction of the period for driving the output clock signal to a second signal level. The fraction of the period can be programmed to a pre-selected value.

Abstract: A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.