Abstract: An apparatus including a driver and an adjustment circuit. The driver circuit may be configured to generate an output signal in response to a clock input signal and an adjustment signal. The adjustment circuit may be configured to generate the adjustment signal in response to the output signal. The adjustment signal may be configured to correct a duty cycle of the output signal.

Abstract: A microwave synthesizer includes a drift-cancel loop having a narrow-band input, a low-frequency comb input, a wide-band input, and an output for providing an adjustable-frequency output signal. A narrow-band synthesizer is coupled to the narrow-band input, and a comb generator is coupled to the low-frequency comb input. Instead of using a wide-band synthesizer to drive the wide-band input, as conventional topologies have done, the instant invention employs a highly stable, low noise high frequency oscillator. The output of the oscillator is mixed with the output of the comb generator to produce low-noise, high frequency combs. The low-noise, high frequency combs are then used to drive the wide-band input of the drift-cancel loop. Significant reductions in phase noise can be achieved as compared with conventional designs.

Abstract: A voltage controlled oscillation device includes a voltage controlled oscillator, fixed-frequency oscillator, frequency mixer, and frequency selector. The voltage controlled oscillator changes the output signal frequency in the microwave band in accordance with the input voltage of a frequency control signal. The fixed-frequency oscillator has a fixed oscillation frequency higher than that of the voltage controlled oscillator. The frequency mixer mixes the output signal from the fixed-frequency oscillator and the output signal from the voltage controlled oscillator and outputs the sum frequency and difference frequency between the two signals. The frequency selector selects and outputs one of the sum frequency and difference frequency contained in the output signal from the frequency mixer.

Abstract: A phase lock loop (PLL) and methods for using same is provided that includes a multiple-feedback CMOS voltage control oscillator (VCO) and multi-phase sampling fractional-N prescaler. The PLL provides increased performance characteristics for a single chip CMOS radio frequency (RF) communications system. The multiple feedback CMOS VCO maintains an amplitude of a VCO signal while reducing a rise/fall time of the VCO signal. The multiple feedback CMOS VCO further reduces supply noise effects. The multi-phase sampling fractional-N prescaler provides sufficient bandwidth for a CMOS VCO while maintaining spectral purity and reducing fractional-spur. The multi-phase sampling fractional-N prescaler can include a divider, a sampler circuit, a selector circuit and a modular counter.

Abstract: An oscillator circuit is disclosed which includes an oscillator to generate a first signal having a first frequency, a second oscillation source to generate a second signal having a second frequency, the second oscillator comprising a frequency divider coupled to the oscillator, and a mixer to mix to the first and second signals, wherein the oscillator, frequency divider and mixer are each quadrature. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: The resonant circuit has at least one resonant body of a semiconductor material anchored on the surface of a semiconductor substrate, at least one first electrode being arranged at said semiconductor material, and at least one second electrode. The first and second electrode are arranged lying opposite one another. When an AC-superimposed DC voltage is applied between the first and the second electrode, the resonant body is excited to mechanical oscillation by the DC voltage. In particular, the resonant circuit can be monoically integrated in electronic circuits.

Abstract: Backbias voltage generation circuit corresponding to the frequency of a chip control signal is disclosed. The circuit includes a normal driving unit, an active driving unit and a level detecting unit. The level detecting unit detects whether a backbias voltage VBB is equal to or higher than a target voltage level. A normal control signal DETN is activated to enable the normal driving unit, and an active control signal DETA is activated to enable the active driving unit. The normal driving unit pumps down the backbias voltage VBB independent of the chip control signal CONC. The active driving unit includes a counter circuit and an active pumping unit. The counter circuit generates first and second edge detecting signals FED and RED in response to an activating edge of the chip control signal CONC. The active pumping unit pumps down the backbias voltage VBB, when the first edge signal FED or second edge signal RED is activated.

Abstract: A frequency generating circuit scales a warp range of a frequency signal. The frequency generating circuit includes a first frequency signal (10) having a first offset signal with a first frequency relationship to the first frequency signal, and a second frequency signal (14). A frequency scaling element (16) receives the first frequency signal (10) and second frequency signal and provides a third frequency signal, such that the third frequency signal includes the first offset signal having a second frequency relationship to the third signal. A switch (54), has a control input (74), a first input for receiving the first frequency signal, a second input operably coupled to the frequency scaling element (16, 42) for receiving the third frequency signal and an output (76) operably coupled to the first input or the second input dependent upon a control signal applied to the control input (74).

Abstract: A system for phase-locking a clock to a digital audio signal embedded within a digital video signal uses an audio extractor, frequency dividers, and an adjusted bandwidth loop filter to prevent phase jitter associated with the digital audio signal preventing the functionality of the phase-lock loop or having unacceptable effects on the generated audio sample frequency signal. Extracted audio samples are divided down and input to a phase detector. The signal is then filtered using a series of loop filters, one of which has an adjusted bandwidth to reject phase jitter. A clock then outputs the generated synthesized audio sample frequency using the output from the series of loop filters, and the synthesized frequency signal is looped back through a second frequency divider to the phase detector.

Abstract: A duty cycle control buffer uses an edge detector input stage to detect the transitions of an unpredictable clock signal input. The edge detector generates one shot output signals in synchronism with the clock signal. A pulse width controllable monostable multivibrator converts the one shot signals into rectangular pulses, at the same frequency as the original clock input. The rectangular pulses are inverted and then averaged, to provide a voltage input to one side of an operational amplifier. A reference voltage is supplied to the other side of the operational amplifier, such that the difference between the average voltage and the reference voltage generates an output control voltage from the operational amplifier. This control voltage provides negative feedback to a pulse width control stage within the monostable multivibrator, thereby adjusting the pulse width of the rectangular pulse output until a steady state is reached.

Abstract: A voltage controlled oscillator comprises first oscillating stage for outputting a first frequency signal, second oscillating stage for outputting a second frequency signal different from the first frequency signal, a buffer stage connected with said first and second oscillating stages, the buffer stage receiving said first and second frequency signals to generate an output signal.

Abstract: A phase noise measurement system including a low noise programmable synthesizer and a receiver/down converter is provided. The low noise synthesizer provides L-Band Signals which can selectively exhibit low noise close-in or low noise far out. The receiver down converter provides for absolute, additive, and down converted/direct/multiple phase noise measurement.

Abstract: A circuit for controlling clock frequency change circuitry to control a frequency of a system clock in response to a clock frequency indication, wherein operating circuitry of an electronic system operates responsive to the system clock. First flip-flop circuitry has an input portion coupled to receive the clock frequency indication. The first flip flop circuitry is configured to pass data from the input portion to an output portion responsive to a first polarity transition of the internal clock. Second flip-flop circuitry has an input portion coupled to the output portion of the first flip-flop circuitry. The second flip-flop circuitry configured to pass data from an input to an output portion responsive to a second polarity transition of the internal clock.

Abstract: A mixed signal phase locked loop is optimized for fast settling and low noise sensitivity. To this end, this device has a digital wide range delay line and a low gain per stage adjust. When first activated, the loop calibrates the digital delay line to its nominal delay characteristic. This delay line, together with the linear low gain per stage adjust, constitutes the internal oscillator of the phase locked loop. After achieving nominal delay, the oscillator uses the low gain per stage adjust to lock to a desired reference or a submultiple thereof. According to the preferred embodiment, the loop locks its internal 125 MHz oscillator to a 25 MHz reference. After achieving lock, the loop performs synchronous data recovery by locking to an incoming data stream, instead of the internal reference, and performing bit framing. In case of losing lock, the phase locked loop of the present invention is capable of recalibrating itself and regaining lock in under 3 microseconds.

Abstract: An optically controlled oscillator utilizes a HEMT or a PIN diode as a photodetector and either a HEMT or HBT as an active inductor. The optically controlled HEMT active inductor provides a means for tuning the frequency of the oscillator. The optical receiver includes an optically tunable active inductor using a photodetector which includes a resonant tank circuit of an electronic oscillator to allow both optical/digital quench and unquench of an oscillator or digital AM detection with an improved signal to noise ratio, or optical FM modulation and analog AM detection by tuning/shifting the frequency of the oscillation through the detection of the optical light intensity.

Abstract: The ability to achieve ultra-fast frequency settling times with good frequency resolution and high absolute accuracy over significant bandwidth at microwave frequencies ranging over three octaves. The implementation is an open-loop system requiring little or no compensation of temperature. This is accomplished by providing a frequency doubled direct digital synthesizer output to up/down convert a microwave frequency source. A special tracking filter architecture coupled to the microwave source provides the suppression of unwanted products. Fixed frequency set-on and swept bandwidths in excess of 300 MHz have been demonstrated. This is accomplished by using a direct digitally synthesized quadrature phased carrier which can be set to any frequency within a 350 MHz bandwidth to coherently up/down convert a low phase-noise microwave frequency to the sum or the difference frequency product.

Abstract: A signal form synthesizer comprises a digital generator circuit (1) for generating the synthesis signal to produce a first series of digital samples which are representative of this signal and formed by binary words of N bits, and a digital-to-analog converter circuit (30) for producing an analog version of this signal. Furthermore, there is provided an assembly (40) for filtering in accordance with a band-pass characteristic curve the samples of the first series and for supplying to said digital-to-analog converter circuit (30) a second series of samples formed by binary words of N' bits, where N.gtoreq.N'. A negative feedback loop (45) subtracts the samples of the second series from the samples of the first series.

Abstract: A split dielectric resonator having two preferably half cylindrical dielectric elements is used to stabilize an oscillator operating at microwave frequencies. Fine tuning may be achieved by means of a tuning screw which has a thermal expansion coefficient between those of the dielectric elements and electrically conductive supporting walls. Additionally, fine tuning may be achieved by offsetting the two elements from each other within a horizontal or vertical plane. This oscillator can also be configured as an accelerometer or pressure or displacement sensor by substituting a movable deflecting member for the supporting wall.

Abstract: A frequency synthesizer includes three subfrequency synthesizers: a first synthesizer generating a first subfrequency varying in units of a frequency step, a second synthesizer generating a second subfrequency varying in units of a frequency step being N times the first frequency step, and a third synthesizer generating a third subfrequency varying in units of the first frequency step. One output signal is obtained by mixing the first subfrequency and the second subfrequency. A second output signal is obtained by mixing the second subfrequency and the third subfrequency.

Abstract: A low-power digital frequency synthesizer combining direct digital frequency synthesis techniques with serrodyne frequency translation principles to produce a wideband frequency response with high spectral purity. A conventional direct digital synthesizer is used to generate a high-resolution analog carrier signal from a low-speed digital clock signal. The carrier signal is phase modulated by a low-resolution signal generated from a high-speed digital clock signal. The modularity signal is a higher frequency signal than the carrier signal. The phase modulation is accomplished by exact decoded attenuators. The spectral purity of the resulting high-resolution output signal is unobtainable by conventional direct digital synthesizers, while providing significant power savings.

Abstract: A scanning-superhetrodyne ESM receiver having a VCO for a local oscillator which is linearized and temperature compensated. A stable combline oscillator is used to generate known frequency signals which are frequency converted to an intermediate frequency (IF) using the local oscillator and frequency converter (mixer). The frequency of each combine signal is measured and a table of known voltage/frequency points is generated. The table is input to a Cubic Spline program which computes the coefficients for the best-fit third order polynomial for each pair of data points. When a particular local oscillator frequency is desired, the corresponding tune voltage is computed by solving the polynomial equation for the given frequency range. By repeating the calibration on a periodic, or an "as needed" basis, temperature compensation is achieved.

Abstract: A microwave synthesiser comprising: a plurality of oscillator sources (1, 13, 3, 15, 5, 17, 7), each for generating signals over a range of frequencies, said ranges of frequencies together extending over a total range of frequencies generated; phase locked loops (19, 31, 83, 37, 38, 41, 81) for phase-locking any selected one of said oscillator sources (1, 13, 3, 15, 5, 17, 7) so that it generates signals of a frequency at which it is set; a single low harmonic modulator (21) for modulating the signals generated by the selected one of said oscillator sources (1, 13, 3, 15, 5, 17, 7), the modulated signals passing to an output (27) of said synthesiser; and at said output (27) elements (25, 29) for detecting the power of the signals at said output (27), the modulation by said single low harmonic modulator (21) being controlled in dependence on the detected power thereby to control the power of the signals at said output (27).

Abstract: A digitally controlled oscillator (100) having a first oscillator circuit (108) for providing an oscillator signal F.sub.o of a defined frequency and a digital divider (110) for dividing the oscillator signal F.sub.o by a selectable number controlled by a digital word for providing a clock signal F.sub.clk. A second oscillator circuit (104) receives the clock signal F.sub.clk and provides a low frequency signal F.sub.c. The second oscillator circuit includes a digitally controlled resonator element (112) for determining the frequency of the low frequency signal and has a center frequency dependent upon the clock signal. Circuitry (118, 120, 138) is included for providing first and second pairs of quadrature phase shifted signals derived from the clock signal F.sub.clk and the low frequency signal F.sub.c and from the oscillator signal F.sub.o, respectively.

Abstract: An apparatus and method is disclosed which phase locks a frequency-agile modulated output signal to any selected channel of a comb generated output. The phase error of an input signal is tracked, the input signal is modulated up to a carrier output frequency, and the modulated output frequency is locked to the comb generator output by subtracting the input signal and negating the phase error.

Abstract: Apparatus for reducing the effects of beat frequencies in systems having multiple oscillators wherein a wide band frequency modulator operates to alter the frequency supplied by one of the oscillators at a rate high enough that any beat frequencies occur at rates undetectable to the human eye.

Abstract: A circuit for generating jitter includes a mixer which mixes a jittered signal from a jitter generator with the output of a variable frequency oscillator to produce a broadband jittered output. A preferred form of the circuit uses a double frequency translation technique in which the output from a reference oscillator is applied to a jitter generator and to a first frequency translation device to translate a variable input frequency to an intermediate frequency. The jittered signal and the intermediate frequency signal are then applied to a second frequency translation device to produce a jittered output at the variable input frequency.

Abstract: A fast switching broadband signal synthesizer method and structure are provided which not only has the ability to change frequency and amplitude quickly, but with a minimal dwell time required before switching can again take place. A signal translator can also be constructed in accordance with this invention in order to convert the output frequency of a companion signal source to any desired frequency while retaining the fast switching speed and switching rate of the signal synthesizer. Amplitude, phase, and frequency modulation of the companion signal are preserved during the translation process. A direct frequency synthesizer is provided wherein internal signals which are combined to generate any output frequency are derived from a single fixed frequency oscillator. By utilizing a single reference frequency oscillator in accordance with this invention, the amount of circuitry required to construct a direct frequency synthesizer is greatly reduced.

Abstract: An improvement in a frequency synthesizer having a generator which produces mix frequencies and at least one mix and filter stage, said stage having a frequency divider. The improvement comprising: (1) a frequency divider for producing a periodic signal the frequency of which is an integer divisor of the mix frequencies, (2) a one-shot for producing an enabling signal whenever a change occurs in the selection of the frequency being synthesized, the duration of the enabling signal being sufficient to ensure coincidence of it and said periodic signal, and (3) a coincidence gate for resetting the frequency divider of each mix and filter stage to a predetermined state whenever there is a coincidence of the enabling signal and the periodic signal.

Abstract: A frequency synthesizer system generates a clock signal having an adjustable, accurate and stable frequency. The synthesizer produces a first reference frequency FR and an adjustable first intermediate frequency F1 equal to the frequency FR divided by a selectable number (N2/N1) which permits course adjustment of the frequency in steps over a prescribed range. The frequencies FR and F1 are then mixed and filtered to produce a second intermediate frequency FR+F1. The system also generates a second reference frequency F3 which is finely adjustable over a range in the order of magnitude of the frequency difference between two successive steps of the first intermediate frequency F1. This second reference frequency is mixed with the second intermediate frequency and the result is filtered to produce a final frequency FR+F1+F3.

Abstract: A frequency synthesizer has in series a digital synthesizer, mix and divide circuits, and a mix only circuit. Each mix and divide circuit includes a mixer having an IF input, a LO input and a RF output, a filter, and a frequency divider. A segment of a digital word selects a tone from a tone generator and also selects a passband of the filter. The selected tone is coupled to the LO input of the mixer. The frequency divider divides the filtered RF output of the mixer. The mix only circuit is at the output of the last of the series connected mix and divide circuits. The mix only circuit is similar to a mix and divide circuit, but does not have a frequency divider. The digital synthesizer provides a signal to the input of the first of the series connected mix and divide circuits, the frequency of which corresponds to a segment of a digital word. The filter is preferably a voltage tunable bandpass filter.

Abstract: A full-octave direct frequency synthesizer which can switch in under one microsecond and whose control frequencies are all harmonics of a single precision clock. Each stage generates a frequency in the 50-100 MHz range; the generated frequency is the sum of one-tenth of the input frequency plus an added increment within the full octave 50-100 MHz range. Each stage includes a first section for operating on the input frequency and the control frequencies for deriving a selected one of five possible frequencies, and a second section for deriving two possible frequencies from each of the five derivable by the first section. The final stage generates a frequency in the 500-1,000 MHz range, in steps of 0.5 Hz.

Abstract: A radio frequency (RF) signal generator is disclosed which generates a baseband signal at a fixed center frequency and having required modulation characteristics. The baseband signal is translated to a desired output frequency signal by mixing with a step-variable local oscillator signal. Fast frequency modulation is achieved by using a fast tuning oscillator as the source of the baseband signal. The output frequency is generated while preserving all modulation characteristics of the baseband signal and to thereby provide high performance modulation having characteristics at a fixed frequency.

Abstract: A generator circuit according to the invention generates two 90.degree. phase-shifted frequency-variable sinusoidal signals by mixing the output signal of a fixed-frequency oscillator and of a continuously variable oscillator with the aid of two multipliers operating as mixers. The fixed-frequency signal is applied to the second multiplier via a 90.degree. phase shifter. The output signal of the multipliers which contains the sum and the difference frequency of its input signals, is respectively fed to a low-pass filter or to a band-pass filter, which suppresses the sum frequency or the difference frequency respectively. By the 90.degree. phase shifter, the sinusoidal signal is phase-shifted with respect to the sinusoidal signal by exactly 90.degree.. During the continuous variation process, the signal as applied to the 90.degree. phase shifter remains stable in its frequency, whereas the output signal of the continuously variable oscillator as fed directly to the two multipliers, is changed in its frequency.

Abstract: The output signal frequencies of two current controlled oscillators are made to track closely by matching timing currents with a current mirror. A frequency difference between the output signals is obtained by establishing an additional timing current for only one of said oscillators.

Abstract: Disclosed is a low noise microwave frequency synthesizer having a plurality of rapidly switchable output frequencies. Two banks of oscillators are selectively mixed to yield a range of output signals of low phase noise and low spurious noise. The first bank of oscillators comprises low noise, highly stable oscillators of a frequency range below the desired synthesized output signal. The second bank of oscillators comprises low noise, highly stable oscillators of a frequency range lower than the first bank. The signal from the second bank of oscillators is frequency multiplied to a desired frequency range by a low multiplication factor and then mixed with the signal from the first bank of oscillators. Multiplied phase noise is reduced by using a low multiplication factor. The upper sideband of the mixed signals is output as the synthesized output signal. Rapid switching between oscillators in both banks provides a frequency range of synthesized output signals which may be rapidly stepped through as desired.

Abstract: A frequency discriminator having a wide capture band is shown to comprise, in addition to a conventional phase detector having two channels fed by a signal whose frequency is to be determined (the first one of the channels containing a tuned circuit operative to shift the phase of the signal in accordance with the difference between the frequency of the signal and the center frequency of the tuned circuit and the second one of the channels containing a phase shifter operative to shift the phase of the signal by 90.degree. regardless of the frequency of the signal), a compensating circuit operative substantially to equalize the amplitudes of the signals applied to the phase detector, the compensating circuit including an amplifier in the first one of the channels to amplify the signal out of the tuned circuit, the gain of the amplifier being controlled by a signal indicative of the difference between the amplitudes of the signals fed to the phase detector.

Abstract: An apparatus including means for providing at least five fixed internal frequency signals having five different values of frequencies in which all of said frequencies are coupled into a first processor stage comprised of a single pole double throw switch controlled by a first input bit command signal for selecting either of two of said five frequencies for coupling into a first frequency mixer. A third frequency signal is also coupled into the first frequency mixer which provides a first difference frequency output signal that is coupled into a second frequency mixer. The second frequency mixer is coupled to a second single pole double throw switch controlled by a second input bit command signal for selecting either of the fourth or the fifth of said five frequencies. The difference output signal of the second frequency mixer is coupled to a frequency divider capable of division by four.

Abstract: The invention relates to a circuit arrangement for producing a low frequency alternating current, such as is particularly used for electric massaging. Any desired frequency characteristics and beats may be produced by the interconnecting of several generators having different, adjustable fundamental frequencies, and by an adjustability of the coupling components. These frequency characteristics and beats have proven to be particularly effective. Above all, the components of the line frequencies of 50-60 Hz, which are dangerous to the human body, are avoided.

Abstract: A linear-moving type displacement detector has a movable electrode disposed between a pair of stationary electrodes such a manner that the electrodes are in parallel with one another, thus forming a pair of variable capacitors. The movable electrode is movable in a direction forming an angle with the stationary electrodes while being kept parallel with the stationary electrodes, so that one of the capacitances of the two capacitors is increased with the movement of the movable electrode, while the other is decreased, and vice versa. The capacitors are coupled to oscillators, the output frequencies of the oscillators are mixed in a mixer, to provide the difference frequency therebetween, or some analogous signal which is responsive to the difference frequency. The difference frequency or the analogous signal is utilized for displacement measurement.

Abstract: A sensor developing a digital output in response to force induced deflection in which the deflection is of a beam formed to have, under stress, a surface undulate in both compression and tension. The signal is developed from piezoelectric transducers connected in a pair of oscillator circuits utilizing surface acoustic wave paths through, respectively, the tension and the compression portions of the beam surface. The frequencies of the oscillators are compared and the frequency difference resulting from beam deflection is sent as a signal to a counter to give a digital read out of the force causing the deflection. The beam is formed of steel and the piezoelectric surface for the surface waves and the interdigitated conductors forming the transducers are deposited by thin film techniques on the beam.

Abstract: A frequency synthesizer, responsive to a reference signal having a frequency f.sub.r, for supplying an output signal at a frequency selectable from M times N signal frequencies (where M and N are preselected integers) is disclosed. In each disclosed arrangement, a set of M signals that are each harmonically related to f.sub.r is derived by a cascade connected harmonic generator and comb filter, and a set of M signals that are each harmonically related to f.sub.r /M is derived from the reference signal by a cascaded frequency divider, harmonic generator and comb filter. Each of these signal frequencies within the two sets of signals can be selectively coupled to the input ports of signal mixing apparatus and bandpass filtering is employed to couple either the mixer sum or difference frequency to the synthesizer output terminal. In some situations, a single mixer circuit and bandpass filter is employed.

Abstract: A quartz crystal thermometer in which a standard frequency is generated by a first oscillator circuit incorporating a quartz crystal element and in which a frequency which varies with temperature is generated by a second circuit incorporating the same quartz crystal element. Two electrode pairs are provided on the single quartz crystal element in order to excite two different modes of vibration of the quartz crystal element, with the metallization being on only one or on both of the major faces of the quartz crystal element. In accordance with preferred embodiments, an AT- or a BT-cut quartz crystal plate is utilized. The ratio of the said two frequencies provides an accurate measure of the temperature.

Abstract: A frequency synthesizer operating in the quaternary system of numeration and comprising a plurality of "quaternade" units, each including a frequency inserting element with a mixer which receives respective frequencies equal to 63 A, 64 A, 65 A and 66 A, A being a predetermined frequency. The said frequencies are generated from a common standard frequency through dividing the standard frequency by variable ratios generating harmonics of the resulting frequencies and filtering.