With Frequency Calibration Or Testing Patents (Class 331/44)
  • Patent number: 9479179
    Abstract: Methodologies and an apparatus for measuring setup and hold times of fabricated semiconductor devices are provided. Embodiments include: providing a first digital frequency divider having an input and an output, the input of the first digital frequency divider receiving a first signal indicating an oscillating signal with a first delay; providing a second digital frequency divider having an input and output, the input of the second digital frequency divider receiving a second signal indicating the oscillating signal with a second delay; and providing a flip-flop having an input and an output, wherein the input of the flip-flop is coupled to the output of the second digital frequency divider and a data signal and clock signal for measuring a set-up time or hold time of a device under test are generated.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Andy T. Nguyen, Navneet Jain
  • Patent number: 9455727
    Abstract: Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). in embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: September 27, 2016
    Assignee: Intel Corporation
    Inventors: Shenggao Li, Guluke Tong, Sujatha B. Gowder, Fulvio Spagna
  • Patent number: 9402342
    Abstract: A seed meter drive system includes a clutch having a toolless fastener configured to selectively couple the clutch to a downstream component. The clutch is configured to receive a rotational input via a flexible drive shaft, and to drive the downstream component in rotation while the clutch is engaged.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: August 2, 2016
    Assignee: CNH Industrial America LLC
    Inventors: Monte Weller, David Flamme, Scott Long, Marvin Prickel
  • Patent number: 9264052
    Abstract: A method and a circuit for implementing dynamic phase error correction for phase locked loop (PLL) circuits, and a design structure on which the subject circuit resides are provided. The circuit implements dynamic phase error correction and includes an adjustable delay line that is placed in either the reference or feedback clock path. The phase error correction circuit detects the propagation delay of the reference clock path from input pin to the phase frequency detector in the PLL. It also detects the propagation delay of the feedback clock path from input pin to the phase frequency detector in the PLL. The detected propagation delays are compared and a control signal is generated that is proportional to the mismatch. The control signal is applied to the adjustable delay line. The delay of the delay line is continually adjusted until the reference and feedback clock paths are balanced.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: February 16, 2016
    Assignee: International Business Machines Corporation
    Inventors: Grant P. Kesselring, Christopher W. Steffen, James D. Strom
  • Patent number: 9130576
    Abstract: One embodiment of communication system comprises a crystal oscillator configured to output a reference clock; cellular radio frequency (RF) and baseband phase locked loops configured to receive the reference clock within a cellular module and compensate for calculated frequency errors between a received cellular downlink signal and a cellular local oscillator signal during operation of the cellular module; global positioning system (GPS) frequency compensation circuitry configured to receive the reference clock within a GPS module and compensate for calculated frequency errors during operation of the GPS module; and a temperature sensing circuit which includes a plurality of sensing resistors and is configured to output a signal corresponding to a temperature of a reference crystal which is translated to a frequency deviation, wherein the (GPS) frequency compensation circuitry is configured to offset the frequency deviation and output a temperate compensated signal to meet GPS clock frequency requirements.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: September 8, 2015
    Assignee: BROADCOM CORPORATION
    Inventor: Rong He
  • Patent number: 9122938
    Abstract: A transmission leakage signal offset apparatus of a radio frequency identification (RFID) reader is disclosed. The transmission leakage signal offset apparatus may include a signal divider to divide a received signal of the RFID reader, the received signal including a transmission leakage signal, and to transmit the divided received signal to a signal combiner and an injection locked oscillator (ILO); a signal synchronizer to synchronize a phase of the ILO with a phase of the transmission leakage signal; a phase controller to control a phase difference between the received signal of the RFID reader and an output signal of the ILO; and a signal combiner to combine the received signal of the RFID reader and the output signal of the ILO, between which the phase difference is controlled.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: September 1, 2015
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Hoe Sung Yang, Sang Hyun Mo
  • Patent number: 9081515
    Abstract: A clock generation circuit includes a counting code generation unit configured to generate counting codes corresponding to a frequency of an input clock when an enable signal is enabled; a control code generation unit configured to decode the counting codes and generate control codes; and a cycle changeable oscillation unit configured to determine a frequency of an output clock in response to the control codes.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: July 14, 2015
    Assignee: SK Hynix Inc.
    Inventors: Jung Hwan Ji, Geun Il Lee
  • Patent number: 9077353
    Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency and calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency source. When a primary power source is unavailable, an output frequency is generated from the oscillator frequency, and the reference frequency source is powered-on only during calibration cycles.
    Type: Grant
    Filed: April 23, 2012
    Date of Patent: July 7, 2015
    Assignee: Silego Technology, Inc.
    Inventors: John Othniel McDonald, Crist Y. Lu, Ilbok Lee
  • Patent number: 9035705
    Abstract: An integrated oscillator circuit comprises an oscillator configured to be switched between a first frequency and a second frequency. A switching circuit receives an input representing a target frequency and switches the oscillator between the first and second frequencies at intervals determined by the input, so as to cause the average output frequency of the oscillator to approximate the target frequency.
    Type: Grant
    Filed: January 19, 2012
    Date of Patent: May 19, 2015
    Assignee: NORDIC SEMICONDUCTOR ASA
    Inventors: Ola Bruset, Tor Oyvind Vedal
  • Patent number: 9013240
    Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.
    Type: Grant
    Filed: March 1, 2014
    Date of Patent: April 21, 2015
    Assignee: Beken Corporation
    Inventors: Jiazhou Liu, Dawei Guo
  • Publication number: 20150102861
    Abstract: A method of determining an effective capacitance of a ring oscillator free of short current. The method comprises determining a frequency of an oscillator signal communicated from a ring oscillator to an inverter via a first communication path. The first communication path has connectivity to a first voltage source, a ground path and the inverter. The first communication path is divided into a second communication path and a third communication path. The method further comprises determining a voltage line current. The method additionally comprises determining an effective capacitance of the ring oscillator based on a first voltage of the first voltage source, the voltage line current and the frequency of the oscillator signal communicated to the inverter along the third communication path.
    Type: Application
    Filed: October 11, 2013
    Publication date: April 16, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, INC.
    Inventors: Chung-Peng HSIEH, Chung-Ting LU, Chung-Chieh YANG, Chih-Chiang CHANG
  • Patent number: 9000850
    Abstract: A method and an apparatus for self-calibration of a driving capability and a resistance of an on-die termination are provided. The apparatus includes an output interface physical layer (PHY) and a ring oscillator. The output interface PHY receives an operation voltage. The ring oscillator surrounds the output interface PHY to sense a work temperature or the operation voltage and accordingly outputs a sensing result. The driving capability or the resistance of the on-die termination of the output interface PHY is adjusted according to the sensing result.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: April 7, 2015
    Assignee: Novatek Microelectronics Corp.
    Inventors: Yao-Cheng Chuang, I-Huan Huang
  • Patent number: 9000856
    Abstract: A method and device for calibrating an oscillator and a temperature sensor in an electronic device are provided. A same temperature cycle, which includes at least two distinct temperatures, may be used to obtain data to calibrate both the oscillator and the temperature sensor. One of the distinct temperatures may comprise an ambient temperature, and a second distinct temperature may comprise a heated temperature greater than the ambient temperature. The electronic device (or a calibration device separate from the electronic device) may receive the readings from the oscillator and the temperature sensor at the two distinct temperatures in the same temperature cycle, and may determine an oscillator correction factor and a temperature sensor correction factor.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: April 7, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Deepak Pancholi, Bhavin Odedara
  • Patent number: 8994461
    Abstract: A cascaded oscillator array includes a first oscillator array and a second oscillator array. The first oscillator array includes at least three oscillator elements coupled unidirectionally in a first ring such that the first oscillator array outputs a first oscillating signal. Each of the at least three oscillator elements is coupled to receive a signal from a sensing element. The second oscillator array includes at least three oscillator elements coupled unidirectionally in a second ring such that the second oscillator array outputs a second oscillating signal. A first number of the at least three oscillator elements of the first oscillator array is the same as a second number of the at least three oscillator elements of the second oscillator. Each oscillator element of the at least three oscillator elements of the second oscillator array is coupled to receive an output signal from a single oscillator element of the at least three oscillator elements of the first oscillator.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: March 31, 2015
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Visarath In, Patrick Longhini, Yong (Andy) Kho, Antonio Palacios
  • Patent number: 8975970
    Abstract: A controlled oscillator is tuned to produce a desired, temperature independent frequency. A first frequency ratio is determined between a first frequency of the output signal generated by the controlled oscillator and a frequency of an output signal from another oscillator. The first frequency is determined based on a sensed temperature. A desired frequency of the output signal of the controlled oscillator is used to determine a desired frequency ratio between the desired frequency and the frequency of the output signal from the other oscillator. The controlled oscillator is tuned and the frequency ratio measured until the tuning has caused the desired frequency ratio to be achieved, thereby causing the controlled oscillator to provide the desired frequency.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: March 10, 2015
    Assignee: Silicon Laboratories Inc.
    Inventor: Jeffrey L. Sonntag
  • Patent number: 8963650
    Abstract: A semiconductor device contrived to prevent a reference voltage and a reference current which are supplied to a high speed OCO from varying with a change in ambient temperature and/or a change in an external power supply voltage and to reduce the circuit area of a power supply module. The high speed OCO outputs a high speed clock whose magnitude is determined by the reference current and the reference voltage. A logic unit adjusts the values of the reference current and reference voltage, according to the reference voltage and reference current trimming codes related to detected ambient temperature and operating voltage.
    Type: Grant
    Filed: August 9, 2012
    Date of Patent: February 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Tsukasa Oishi, Katsuyoshi Mitsui, Naoki Otani
  • Patent number: 8957736
    Abstract: The oscillation method uses an oscillation circuit in which a plurality of MOSFETs are annularly connected. The method comprises the steps of: forming GND of the circuit, which is separated from GND of a driving electric source of the MOSFETs, in a part of a first connection line which connects the MOSFET with the adjacent MOSFET; connecting a probe with a second connection line which connects another MOSFET with the adjacent MOSFET, an odd number of the MOSFETs being connected between the GND and the second connection line; and generating an oscillation waveform between the probe and the GND.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: February 17, 2015
    Inventor: Akira Takizawa
  • Publication number: 20150035610
    Abstract: A method in a circuit comprises providing a first clock by a resistor-capacitor (RC) oscillator; demodulating a plurality of input signals to form a plurality of demodulated input signals; discriminating frequency ranges of the plurality of demodulated input signals according to the first clock; determining whether a first predetermined number of consecutive demodulated input signals among the plurality of demodulated input signals fall into a first predetermined frequency range; triggering a crystal oscillator to provide a second clock to calibrate the first clock if the first predetermined number of consecutive input signals fall into the first predetermined frequency range.
    Type: Application
    Filed: March 1, 2014
    Publication date: February 5, 2015
    Applicant: BEKEN CORPORATION
    Inventors: Jiazhou Liu, Dawei Guo
  • Patent number: 8928418
    Abstract: Systems and methods for reducing process sensitivity in integrated circuit (“IC”) fabrication. An integrated circuit structure is provided that includes a first integrated circuit device having at least one parameter influenced by process variation in a first manner. The integrated circuit structure further includes a second integrated device having the least one parameter influenced by the process variation in a second manner. The first manner is opposite of the second manner. The second integrated device is configured to offset or reduce the influence of the process variation on the at least one parameter in the first integrated circuit device.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Herschel A. Ainspan, Anthony R. Bonaccio, Ramana M. Malladi
  • Patent number: 8924765
    Abstract: A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: December 30, 2014
    Assignee: Ambiq Micro, Inc.
    Inventor: Stephen Sheafor
  • Publication number: 20140361842
    Abstract: A dual-mode crystal oscillator includes a single AT-cut quartz crystal piece, a package, and an integrated circuit. The integrated circuit includes an oscillation circuit configured to cause the AT-cut quartz crystal piece to oscillate at a frequency in the MHz band, a dividing circuit configured to divide the frequency in the MHz band to generate a frequency of 32.768 kHz, a selection circuit configured to select one of a pause state where the frequency in the MHz band is not output and an active state where the frequency in the MHz band is output. The mounting surface includes three electrodes arranged in a direction along the long side and two electrodes arranged in a direction along the short side. The electrode to output the frequency of 32.768 kHz and the electrode to output the frequency in the MHz band are arranged not adjacent to one another.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 11, 2014
    Inventors: WEN JEN CHEN, CHISATO ISHIMARU
  • Patent number: 8903022
    Abstract: There is provided a solution for simultaneous reception of dual channel transmission. The solution is based on applying a first and a second oscillating signals, mixing and adding in order to separate the in-phase and quadrature components of first and second signals from a combined radio frequency signal received as input.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: December 2, 2014
    Assignee: Nokia Corporation
    Inventor: Risto Olavi Vaisanen
  • Patent number: 8884706
    Abstract: Embodiments of the invention include a method for use in a device having a local oscillator. The method includes performing, for the local oscillator that is disciplined by an external reference signal, while locked to the external reference signal, training at least two mathematical models of the oscillator to determine a predicted correction signal for each mathematical model based at least in part on a correction signal that is a function of the external reference signal and which is used to discipline drift in the oscillator. The method also includes selecting a mathematical model of the at least two mathematical models that results in a smallest time error when disciplining the oscillator to use when the external reference signal is unavailable and an alternative correction signal is to be used to discipline drift in the oscillator.
    Type: Grant
    Filed: March 25, 2011
    Date of Patent: November 11, 2014
    Assignee: BlackBerry Limited
    Inventors: Charles Nicholls, Philippe Wu
  • Patent number: 8878616
    Abstract: The described embodiments provide a configurable pulse generator circuit. More specifically, the described embodiments include a pulse generator circuit; an inverting difference oscillator (IDO) enabling circuit coupled to the pulse generator circuit; and a disable signal coupled to the IDO enabling circuit. When the disable signal is asserted, the IDO enabling circuit is disabled and the pulse generator circuit is configured as a pulse generator. In contrast, when the disable signal is deasserted, the IDO enabling circuit is enabled and the pulse generator circuit is configured as part of an IDO.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: November 4, 2014
    Assignee: Oracle International Corporation
    Inventors: Anand Dixit, Robert P. Masleid
  • Patent number: 8878615
    Abstract: The present application discloses a voltage-controlled oscillator device and a method of correcting the voltage-controlled oscillator. The voltage-controlled oscillator device comprises predistortion module, configured to predistort an input voltage to obtain a predistorted voltage; and a voltage-controlled oscillator, configured to generate an output signal with a corresponding oscillation frequency according to the predistorted voltage, wherein the predistortion module corrects a non-linear characteristic of the voltage-controlled oscillator, so that there is a linear relationship between the input voltage and the oscillation frequency of the output signal. The voltage-controlled oscillator device may be applied to a phase-locked circuit in a communication system.
    Type: Grant
    Filed: October 9, 2011
    Date of Patent: November 4, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Yuping Wu, Lan Chen
  • Patent number: 8872593
    Abstract: A technique for calibration of on-chip resistance (R) and capacitance (C) values using an on-board bypass capacitor may include configuring an on-chip switch to selectively couple an on-chip calibration circuit to an on-chip port. The on-chip calibration circuit may include an RC oscillator having an RC time constant (RCTC). The on-board bypass capacitor may be coupled to the on-chip calibration circuit, by using the on-chip port. The on-chip R and C values may be calibrated using the on-chip calibration circuit and the on-board bypass capacitor.
    Type: Grant
    Filed: January 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Mohyee Mikhemar, Hooman Darabi
  • Patent number: 8872523
    Abstract: Embodiments of the invention relate to automatic test equipment for testing a circuit having an oscillating crystal and to a method for operating such automatic test equipment. A generator generates a first signal comprising an oscillating part having at least one predetermined frequency. A first terminal couples the first signal to the oscillating crystal. At least one predetermined frequency is located inside a predetermined window around one of the resonance frequencies of the oscillating crystal. An analyzer has a second terminal coupled to the oscillating crystal for detecting a second signal and a rectifier connected in series with a low-pass filter for rectifying and filtering the second signal. A detector for detects a DC-signal at the output of the low-pass filter and for signals a valid test result for the oscillating crystal if the DC-signal exceeds a certain threshold value.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: October 28, 2014
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Ralf Sonnhueter, Anton Ecker
  • Publication number: 20140306771
    Abstract: A method for stabilizing the output frequency of an oscillator comprises providing a temperature model to capture the temperature characteristics of a second oscillator when measured by a first oscillator, measuring a value indicative of the frequency of the second oscillator by using the first oscillator, determine a temperature of the second oscillator based on the measured value indicative of the frequency of the second oscillator and the temperature model, determining a compensation amount for the frequency of the first oscillator from the determined temperature, and providing a compensated output frequency of the first oscillator as a stabilized output.
    Type: Application
    Filed: April 8, 2014
    Publication date: October 16, 2014
    Applicant: Dialog Semiconductor GmbH
    Inventor: Adam Malpass
  • Patent number: 8860478
    Abstract: The invention provides a phase-locked loop with loop gain calibration and methods for measuring an oscillator gain, gain calibration and jitter measurement for a phase-locked loop. The method for measuring an oscillator gain of a phase-locked loop includes the steps of providing a varying code at an input end of the oscillator; outputting excess reference phase information by a reference phase integral path and outputting excess feedback phase information based on the varying code by a feedback phase integral path; and obtaining an estimated gain information of the oscillator based on the excess reference phase information and the excess feedback phase information.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 14, 2014
    Assignee: National Chiao Tung University
    Inventors: Wei-Zen Chen, Shu-Chin Chuang
  • Patent number: 8847690
    Abstract: Aspects of the embodiments include a method for synchronizing a device having an oscillator to a reference signal. A correction signal can be determined based on the reference signal. A mathematical model of the oscillator can be trained based at least upon the correction signal. A predicted correction signal for the trained mathematical model can be determined. A time error using the predicted correction signal can be generated to assess suitability of the trained mathematical model for disciplining drift in the oscillator and synchronizing the device when the reference signal is not available.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: September 30, 2014
    Assignee: BlackBerry Limited
    Inventors: Charles Nicholls, Philippe Wu
  • Publication number: 20140266472
    Abstract: In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Jeffrey W. Waldrip, Yongping Fan, Jing Li
  • Patent number: 8830002
    Abstract: Apparatuses, methods, systems, algorithms, and circuits for reference clock frequency determination are disclosed. In one embodiment, a circuit for detecting a reference clock frequency can include a clock counter configured to count a number of cycles of the reference clock over a predetermined portion of a sleep clock to provide a reference clock cycle count, where the sleep clock has a known frequency and a predetermined accuracy; a frequency estimator configured to estimate the reference clock frequency from the reference clock cycle count and the known frequency of the sleep clock; and a frequency selector configured to select a closest frequency to the estimated reference clock frequency from a plurality of allowed frequencies.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: September 9, 2014
    Assignee: Marvell World Trade Ltd.
    Inventors: Ken Yeung, Hedley Rainnie
  • Patent number: 8816778
    Abstract: A method for adjusting an oscillator clock frequency, comprising: providing a first oscillator, applying a first setpoint value to the first oscillator, determining a first oscillator frequency value within a first time frame, providing a second oscillator, applying a second setpoint value to the second oscillator, determining a second oscillator frequency value within a second time frame, determining a new frequency setpoint value from the first and second frequency values, the first and second setpoint values, and a desired frequency value, and applying the new frequency setpoint value to one of the first and second oscillators.
    Type: Grant
    Filed: July 19, 2012
    Date of Patent: August 26, 2014
    Assignee: INSIDE Secure
    Inventors: Gaetan Bracmard, Jean-Pascal Maraninchi, Julien Roche
  • Patent number: 8816781
    Abstract: An all-digital frequency detector is provided, which includes a phase-frequency detector receiving a reference clock and an input clock, two sample/hold circuits sampling the phase-frequency detector outputs responsive to a ninety-degree phase shifted reference clock and a ninety-degree phase shifted input clock, a plurality of logical operators to generate an output frequency detection signal and a output clock responsive to the difference between the reference clock and the input clock.
    Type: Grant
    Filed: September 20, 2012
    Date of Patent: August 26, 2014
    Inventor: Phuong Huynh
  • Publication number: 20140232475
    Abstract: A highly integrated monolithic self-compensated oscillator (SCO) with high frequency stability versus temperature variations is described, together with a cost effective single insertion point trimming (SPT) algorithm. The SPT is utilized to adjust the phase and frequency of the SCO to meet frequency stability versus temperature and frequency accuracy requirements for a reference clock. The techniques used in the SPT algorithm provide a robust, fast and low testing cost for the SCO. Moreover, the concepts and techniques utilized in the SCO SPT can be used effectively for any temperature compensated oscillator (TCO) including TCXO, MEMS, FBAR and RC oscillators. Additionally, the described SPT algorithm is capable of measuring the temperature sensitivity of any oscillator, estimating suitable temperature compensation parameters and adjusting the oscillator frequency to the required value simultaneously.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 21, 2014
    Applicant: Si-Ware Systems
    Inventors: Ahmed Elkholy, Ayman Ahmed
  • Patent number: 8810321
    Abstract: An oscillator auto-trimming method is provided. The oscillator auto-trimming method includes receiving, by a subtractor, a first count result and second count result to output a difference between the first count result and the second count result as an offset frequency, receiving, by a divider, the offset frequency to output a divided signal corresponding to a result of dividing the offset frequency by a reference offset frequency output from a micro control unit, and receiving, by the micro control unit, the divided signal and determine whether to change an oscillator frequency.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: August 19, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Kwang Ho Choi
  • Patent number: 8787423
    Abstract: A system and method for frequency hopping precalibrates a subset of a plurality of channels, storing the channels' associated curves in a computer readable medium. Before hopping to a new channel, decision making circuitry can access the precalibrated curves. If the destination channel has an associated curve, then the system can use the values from that curve when hopping to a new channel. If the destination channel does not have an associated precalibrated curve, then the system can identify a closely situated channel with a precalibrated curve and use an offset value to settle at the destination channel. According to another aspect of the present invention, the offsets can be updated. According to a further aspect of the invention, the updated can be done dynamically.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: July 22, 2014
    Assignee: Marvell International Ltd.
    Inventors: Randy Tsang, Chun Geik Tan, Yui Lin, Meng Long
  • Patent number: 8786374
    Abstract: An error detection system employs a chain of delay elements connected in an open loop configuration. To determine whether the oscillator is operating within a specified set of parameters, the error detection system applies a start pulse to an input of the open-loop chain of delay elements. The error detection system compares the resulting output signal with the output of the oscillator. If the oscillator has locked onto a harmonic of the intended output frequency, the comparison of the output signals will indicate an error.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: July 22, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Jon S. Choy
  • Publication number: 20140176246
    Abstract: A resonator has a main resonator body and a secondary resonator structure. The resonator body has a desired mode of vibration of the resonator alone, and a parasitic mode of vibration, wherein the parasitic mode comprises vibration of the resonator body and the secondary resonator structure as a composite body. In this way, unwanted vibrational modes are quenched by the second suspended body.
    Type: Application
    Filed: September 23, 2013
    Publication date: June 26, 2014
    Applicant: NXP B.V.
    Inventors: Casper van der Avoort, Andreas Bernardus Maria Jansman, Robert James Pascoe Lander
  • Publication number: 20140167866
    Abstract: A calibrated crystal warm-up method that can include determining the number of clock cycles of a crystal clock reference signal from a crystal oscillator occur during a single clock cycle of a low-power oscillator. Further, the determination can occur when the crystal oscillator is warmed up. The method can also include comparing a number of clock cycles of the crystal clock reference signal with a previously determined number of clock cycles of the crystal clock reference signal to indicate whether the crystal oscillator is warmed up. Further, the method can include counting the number of clock cycles of a low-power clock reference signal have occurred up until the time it has been determined that the crystal oscillator has been warmed up.
    Type: Application
    Filed: December 14, 2012
    Publication date: June 19, 2014
    Applicant: Broadcom Corporation
    Inventors: Praveen VASISHTHA, Satyaprasad SRINIVAS
  • Patent number: 8754715
    Abstract: A semiconductor device includes a first oscillator that generates a first clock signal, a second oscillator that generates a second clock signal in response to the first clock signal, a third oscillator that generates a third clock signal, a counter that counts a signal corresponding to the first clock signal or a signal corresponding to the second clock signal during a predetermined period that is set based on the third clock signal to generate an overflow signal indicating that a count value of the signal corresponding to the first clock signal or the signal corresponding to the second clock signal exceeds a predetermined value, and an abnormality notice unit that receives the overflow signal to generate an abnormal signal indicating that an abnormal oscillation occurs in at least one of the first to third clock signals.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: June 17, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Masanori Honda
  • Patent number: 8742858
    Abstract: Techniques and architectures corresponding to relaxation oscillators having output frequencies that are supply voltage independent are described. In a particular embodiment, an apparatus includes a relaxation oscillator having one or more capacitors and a compensation current circuit coupled to the relaxation oscillator. The compensation current circuit is configured to regulate current provided to the one or more capacitors of the relaxation oscillator in response to changes in a supply voltage provided to the compensation current circuit and to the relaxation oscillator.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: June 3, 2014
    Assignee: Infineon Technologies AG
    Inventors: Roberto Nonis, Nicola DaDalt
  • Patent number: 8742863
    Abstract: A communication terminal includes a crystal oscillator, a transceiver and circuitry. The crystal oscillator belongs to a specified type in which a dependence of an output frequency on temperature has one or more temperature dependence coefficients. The transceiver is arranged to operate an AFC loop having an initial frequency accuracy requirement that is more stringent than an uncompensated frequency accuracy of the crystal oscillator. The circuitry is arranged to determine output frequencies of the crystal oscillator at respective operating temperatures, to compute the temperature dependence coefficients based on the output frequencies and operating temperatures, to correct a frequency error in the output frequency using the dependence and the temperature dependence coefficients, to ascertain that the corrected frequency error meets the initial frequency accuracy requirement, and to subsequently correct a frequency of the received signal using the AFC loop.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: June 3, 2014
    Assignee: Marvell International Ltd.
    Inventor: Alex Zaslavsky
  • Patent number: 8736388
    Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: May 27, 2014
    Assignee: Sand 9, Inc.
    Inventors: Klaus Juergen Schoepf, Reimund Rebel, Jan H. Kuypers
  • Patent number: 8729920
    Abstract: Circuits and methods are provided for a reliability, availability and serviceability (RAS) enabled and self-regulated frequency and delay sensor of a semiconductor. A circuit for measuring and compensating for time-dependent performance degradation of an integrated circuit, includes at least one critical functional path of the integrated circuit, and Wearout Isolation Registers (WIR's) connected to boundaries of the critical functional path. The circuit also includes a feedback path connected to the WIR's, and a sensor control module operable to disconnect the critical functional path from preceding and succeeding functional paths of the integrated circuit, connect the critical functional path to the feedback path to form a critical path ring oscillator (CPRO), and enable the CPRO to generate an operating signal. A delay sensor module is operable to measure a frequency of the operating signal to determine and compensate for a degradation of application performance over a lifetime of a semiconductor product.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: May 20, 2014
    Assignee: International Business Machines Corporation
    Inventors: Carole D. Graas, Keith A. Jenkins, Pascal A. Nsame, Kevin G. Stawiasz
  • Patent number: 8729968
    Abstract: A built-in self-test circuit for testing a voltage controlled oscillator comprises a voltage controlled oscillator, a buffer having an input coupled to an output of the voltage controlled oscillator and a radio frequency peak detector coupled to the output of the buffer. The radio frequency peak detector is configured to receive an ac signal from the voltage controlled oscillator and generate a dc value proportional to the ac signal at an output of the radio frequency peak detector. Furthermore, the output of the radio frequency peak detector generates a dc value proportional to an amplitude of the ac signal from the voltage controlled oscillator when the voltage controlled oscillator functions correctly. On the other hand, the output of the radio frequency peak detector is at zero volts when the voltage controlled oscillator fails to generate an ac signal.
    Type: Grant
    Filed: May 9, 2011
    Date of Patent: May 20, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsieh-Hung Hsieh, Ming Hsien Tsai, Tzu-Jin Yeh, Chewn-Pu Jou, Fu-Lung Hsueh
  • Publication number: 20140125419
    Abstract: An oscillator circuit generates a voltage signal. The magnitude of the voltage signal is measured and compared with predetermined upper and lower voltage signals by an internal test circuit. If the magnitude of the voltage signal is between the predetermined upper and lower voltage signals, then a pass test status signal is generated. If the magnitude of the voltage signal is not between the predetermined upper and lower voltage signals then a fail test status signal is generated.
    Type: Application
    Filed: January 15, 2014
    Publication date: May 8, 2014
    Inventors: Jun Zhang, Xiuqiang Xu
  • Patent number: 8704604
    Abstract: Systems and methods for operating with oscillators configured to produce an oscillating signal having an arbitrary frequency are described. The frequency of the oscillating signal may be shifted to remove its arbitrary nature by application of multiple tuning signals or values to the oscillator. Alternatively, the arbitrary frequency may be accommodated by adjusting operation one or more components of a circuit receiving the oscillating signal.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: April 22, 2014
    Assignee: Sand 9, Inc.
    Inventors: Klaus Juergen Schoepf, Reimund Rebel, Jan H. Kuypers
  • Patent number: 8698567
    Abstract: In a phase-locked loop (PLL) calibration system and method, the PLL input reference clock is phase-modulated, the resulting PLL output modulation is measured, and PLL calibration signals, such as a PLL proportional path adjustment signal and a PLL integral path adjustment signal, are derived from the measured PLL output modulation.
    Type: Grant
    Filed: April 2, 2012
    Date of Patent: April 15, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Robert Thelen, Michael Farmer, Robert K. Barnes
  • Patent number: 8698568
    Abstract: An automatic self-calibrated oscillation method and an apparatus using the same are provided. After a static time tuning (STT) table and a run time tuning (RTT) table have been established, the apparatus converts an output clock signal to generate a current RTT value at every predefined time and then compares the current RTT value with a reference RTT value generated in response to a STT value of the STT table, or with an interpolated result generated in response to the reference RTT value to generate a deviation value. Thus, through the deviation value, the output clock signal may be calibrated to address the target frequency without the assistance of external reference clock unit or locked loop unit after the STT table and the RTT table are established.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: April 15, 2014
    Assignee: Silicon Integrated Systems Corp.
    Inventors: Song Sheng Lin, Chia-Yi Chu