Abstract: Several calibration techniques for a precision relaxation oscillator with temperature compensation produces a stable clock frequency over wide variations of ambient temperature. The calibration techniques provide for different methods of determining CTAT current, PTAT current or the ratio of PTAT current to CTAT current. The calibration techniques provide different methods for determining CTAT and PTAT calibration values and for setting CTAT and PTAT calibration select switches.

Abstract: An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number, M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.

Abstract: An electrical circuit having an oscillator and additional structural elements that are connected to the oscillator. In an iterative method, upon variation of circuit parameters of the additional structural elements, the following steps are carried out for each instance of the circuit parameters: a stability analysis of the circuit is carried out for each respective instance, and if the circuit oscillates, a first value is assigned to the instance in a matrix in which all the instances being examined are stored. Otherwise, a second value is assigned to the instance in the matrix.

Abstract: In the path from the output of a charging pump to a control voltage terminal including the inside of a loop filter, voltage application means for applying a direct-current voltage of a predictable value to the control voltage terminal is given, resulting in a PLL circuit. In the PLL circuit, first, a fixed direct-current voltage is applied to the control voltage terminal from the voltage application means. The oscillation frequency of a voltage-controlled oscillator may be adjusted by making use of a trimming area as a oscillation frequency adjustment mechanism. Therefore, the oscillation frequency of the voltage-controlled oscillator can be quickly adjusted using fewer pieces of equipment.

Abstract: An apparatus comprising a control circuit and a first circuit. The first circuit may be configured to generate a calibration signal in response to an adjustment signal and a first control signal. The control circuit may be configured to generate (i) the first control signal, (ii) a second control signal and (iii) the adjustment signal in response to a rate of an input signal.

Abstract: A method and apparatus for digitally controlling the capacitance of an integrated circuit device using MOS-FET devices. In accordance with one aspect of the present invention, a one-bit or “binary” varactor is presented wherein the gate-to-bulk capacitance of the MOS-FET device exhibits dependency to a D.C. voltage applied between its gate and well implant regions. The capacitance-voltage characteristic of the binary capacitor has three major regions: (1) a first relatively flat region having little or no voltage dependency and having a capacitance equal to a first low capacitance of C1; (2) a sloped region wherein a voltage dependency exists; and (3) a second relatively flat region where there is little or no voltage dependency and where the capacitance equals a second higher capacitance of C2. The capacitance of the binary capacitor can be changed from C1 to C2 simply by changing the polarity of the applied D.C. voltage from a positive to a negative value.

Abstract: A method of evaluating quality of a crystal unit, capable of performing quantitative measurement of an actual operation of a crystal unit which is to be oscillated in an actual oscillator to ensure an accurate quality evaluation, is provided which comprises the steps of increasing a DC input voltage of a crystal oscillator, said crystal oscillator having at least one AGC amplifier whose amplification rate varies depending on the DC input voltage and having a crystal unit connected thereto; measuring a maximum value of the DC input voltage at a start of oscillation of the crystal oscillator; and evaluating quality of the crystal unit by the measured maximum value.

Abstract: A phase-locked loop (PLL) is provided, which includes a PLL reference input, a PLL output and a phase detection loop coupled between the PLL reference input and the PLL output. The phase detection loop has a loop filter node. A delay element is coupled within the phase detection loop and has a variable delay, which can be increased to a critical delay at which the phase detection loop becomes unstable. A demodulator is coupled to the loop filter node and is adapted to demodulate a modulated voltage on the loop filter node. The demodulator has a demodulated output, which is representative of a phase margin of the phase detection loop when the delay element has the critical delay.

Abstract: A YIG oscillator is provided having a YIG sphere magnetically coupled to a permanent magnet, a field straightener, and a ferromagnetic ring. The field straightener is attached to the permanent magnet and has a predetermined circumference. The ferromagnetic ring is configured to fit around the predetermined circumference of the field straightener. The ferromagnetic ring fine-tunes the magnetic field combination of the permanent magnetic and the field straightener. A coupling loop is configured to transceive resonance signals to and from the YIG sphere.

Abstract: A method is disclosed for calibrating the oscillation frequency versus control voltage characteristic of a voltage controlled oscillator (VCO). The method includes establishing an oscillation frequency of the VCO at a maximum target frequency value ft_H (point Q) when the control voltage Vc equals a predetermined reference voltage Vref which lies within the operating range of the control voltage Vc, and verifying that the oscillation frequency becomes a minimum target frequency value ft_L when the control voltage Vc is changed to a value between the minimum value Vclamp_L and the reference voltage Vref. An automatically calibrated PLL circuit including a VCO is disclosed which performs a calibration to set the oscillation frequency versus control voltage characteristic of the VCO.

Abstract: An oscillator circuit having a first programmable divider for obtaining a reference signal by dividing the frequency of an oscillation signal of a piezoelectric resonator by a frequency dividing number M. A PLL circuit using the reference signal as input thereto to obtain a multiplied signal, the multiplied signal being formed by multiplying the input signal by a second frequency dividing number N for a second programmable divider provided in a feedback circuit. A third programmable divider capable of dividing the frequency of the multiplied signal by a third frequency dividing number X and outputting the frequency-divided signal. The frequency dividing numbers M, N, and X can be set to values independent of each other. Therefore, innumerable combinations of the frequency dividing numbers M, N, and X can be used and the number of frequencies producible by one oscillator can be largely increased by enabling selection of any suitable one of such combinations.

Abstract: A method for centering the frequency of an injection locked oscillator or (ILO) includes producing measurements of the magnitude and sign of the phase difference between ILO output signals in response to alternate high level and low level RF drive signals, and tuning the center frequency of the ILO in accordance with the measurements to minimize the phase difference.

Abstract: A C-R oscillator generates a clock signal at a predetermined frequency determined by a capacitor and a resistor, and a test circuit is connected between the C-R oscillator and a pair of signal terminals for outputting the clock signal; when external control signals are supplied to the test circuit, the test circuit isolates the pair of signal terminals from the C-R oscillator, and checks the clock signal to see whether or not the duty factor of the clock signal falls within a target range so that an external testing apparatus easily diagnoses the C-R oscillator for not only the generation of the clock signal but also the duty factor.

Abstract: An improved oscillator test structure is disclosed. A structure according to one embodiment includes an odd plurality of first transistor pairs formed on a predetermined area of a semiconductor substrate. The transistor pairs are electrically connected in a serial ring. The structure also includes at least one second transistor pair, also formed within the predetermined area on the substrate, but electrically isolated from the odd plurality of first transistor pairs.

Abstract: A phase-locked loop bandwidth is tuned to a desired level by operating the phase-locked loop in a phase-locked condition at a first frequency and applying a step response to the phase-locked loop by causing the phase-locked loop to begin locking to a second frequency that is different from the first frequency. A parameter is then detected that is related to the applied step response and that is indicative of whether the phase-locked loop bandwidth is at the desired level. The phase-locked loop bandwidth is adjusted, and the steps of operating at the first frequency, applying the step response, detecting the parameter and adjusting the phase-locked loop bandwidth are repeated until the phase-locked loop bandwidth is at the desired level. Where the desired bandwidth level for tuning is not the operational bandwidth, the phase-locked loop bandwidth is further adjusted by a predetermined amount, thereby tuning the phase-locked loop bandwidth to an operational level.

Abstract: The invention relates to a device and process for data transmission. The data is transmitted by changes in the field strength of an electromagnetic or magnetic field, and then the times between at least two sequential field strength changes are evaluated. A frequency serving as the time base for evaluating the times between the field strength changes is calibrated at least at the beginning of data transmission so that it has a set relationship to the cycle duration of the field strength changes.

Abstract: The frequency of a quartz oscillator having a trimmer 2, a quartz oscillator 3 on which its temperature characteristic is printed in the form of a bar code 6, and a storage device 4 is adjusted to a predetermined frequency, and the temperature at that time is measured by a noncontact temperature sensor of a frequency adjusting device 10, and is written into the storage device 4. The temperature characteristic of the quartz oscillator is read by a bar code reader 21, and optimally suited temperature compensating data is selected from among a plurality of pieces of temperature compensating data stored in advance in a temperature-compensating-data writing device. Further, a frequency deviation between the temperature at the time of adjustment and a standard temperature is calculated, and the temperature compensating data including that frequency deviation is stored in the storage device 4.

Abstract: In a method of calibration of a voltage controlled oscillator (VCO), the VCO (100) provides an output signal which is used to drive a dividing oscillator (10) such as a relaxation oscillator (RO). The RO has at least two states, one in which the RO provides an output signal which has a first frequency that is related to the VCO output signal by a first ratio (e.g. 1/N) and one in which the relaxation oscillator provides a RO output signal which has a second frequency that is related to the VCO output signal by a second ratio (e.g. 1/(N+1)). By measuring the first and second frequencies (and knowing the relationship between the first and second ratios), the VCO frequency is calculated and stored (110). Several VCO frequencies can be calculated and stored for several applied voltages. As a result the VCO can be driven to any selected frequency in the calibrated range and can be used to provide an injection frequency for a radio.

Abstract: An integrated RC oscillator circuit includes a reference voltage generator, a fine tuner, a charging/discharging oscillator, a frequency counter, and a comparator. The reference voltage generator generates stable reference voltages Vref, Vref 1 to Vref 31, 3/4Vref and 1/2Vref. The fine tuner receives as inputs a reset signal, Vref and Vref 1 to Vref 31 and outputs a reference voltage PVref (0<P<1). The charging/discharging oscillator receives as inputs an enable signal, PVref, Vref, 3/4Vref and 1/2Vref and outputs a square wave signal whose frequency is determined by a resistor, a capacitor and the value of P. The frequency counter receives as inputs the reset signal, a timing reference clock and the square wave signal, it counts the frequency of the square wave signal and outputs the frequency value, and it also outputs a PROGRAM signal to the fine tuner.

Abstract: A method (100) for mechanically tuning a VCO that has a resonant stripline having vias in predetermined locations connected through a circuit board to ground. This includes a step (104) of measuring the operating frequency of the VCO. A following step (106) includes calculating an amount of frequency shift needed to achieve a desired frequency. A following step (108) matches the amount of frequency shift needed to values in a look-up table of frequency shifts versus via locations to determine which vias locations will provide the proper amount of frequency shift. A last step (110) includes mechanically disconnecting from ground the via locations indicated in the third step such that the desired frequency is achieved. This method (100) of tuning allows VCO frequency adjustment after final assembly avoiding problems of frequency shifts that can occur due to the placement of a metal lid on the circuit board after assembly.

Abstract: In a preferred embodiment, a gain control circuit employs variable gain circuitry and a variable frequency converter, both controlled by a processor. The processor controls the carrier frequency of an RF modulated output signal of the circuit by controlling the frequency converter. The processor also preferably controls the gain of the variable gain circuitry as a function of both the output carrier frequency and temperature, as measured by a temperature sensing element. Preferably, the gain is controlled to maintain a constant gain over specified operating frequency and temperature ranges. The gain control circuit can be employed within a transceiver of a wireless communication terminal. Similar gain control circuitry can be utilized within a base station transceiver in which frequency channels are dynamically allocable among a plurality of gain-controlled amplification circuits.

Abstract: A phase locked loop in a LSI comprises a phase comparator, a low-pass filter, a voltage controlled oscillator and a frequency divider, and receives an input clock signal to output an internal clock signal obtained by multiplication of the input clock signal. The output of the low-pass filter is supplied through a voltage follower from an external pin toward outside the integrated circuit. The output voltage of the low-pass filter is evaluated during a test mode for evaluating the function of the phase locked loop without affecting the characteristics of the phase locked loop.

Abstract: A crystal oscillator for measuring crystal impedance (CI) easily and accurately of various crystal units having an oscillating frequency in a wide band and various CI-values in a broad rage. A DC input voltage is measured, representing CI of a crystal unit, in a crystal oscillator, wherein an integrating circuit is provided in an output section providing a frequency oscillated from the crystal unit as an output, and one or more AGC amplifiers having an amplification rate proportional to a DC input voltage is provided between the crystal unit and the integrating circuit.

Abstract: A method (100) for tuning a voltage controlled oscillator by changing electrical circuit parasitics includes a first step (102) of providing a voltage controlled oscillator circuit on a circuit board and a plurality of different metal lids each having different numbers, sizes and locations of holes. Each different lid presents a different electrical circuit parasitic to the voltage controlled oscillator. In a second step (104), the voltage controlled oscillator frequency is measured, and the frequency shift needed to achieve a desired operating frequency is calculated in a third step (106). In a fourth step (108), a lid is chosen that will present the parasitics needed to provide the amount of frequency shift needed. As a last step (110), the chosen lid is attaching to the circuit board to obtain the desired nominal operating frequency from the voltage controlled oscillator.

Abstract: A fractional-N phase-lock loop (PLL) with a delay line loop (DLL) having a self-calibrating fractional delay element which controls the PLL feedback signal in such a manner that the delay intervals for the feedback signal are: increased when small fractional divisors (<1/2) causing a lagging phase relationship or large fractional divisors (>1/2) causing a leading phase relationship are sensed; and decreased when small fractional divisors (<1/2) causing a leading phase relationship or large fractional divisors (>1/2) causing a lagging phase relationship are sensed.

Abstract: A voltage controlled oscillator with bias current calibration includes a voltage controlled oscillator 1504. A tuning current source 1510 is coupled to oscillator 1504 in parallel with bias current source 1512 for providing a tuning current to oscillator 1504. A selected control voltage is provided by oscillator 1504 for setting an oscillator output frequency. Control circuitry 1513, 1514 allows adjusting of the tuning current source to optimize bias current.

Abstract: A VCO (Voltage Controlled Oscillator) (10) operates in a phase-locked loop at a desired frequency. One input to the VCO is a variable control signal (24) that holds the VCO at the desired frequency. Another input is a bias input (40) that changes the operating point of a transistor (34) in the VCO and also tends to change the VCO's frequency. The value of the variable control signal (24) is sensed while the bias input (40) is changed until a desired, minimum value of the control signal is sensed. The value of the bias input at that point is held constant while operating the VCO at the desired frequency and with minimal side band noise.

Abstract: A method and system are provided for calibrating a batch of devices each containing a circuit which is responsive to a control signal for producing a desired output which varies in accordance with a first predetermined function of a specific ambient condition, the control signal having a magnitude which varies as a second predetermined function of the specific ambient condition, the second function being based on data stored as a look-up table in a memory of the device and which must be individually calibrated for each device. In a preferred embodiment, the device is a digital temperature controlled crystal oscillator which produces a desired output frequency and includes a voltage controlled oscillator (VCO) responsive to a control signal having a magnitude which varies as a predetermined function of ambient temperature in order to compensate for temperature variations in the oscillator output frequency.

Abstract: An ASIC includes a PLL and digital circuitry to quantize and measure phase and average maximum jitter between a system clock input to the PLL, and a PLL-generated clock signal. The system clock is input to a series-string of delay elements, each contributing a delay of about 1.DELTA.t. Each delay element is associated with a two-input logic element, such as an EX-OR gate or an EX-NOR gate. One input to each two-input logic element is a version of the PLL-generated clock delayed by about (N/2) .DELTA.t. The second input to the first EX-OR is the output from the first delay element, the second input to the first EX-NOR is the output from the second delay element, and so on. Whichever delay element outputs a signal most closely in phase with the delayed PLL-generated clock will have an associated two-input logic element signal with a minimum duty cycle. Each two-input logic element output signal is capacitor integrated, sampled, stored and digitized.

Abstract: A monolithic high frequency voltage controlled oscillator trimming circuit includes a plurality of capacitance loops selectively connected between a first and second differential input of a voltage oscillator active network. A plurality of diodes, connected in series with the respective plurality of capacitance loops, selectively connect respective capacitance loops between the first and second differential input when forward biased. In a similar fashion, the plurality of diodes selectively disconnect the respective capacitance loops from the first and second differential input when reverse biased. A controller applies a forward biasing voltage to the diode of the selected capacitance loop to connect the capacitance loop to the active network of the voltage controlled oscillator and applies a reverse biasing voltage to the diode of the selected capacitance loop to disconnect the capacitance loop from the active network.

Abstract: Apparatus, and an associated method, for calibrating a device responsive to values of a reference signal. The reference signal may be subject to short-term disturbances. In one implementation, a cellular radio base station utilizes a Stratum-2 oscillator to which to phase-lock a base station VCO. Compensation is made for the aging of the Stratum-2 oscillator, thereby to provide a regulation signal causing the VCO to exhibit acceptable short-term and long-term frequency stability characteristics.

Abstract: The invention relates to a digitally adjustable crystal oscillator having a quartz crystal and a monolithic integrated oscillator circuit including a series combination of a first frequency-adjusting capacitor C1 and a second frequency-adjusting capacitor C2 connected in parallel with the quartz crystal and comprising parallel-connected first capacitance stages and parallel-connected second capacitance stages, respectively, and an inverter circuit connected in parallel with the quartz crystal and comprising a feedback resistor R.sub.K, the output of the innverter circuit being connected to a load resistor. The inverter circuit comprises parallel-connected inverter stages, and switching elements are provided within the inverter stages and cqapacitor stages in such a way that a respective one of the inverter stages as well as a first capacitance stage C.sub.1i and a second capacitance stage C.sub.2i are switchable into or out of circuit by means of a control signal I.sub.i.

Abstract: A microcontroller circuit having firmware selectable oscillator trimming includes, in combination, a microcontroller, an oscillator located within the microcontroller for providing a system clock signal for the microcontroller, and a memory portion for providing trimming data to the oscillator for trimming frequency of the system clock. The microcontroller circuit includes microcontroller logic which has the trimming data stored therein for transfer to the memory portion. Additionally, the microcontroller logic permits the user to alter the trimming data after it has been transferred to the memory portion, thereby permitting the user to alter the amount of modification of the system clock frequency from the amount associated with the trimming data.

Abstract: A temperature compensation apparatus for an oscillator includes an oscillator having an output for generating a clock signal with a frequency identical to the oscillating frequency of the oscillator, a memory for storing a frequency compensation lookup table based on the relationship between output frequencies of the oscillator and the environmental temperature variations, a temperature detector for detecting the environmental temperature variations, a central processing unit for selecting a rating output frequency of the oscillator, acquiring a frequency compensation value from the frequency compensation lookup table stored in the memory in response to a detected environmental temperature, and converting the frequency compensation value into a corresponding compensation signal, and a compensation circuit receiving an output signal of the oscillator and a compensation signal from the CPU for compensating a deviation between the output frequency of the oscillator and the rating frequency and outputting a frequ

Abstract: The invention is related to an electrically tunable voltage-controlled oscillatory circuit, wherein the negative bias voltage (-Vcf) of a capacitance diode (5) needed for tuning the center frequency of the oscillatory circuit is generated on the basis of an electric oscillating signal (RFout) produced by the oscillatory circuit itself. Said oscillating signal is used for generating a negative voltage with a clamp/voltage multiplier type circuit (15) and it is adjusted to a desired value with an adjustment circuit (14), in which the values of the components (R2) can be permanently adjusted suitable in the tuning stage. Alternatively, the adjustment circuit (14) may include an active component (Q1) which can have an effect on the value of the negative bias voltage (-Vcf) during the use of the oscillatory circuit.

Abstract: The present invention provides a semiconductor device wherein the oscillation of a clock signal oscillation circuit is halted by control carried out by a CPU when a clock-signal switching circuit selects either a clock signal generated by a CR oscillation circuit or a clock signal generated by an oscillator-driven oscillation circuit. A frequency divider divides the frequency of a clock signal generated by the clock signal oscillation circuit, supplying a clock signal with a divided frequency to the clock-signal switching circuit.

Abstract: A microwave frequency generator and method of generating a predetermined microwave signal. The invention comprises oscillator means to generate a determinable frequency signal and means responsive to the frequency signal received from the oscillator means to generate a predetermined Intermediate Frequency (IF) signal. The invention further includes means to generate a determinable ultrahigh frequency (UHF) signal, along with means responsive to the IF signal and to a UHF signal to generate a resultant frequency signal. Means responsive to the resultant frequency and to the predetermined frequency signal generated by the oscillator means are further provided to generate the desired predetermined microwave frequency signal.

Abstract: A clock recovery phase locked loop system is described. One embodiment has a voltage controlled oscillator divider (the signal of which is compared with a REFCLK divider signal), a voltage stimulus input where a test voltage is applied, a time stimulus input where a digital input with appropriate pulse width is applied and a monitor (output) where the results of the measurement can be observed. A test system is included which applies a series of analog voltages to the voltage stimulus input. For each analog voltage, the test system apply a series of pulses to the time stimulus input. By monitoring (a) the level on the monitor output and (b) the time at which it switches, the VCO gain can be calculated. This allows a direct measurement of VCO gain (K.sub.v) using conventional automatic test equipment used to test digital logic or memory devices.

Abstract: A PLL circuit (401), including a VCO (420) having a trimming port (418) and a tuning port (416), a PLL controller (404), a variable voltage source (408), a voltage measuring circuit (426) and a multiplexer (412, 414, 428), performs automatic trimming of the VCO (420). The PLL circuit (401) accomplishes this by initiating a trimming mode that controls the multiplexer so that it couples the output of the PLL controller (404) to the trimming port (418), and the output of the variable voltage source (408) to the tuning port (416), thereby to phase lock the VCO (420) to the reference frequency signal (421). The PLL circuit (401) then measures, by way of the voltage measuring circuit (426), a voltage at the trimming port (418), switches the PLL circuit (401) to an operational mode, and then adjusts the variable voltage source (408) to be substantially equal to the voltage measured.

Abstract: A temperature compensation circuit (10) for a crystal oscillator programmed by a single component (12), such as a resistor. The component (12) provides a voltage to an A/D converter (26). The digital signals (28) from the A/D converter (26) are divided and directed to separate signal generators (44,46,48,50,56) which control different aspects of the temperature compensation circuit (10). These aspects include a hot, cold, linear, balance and warp adjustment. The temperature compensation circuit (10) drives a varactor (18) which reactively loads a crystal oscillator (14) to compensate frequency over temperature. By using a single component (12) to program the circuit (10), an EEPROM is no longer needed which saves IC space and reduces IC processing steps, and the use of multiple external components to perform a compensation is avoided which further saves physical space.

Abstract: A method for selecting fundamental clock frequencies in order to achieve electromagnetic compatibility in electronic products which employ a plurality of clocks. The method require first selecting an ideal frequency for each clock in the product. Then, and until the goal of avoiding coinciding harmonics is complete, the method includes the steps of computing all harmonics of all clock frequencies chosen, determining a minimum difference tolerable in the chosen frequencies and their harmonics for sufficient minimization of electromagnetic interference, and determining if the harmonics of the chosen frequencies coincide impermissibly within the frequency range. If there exists coincidence of harmonics within the predetermined minimum range, then the fundamental frequency of at least one of the clocks corresponding to an interfering harmonic must be adjusted to eliminate the interference.

Abstract: A system for self-calibrating a clock of a communication terminal for use with communication systems in which a central communication node generates time base correction signals for the terminal clock includes a terminal oscillator which generates an oscillator frequency that includes an error amount. An oscillator calibration filter generates a frequency error estimate amount. Circuitry is provided for subtracting the frequency error estimate amount generated by the calibration filter from the oscillator frequency error amount. Circuitry is provided for applying the time base correction signals to the calibration filter to thereby modify the frequency error estimate amount generated by the calibration filter based upon the time base correction signals generated by the communication central node.

Abstract: A frequency synthesizer having two atomic frequency standard inputs that is adapted to provide seamless switching or transition between the atomic frequency standard inputs with no change in the synthesizer output phase and frequency. The synthesizer includes a multichannel phase comparison system, each channel adapted for handling an atomic frequency standard input, a digital phase lock loop, a digital to analog converter, and a voltage controlled crystal oscillator which provides the synthesizer output. The phase comparison system is adapted to continually monitor the integrity of the atomic frequency standard inputs and to continually estimate the phase differences between the two atomic frequency standard inputs. The phase difference is used to estimate the proper phase and frequency offset between the primary and secondary inputs.

Abstract: Calibration systems and techniques for analog phase-lock loops (PLLs) providing the capability to dynamically maintain a constant damping factor. Damping factor is calibrated by automatically setting a reference bias current I.sub.r to the PLL's charge pump such that the charge current I.sub.c output therefrom maintains the desired PLL damping characteristic. The technique presented involves selecting a known first frequency F.sub.1 and allowing the PLL circuit to reach steady state, after which a known second frequency F.sub.2 is applied and the PLL circuit is monitored to determine whether steady state at this second frequency F.sub.2 is accomplished within a predetermined target time T.sub.x, which corresponds to the desired damping factor. The determination of whether lock occurs within the target time T.sub.x is then employed to automatically setting the reference current I.sub.r.

Abstract: A clock overdrive function is provided which advantageously facilitates testing of circuits incorporating timing circuits. The clock overdrive function allows a tester to furnish a clock pulse timing reference to drive a circuit containing a system clock, thereby overdriving the system clock signal. Overdriving of the system clock signal allows precise control of circuit timing. A method of overdriving a system clock signal includes the steps of forming a low reference voltage and a high reference voltage, applying a timing signal having a timing signal voltage at an external pin, comparing the timing signal voltage at the external pin to the low reference voltage and the high reference voltage, driving the circuit with the system clock timing signal when the timing signal voltage at the external pin is less than the low reference voltage and driving the circuit with the timing signal at the external pin, otherwise.

Abstract: A frequency standard generator includes a voltage controlled crystal oscillator for generating high stability output signal to be used as a standard frequency signal, a satellite wave receiver which receives a radio wave from a satellite which includes a highly accurate satellite time signal and reproduces the satellite time signal to be used as a reference for the voltage controlled crystal oscillator, a frequency divider which divides the output signal of the voltage controlled crystal oscillator by a dividing ratio arranged to generate a crystal time signal which is identical in frequency to the satellite time signal, a time interval measuring circuit which measures a time interval which is a phase difference between the satellite time signal and the crystal time signal and generates a digital signal indicating the phase difference, a frequency control processor which arithmetically determines control data based on the digital signal from the time interval measuring circuit such that the phase difference m

Abstract: A component detector circuit operates to detect the presence or absence of a circuit component, such as an external component. A resistor detecting circuit includes a biasing circuit connected to the resistor. The biasing circuit generating a bias current. The resistor detecting circuit also includes a bias current threshold detector connected to the biasing circuit and a circuit connected to the bias current threshold detector which generates a signal indicative that the bias current is lower than threshold. A capacitor detecting circuit includes a circuit connected to a resistor and configured to be connected to a capacitor which establishes a time constant proportional to an RC product of the resistor and capacitor.

Abstract: A digital trimming circuit is used to produce a stable time reference signal. This type of reference time signal can be used in equipment, such as watches, which have motors and acoustic outputs that interfere with producing the time reference signal. A basic oscillation frequency, which is produced by an oscillator circuit, is frequency divided to form the generic time reference signal. The digital trimming circuit generates a control signal to shorten the period of the time reference signal by predetermined amounts based on correction data. The control signal is in the form of pulses which can be dispersively applied to create substantially equal intervals between pulses during one time period of the time reference time signal. While maintaining the necessary digital trimming amount in one digital trimming time period, an expansion/reduction amount of the time reference signal is suppressed at one digital trimming time instant.

Abstract: A communication system providing read and write access to analog and digitally controlled calibration and configuration information contained within prepackaged crystal oscillators having a crystal oscillator electrical interface with power (VCC), ground (GND), output enable (OE), and oscillator output (XO) interface pins. An output enable (OE) signal is used to control the activity state of the crystal oscillator output, with a pullup MOSFET connected to the XO pin to detect a logic low level at the XO pin during times when the OE signal is logically inactive. A state machine controls access to a serial shift register having multiple calibration and configuration bits. The calibration and configuration bits are used in performing an oscillator specific calibration and configuration function. The state machine also controls the reads and writes of the calibration and configuration shift register.