Abstract: A delay unit having a complementary architecture for use in a voltage control oscillator includes a first voltage control oscillating circuit and a second voltage control oscillating circuit. The first voltage control oscillating circuit includes a first gain circuit, a first current-source circuit coupled to the first gain circuit, and a first load circuit. The second voltage control oscillator circuit includes a second gain circuit, a second current-source circuit coupled to the second gain circuit, and a second load circuit. At least one pair of the first and second gain circuits, the first and second current-source circuits and the first and second load circuits are implemented with complementary integrated circuits.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation-frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: Distributed traveling wave oscillator circuitry is disclosed. The oscillator circuitry includes a signal path, a plurality of active switching means, and a direction promoting means. The signal path is formed from a pair of adjacent conductors and exhibits endless electric or magnetic continuity. The signal path also includes a portion that creates a signal phase inversion which sets half-cycles of oscillation to be the time of a single traverse of the signal path by the signal. The plurality of active switching means is connected between the adjacent conductors of the signal path for setting rise and fall times of each said half-cycle of oscillation. The direction promoting means establishes the direction of the traveling wave on the signal path.

Abstract: A sampling clock generator circuit comprises a ring oscillator including series-connected m first inverters connected to a first power supply line, where m is an odd number equal to or larger than 3, a delay line including series-connected 2m or 2m?1 second inverters connected to a second power supply line, for delaying an externally supplied clock, and a PLL circuit for controlling an oscillation frequency of the ring oscillator by controlling a voltage of the first power supply line by using the ring oscillator as a voltage controlled oscillation circuit. A voltage of the second power supply line is set substantially equal to the voltage of the first power supply line and the delayed clock obtained by the second inverters is used as a sampling clock.

Abstract: A voltage-controlled oscillator includes a bias circuit and a delay circuit. The bias circuit may generate a bias voltage signal pair having levels that are based on the voltage level of an input voltage signal and that are constrained by the values of a maximum current signal and a minimum current signal that are generated in the bias circuit. The delay circuit generates an output signal having a frequency that varies in response to the bias voltage signal pair. Because an operating frequency range of a voltage-controlled oscillator VCO is limited by a bias circuit, the VCO can operate with reduced gain and can limit the maximum operating frequency to a predetermined level. The VCO may also include a PTAT current generator in the bias circuit which can allow the VCO to compensate for variations of the VCO output frequency based on temperature.

Abstract: A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in columns and rows. Each oscillator in a column is unique from the other oscillators in the column based on number of stages in the oscillator and fanout so that each oscillator will operate at a unique frequency. Oscillators of different columns within the array may differ by a common setting of the selects to these oscillators and the physical ordering of the oscillators in the column to further reduce the possibility of injection locking. A base delay cell provides selects to each column of oscillators such that each column may be programmed to operate at a different frequency from its neighbors.

Abstract: Methods and circuits for chain ring oscillators having a constant duty cycle and being insensitive to ground noise have been disclosed. The ring oscillator generates n outputs with 360°/n phase shift and each stage is delayed by T 2 × n . The output of a suitable stage is selected so that a digital XOR-gate, using the output of a selected stage and the output of the nth stage, eliminates variations of the duty cycle caused by temperature and process variations. In case a 50% duty cycle is desired the stage number N of the selected stage can be calculated using the equation N=(n?1)/2. The duty cycle can be varied by selecting the output of another gate. A D-flipflop, clocked by the output of the XOR-gate removes noise from the clock pulses.

Abstract: A delay line for a ring oscillator circuit includes at least one delay stage having a multiple logic gate delay cells driven by a multiplexer. The multiplexer is symmetrically configured and includes multiple logic gates that are similar to the logic gates of the delay stage.

Abstract: An open-loop switching amplifier achieves synchronous operation using a ring oscillator based upon a tapped delay line. A counter is clocked from the ring oscillator, periodically comparing incoming more significant data to the value of the counter to form a pulsewidth modulated output waveform. Modulating the effective width of the output waveform in incremental delay line taps is equivalent to incoming less significant data. This technique then effects time-period summation of coarse and fine resolution clocked data.

Abstract: In one embodiment of the present invention, an apparatus includes a plurality of gain stages each having a gain greater than one, and which are coupled to create a positive feedback at an oscillation frequency. The gain stages may be formed of transconductance gain stages which may be coupled together as a ring oscillator or a latch type circuit. Such circuits may be used as calibration circuits in which small signal parameters of the gain stages are directly calibrated, and are used in turn to directly calibrate small signal parameters of a target circuit.

Abstract: A low noise oscillator constructed using a rotary traveling wave oscillator. The conductors of the rotary traveling wave oscillator provide at any tap position a pair of oppositely phased oscillations and these oscillations have slightly different phases at positions that are slightly different on the conductors. Regeneration devices establish and maintain oscillations on the conductors of the traveling wave oscillator. A regeneration device made from p-channel and n-channel transistors is connected to the conductors of the traveling wave oscillator in such a way that the gate connections of the transistors receive the traveling wavefront before the drains of the transistors receive the wavefront. By the time the regeneration device switches in response to the wavefront arriving at the gates of the transistors, the wavefront has arrived at the drains. This creates little or no disturbance to the wave on the conductors and results in low phase noise.

Abstract: The four types of the controllable idle time current mirror circuits are presented with an improvement in productivity, performance, cost, chip area, power consumption, and design time. The controllable idle time current mirror circuits basically include a sensing block, triggering transistors, current mirror, current source, a n-bit control circuit array, and a feedback line. If the sensing voltage does not reach the expected voltage compared to the midpoint voltage of the sensing gate, the triggering transistors provide a current to its output through the current mirror until the voltage at feedback reaches the midpoint voltage. Time to reach the midpoint voltage at a load is simply equal to the charge stored at the load divided by the total current, which is controlled by an N-bit digital input and a device aspect ratio of each triggering transistor.

Abstract: The present invention is directed to a system that enables the simultaneous remote monitoring of a plurality of infants' skin temperatures. The system comprises an electronic circuit that combines the functions of sensoring and multiple-channel transmitting, a pre-deployment temperature bath for calibration of the temperature sensor(s), and a receiving and reporting station for centralized monitoring the infants' skin temperatures. The present invention is further directed to a temperature sensor that measures the temperature and transmits the data in multiple channels to a remote receiver. In one embodiment, the temperature sensor comprises a ring oscillator, having a plurality of odd number of inverters, and the ring oscillator is capable of utilizing less than all of the inverters in the ring to modulate the frequency of the signal. In another embodiment, the temperature sensor comprises one inverter and a plurality of delay elements and sensor transmits phase shifted signals to modulate the signals.

Abstract: Embodiments of the invention include on-chip characterization of transistor degradation. In one embodiment, includes one or more functional blocks to perform one or more functions and an integrated on-chip characterization circuit to perform on-chip characterization of transistor degradation. The integrated on-chip characterization circuit includes a selectively enabled ring oscillator to generate a reference oscillating signal, a free-running ring oscillator to generate a free-running oscillating signal, and a comparison circuit coupled to the selectively enabled ring oscillator and the free-running ring oscillator. From the reference oscillating signal and the free-running oscillating signal, the comparison circuit determine a measure of transistor degradation.

Abstract: A method and apparatus for reducing the number of stages for measuring first and second switching speeds for PD/SOI transistors uses an inverter circuit which includes: a p-channel body-tied transistor; an n-channel body-tied transistor, coupled at their drains and gates; and a first and a second group of components tied to the bodies of the transistors. The first group restores body potentials for the transistors if the inverter circuit belongs to an even numbered stage of a ring oscillator. The second group provides body potentials for the transistors if the inverter circuit belongs to an odd numbered stage. After each transition of a waveform, the body potentials for the PD/SOI transistors are restored to the original potentials as stored in the capacitors. In this manner, a much smaller ring oscillator with fewer number of stages may be used to accurately measure the first and second switching speeds.

Abstract: The distortion component of an oscillation signal is reduced. An oscillation signal generating circuit generates, as oscillation signals, first generation oscillation signal and second generation oscillation signal which are related to each other as a differential signal. A differential amplifier performs differential amplification on the first generation oscillation signal and the second generation oscillation signal, respectively, and outputs first amplification oscillation signal and second amplification oscillation signal. A converter circuit converts the first amplification oscillation signal and the second amplification oscillation signal into an output current oscillation signal of such a form that sink current and source current are alternately switched. In order to convert voltages of the first amplification oscillation signal and the second amplification oscillation signal into currents, a variable current source delivers a converting drive current to drive the converter circuit.

Abstract: A phase locked loop circuit is implemented with difference detection module that produces a difference signal based on at least one of phase difference and frequency difference between a reference oscillation and a feedback oscillation. A loop filter module converts the difference signal into a control signal. A controlled oscillation module converts the control signal into an output oscillation. An output oscillation adjust module, coupled to the controlled oscillation module, produces an effective output oscillation based on an oscillation control signal. A divider module converts the effective output oscillation into the feedback oscillation.

Abstract: An oscillation frequency control part includes a voltage-to-current converting circuit converting an input voltage to a current having a value corresponding to the input voltage, and outputting a current in proportion to the current obtained from the voltage-to-current converting circuit. An oscillating circuit part includes a ring oscillator, wherein a current in proportion to the output current of the oscillation frequency control part flows through the ring oscillator so that the oscillation frequency in the ring oscillator is controlled by the output current of the oscillation frequency control part. The voltage-to-current converting circuit has linear voltage-to-current conversion characteristics in a predetermined range of the input voltage including a ground potential.

Abstract: An integrated circuit device is provided having one or more pairs of ring oscillator circuits. Each ring oscillator circuit of the one or more pairs of ring oscillator circuits is configured to connect to at least one voltage source capable of applying a stress to a ring oscillator circuit. One or more frequency measurement circuits are each electrically connected to a respective pair of the one or more pairs of ring oscillator circuits. Each frequency measurement circuit is configured to measure a stress induced change in frequency difference of the respective pair of the one or more pairs of ring oscillator circuits.

Abstract: A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.

Abstract: A delay circuit according to embodiments of the present invention capable of operating over a wide range of frequencies is presented. Embodiments of the invention minimize or eliminate parasitic capacitance at the output terminals that arise from switching elements used to selectively add capacitive elements to the circuit to vary the operating frequency range. A ring oscillator using embodiments of the delay circuit according to the present invention is also presented. A sequence of an integral number of delay circuits according to the present invention is coupled in series to form a ring oscillator. In some embodiments the delay circuit or a ring oscillator incorporating the delay circuit may be fabricated as an integrated circuit.

Abstract: An oscillator operates with a variable driving voltage to produce an oscillation signal of a predetermined period in a semiconductor device. The oscillator has a plurality of logic devices connected to each other in a form of a ring. The oscillator includes a voltage generating circuit for generating first and second driving voltages which are selectively applied to the logic devices. The selective application of the first or second driving voltage to the logic devices affects the period of the oscillation signal produced. The first driving voltage is applied to the logic devices for normal operations when the oscillation signal period is tested to substantially equal the predetermined period. The second driving voltage is applied to the logic devices for normal operations when the oscillation signal period is tested to be different from the predetermined period. The second driving voltage is adjusted by changing the resistance ratio of at least two resistors in the circuit.

Abstract: A ring oscillator has multiple stages that are independently adjustable. The delay is controlled using digital signals supplied to the stages. Each stage may receive two digital signals to control the delay with outputs of the particular stage controlling which of the two digital signals is used to control the delay through the stage at any particular time. The stages of the ring oscillator may be biased towards either supplying a faster or slower output signal. Each stage of the ring oscillator includes a tail node having a gate of a first transistor coupled to a digital control signal that adjusts a delay of the ring oscillator stage by turning on or off the transistor and a second transistor having a gate input coupled to a first or second voltage.

Abstract: A power management circuit is arranged to apply power to and remove power from its own oscillator to conserve power. A power-on reset circuit provides a power-on-reset signal to a state machine. The state machine contains states that are programmed with information that is used to power up or down various subsystems within a device that includes the power management systems, including the oscillator of the state machine. The state machine assumes a known state and applies power to the oscillator in response to the power-on-reset signal. The state machine changes states in response to system events (e.g., a keypress). The state machine also maintains power to the oscillator during the period of time and which the state machine requires clock signal from the oscillator. The state machine can power down the oscillator to conserve power when the state machine does not require a clock signal from the oscillator.

Abstract: A local oscillation signal generator and a multi-band transceiver including the local oscillation signal generator are provided. The multi-band transceiver includes a fractional-N phased locked loop (PLL), a local oscillation signal generator, and a transmitter. The fractional-N PLL receives a reference signal and outputs an oscillation signal that is phase-locked to the reference signal. The local oscillation signal generator receives the oscillation signal and outputs a first divided signal that is obtained by dividing a frequency of the oscillation signal by a first value and a second divided signal that is obtained by dividing the frequency of the oscillation signal by a second value. The transmitter receives input signals and generates a transmitter signal using an equation f TX = ( 2 3 ? k - 1 M ) ? f VCO , based on the first divided signal and the second divided signal.

Abstract: A tunable ring oscillator, in accordance with the teachings described herein, may include one or more delay circuits having a coarse tuning circuitry and a fine tuning circuitry. The coarse tuning circuitry may be used to set one of a minimum time delay or a maximum time delay as a function of a coarse tuning input. The fine tuning circuitry may be used to adjust between the minimum time delay and the maximum time delay as a function of a fine tuning input.

Abstract: An integrated circuit includes a first temperature sensing device providing an indication of a sensed temperature, a correlation oscillator circuit positioned adjacent to the first temperature sensing device, a plurality of other oscillator circuits, and storage locations storing calibration factors associated with at least the first temperature sensing device and the plurality of other oscillator circuits. A temperature calculation circuit determines temperatures of various locations in the integrated circuit. Each of the temperatures is determined according to an oscillation frequency of a respective one of the other oscillators, the oscillation frequency of the correlation ring oscillator, the temperature of the first temperature sensing device, and one or more stored calibration factors.

Abstract: A differential delay cell is provided herein that not only receives a pair of differential input values, but also receives a pair of differential control values for delaying the differential input values to produce a pair of differential output values. As such, a delay cell is provided, which is truly differential, and therefore, capable of demonstrating a significant improvement in noise performance. The differential delay cell of the present invention also demonstrates high frequency stability around the center frequency, constant gain and increased tuning range capabilities. In this manner, the differential delay cell may be used in PLL or DLL designs as part of a low noise VCO or a low noise delay line, respectively.

Abstract: A method and apparatus for creating a variable frequency-oscillating signal on a semiconductor device. The frequency of a ring oscillator is varied by inserting or removing additional delay into the ring. The frequency of the oscillating signal is periodically compared to an encoded input signal indicating the desired frequency. The comparison result modifies the desired frequency by modifying the amount of delay in the ring oscillator. In an alternate embodiment, an input reference clock is converted to an encoded representation of the input reference clock's current frequency. This resultant encoded representation is compared to the encoded representation of the variable frequency-oscillating signal to determine whether the delay in the ring oscillator should be modified so the frequency of the variable oscillating signal matches the frequency of the input reference clock.

Abstract: The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).

Abstract: A ring oscillator of an even number of stages of inverting/summing amplifiers that adds, to an input of each of the amplifiers, a signal from one such of the amplifiers as to be distant by an even number of stages therefrom, to realize a desired oscillation operation, thereby directly generating signals having phases shifted by 90 degrees from each other. Further, the signals in the ring oscillator are complementary to each other, so that by arranging these signals close to each other in a wiring, it is possible to realize low sensitivity to a mixed external signal.

Abstract: According to some embodiments, a circuit includes a ring oscillator delay stage. The delay stage may include a first transistor, a second transistor, and an active inductor. A gate of the first transistor may receive a first input signal, a gate of the second transistor may receive a second input signal, a source of the second transistor may be coupled to a source of the first transistor, and the active inductor may be coupled to a drain of the first transistor.

Abstract: Electronic circuitry for generating and distributing standing wave clock signals. The electronic circuitry includes one or more two-conductor transmission line segments that are interconnected with an odd number of voltage-reversing connections to form a closed loop. A regeneration device is connected between the conductors of the transmission line segments and operates to establish and maintain a standing wave on the loop. At any location on a segment there is a pair of oppositely phase oscillations.

Abstract: A clock generator capable of providing reduced low-frequency jitter clock signals without utilization of a crystal oscillator is introduced. The present invention clock generator utilizes a diode in related biasing circuit such that the generated control current to a current control oscillator is stable and clear due to the low flicker noise and low thermal noise of the voltage across the diode. The cost of PLL systems utilizing the present invention clock generator instead of a crystal oscillator is decreased. The adopted biasing circuit is introduced as well.

Abstract: A delay cell has selectable numbers of parallel load resistance transistors operable in parallel, and a similarly selectable number of bias current transistors connectable in parallel. The delay cell is preferably differential in construction and operation. A voltage controlled oscillator (“VCO”) includes a plurality of such delay cells connected in a closed loop series. Phase locked loop (“PLL”) circuitry includes such a VCO controlled by phase/frequency detector circuitry. The PLL can have a very wide range of operating frequencies as a result of the ability to control the number of load resistance transistors and bias current transistors that are active or inactive in each delay cell. Such activation/deactivation may be programmable or otherwise controlled.

Abstract: An apparatus for characterizing an operating parameter in an integrated circuit, in accordance with one embodiment of the present invention, includes a voltage potential module, a plurality of distribution systems and a plurality of ring oscillator modules. Each ring oscillator module is coupled to the voltage potential module by a respective distribution system. Each ring oscillator module generates an oscillator signal as a function of the voltage potential and a voltage drop caused by the respective distribution system. The characterization of the operating parameter may be extrapolated from the difference in the operating frequencies of the ring oscillator modules.

Abstract: An integrated circuit comprises a first circuit that receives a clock signal. A first temperature sensor senses a first temperature. Non-volatile memory that communicates with the first temperature sensor outputs calibration data as a function of the first temperature. A semiconductor oscillator that communicates with the non-volatile memory and the first circuit generates the clock signal having a frequency that is related to the calibration data. A select input selects the frequency of the output signal as a function of an external passive component.

Abstract: An SRAM design evaluation circuit topology has the gates of the SRAM cell pass Gate Field Effect Transistors (FETs) connected to the cross-coupled gates of the inverter pair of the SRAM cell. This evaluation circuit typology is used in a full cell implementation. A series of full cells are interconnected one to another in a loop to form a ring oscillator. The output of the ring is frequency divided and measured to study the read and write behavior of the cell design. Similarly, half-cells, with the gates of their pass gates grounded, are interconnected one to another to form a ring oscillator, the output of which is frequency divided and measured to help isolate pass gate impact on memory function. The modified SRAM cell topology, connected as a ring oscillator in hardware, can be used to fully characterize an SRAM cell design, without the use of peripheral read/write circuitry.

Abstract: An injection-locked frequency divider includes a selecting module for generating a control signal; a biasing module coupled to the selecting module, for receiving an original signal and generating a biasing signal according to the control signal; and an oscillating module coupled to the biasing module, for receiving the biasing signal to generate a target signal. A ratio exists between the frequency of the target signal and the frequency of the original signal.

Abstract: A ring oscillator has a first logic circuit forming a first loop. The ring oscillator also has a second logic circuit forming a second loop, such that phase interpolation occurs at a node common to the first and second loops. The phase interpolation results in an output signal with a high frequency.

Abstract: A programmable PLL including a receiver, a phase frequency detector, a charge pump, and a VCO. The receiver includes a programmable capacitor voltage divider that shifts voltage of an input clock to provide a level-shifted clock. The AC interface includes a state detection and correction circuit that ensures proper state of the level-shifted clock. The PLL includes a pulse delay modulator for generating delayed clock control signals. The VCO includes a programmable phase control circuit that dynamically adjusts phase using the delayed clock control signals. The VCO circuit includes a ring oscillator circuit with one or more phase control nodes. The programmable phase control circuit selectively couples devices to the phase control node using the clock control signals to adjust phase. The devices may be capacitors or transistors, each switched using switches controlled by the delayed clock control signals. The capacitors may be metal capacitors or semiconductor transistor capacitors.

Abstract: A digitally-controlled oscillator comprises an input for the supply of a digital input word, an adder, a stable local oscillator and a delay circuit, comprising a delay stage with a number of serially-connected coarse delay elements and a fine delay stage with a number of serially-connected fine delay elements. The coarse delay stage and the fine delay stage are embodied such that the maximum total delay and the minimum total delay differ by at most one period of the cycle signal. The delay produced by the number of fine delay elements corresponds to the delay of one coarse delay element. Each coarse delay element and each fine delay element comprise their own controllable selector.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A set of interconnected delay stages, such as a voltage-controlled oscillator, has switch-controlled load circuitry connected to each output of each delay stage in the oscillator ring. In one embodiment, for each delay stage output, the switch-controlled load circuitry includes a switch, a transistor, and a current source. The switch is connected between the corresponding delay stage output and the transistor gate, the current source is connected between a power supply and the transistor drain, and the transistor source is connected to ground. In such a configuration, the transistor's gate-to-source capacitance can be applied to the corresponding delay stage output by closing the switch, for example, for lower-frequency operations. In addition, the output impedance of the current source decouples the capacitive load from the power supply, thereby substantially shielding the oscillator ring from noise in the power supply.

Abstract: A semiconductor oscillator circuit for an EEPROM high voltage charge pump utilizes a current generating means to charge a first and a second capacitor alternatively. The charging current produced by the current generating means is inversely proportional to the ambient temperature. The charging current is proportional to the supply voltage and consequently, the oscillator frequency output remains constant over a variable voltage supply. Such a constant frequency characteristic makes a low voltage operation possible, but slows down the oscillator frequency as temperature increases. The slowing of oscillator frequency limits the charge pump output voltage and enhances the lifespan of the EEPROM cells.

Abstract: An oscillator includes first, second and third inverters (1, 2, 3) connected in series. A feedback path is connected from the output terminal of the third inverter (3) to the input terminal of the first inverter 1 through a resistor (5) while a second feedback path is connected from the output terminal of the second inverter (2) to the input terminal of the first inverter (1) through a capacitor (4). The second feedback path further includes a resistor (6) having a temperature coefficient larger than that of resistor (5) is inserted to adjust the charge/discharge trigger voltage and charge/discharge time of the capacitor (4).

Abstract: A method and apparatus for compensating for age related degradation in the performance of integrated circuits. In one embodiment, the phase-locked loop (PLL) charge pump is provided with multiple legs that can be selectively enabled or disabled to compensate for the effects of aging. In an alternate embodiment, the power supply voltage control codes can be increased or decreased to compensate for aging effects. In another embodiment, a ring oscillator is used to approximate the effects of NBTI. In this embodiment, the frequency domain is converted to time domain using digital counters and programmable power supply control words are used to change the operating parameters of the power supply to compensate for aging effects.

Abstract: The ring oscillator circuit with the current mirror type current limit circuit of this invention prevents the malfunction and the halt of the ring oscillator. The ring oscillator is configured with the serially connected CMOS inverters INV1–INV5 where the output of the last CMOS inverter INV5 is fed back to the input of the first CMOS inverter INV1. Also, the current mirror type current limit circuit for controlling the electric current going through the CMOS inverters INV1–INV5 is formed. The first supporting transistor T1 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the power supply voltage Vdd and the second supporting transistor T2 that helps the output of the CMOS inverter INV5 achieve the full-swing for reaching the ground voltage Vss according to the output of the CMOS inverter INV3 two positions ahead of the last inverter INV5 are also formed.

Abstract: A semiconductor integrated circuit in which, when leading out multiple-phase clock signal wirings from the ring oscillator circuit capable of oscillating at a high frequency, increase in the area of the substrate and deterioration in the clock phase accuracy caused by the non-uniform stray capacitances among the multiple-phase clock signal wirings are prevented. The semiconductor integrated circuit includes: N-stage amplifying circuits connected in a form of a ring to perform oscillating operation, which amplifying circuits are arranged in a semiconductor substrate to be divided into a plurality of rows, wherein in each row an amplifying circuit of “m?1”th stage and an amplifying circuit of “m”th stage are not adjacent to each other, where m is an arbitrary integer number within a range from 2 to N; and a plurality of wirings for respectively leading out a plurality of output signals from the amplifying circuits disposed in one of the plurality of rows.

Abstract: A differential delay cell includes a current source for establishing an operating current and a differentially coupled transistor pair having a common node, two input nodes, and two output nodes. The common node is coupled to the current source, and the two output nodes are coupled to an impedance load. The impedance load establishes a time delay between each of the input nodes and a corresponding one of the output nodes. Differential output signals are generated at said two output nodes in response to input signals coupled to said two input nodes. An amplitude control device is coupled between the two output nodes for controlling an amplitude of the differential output signals being generated.