Abstract: An internal voltage generator includes an oscillator, a cycle control unit and a voltage generator. The oscillator periodically generates a pulse-shaped oscillation signal. The cycle control unit bypasses the oscillation signal to an output node, or selectively controls the cycle of the oscillation signal and output a controlled oscillation signal to the output node. The voltage generator generates an internal voltage in response to the oscillation signal or the controlled oscillation signal received through the output node. The cycle of the controlled oscillation signal is shorter than that of the oscillation signal. The operating speed of the voltage generator when receiving the controlled oscillation signal is faster than that of the voltage generator when receiving the oscillation signal.

Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=¼*(f4) causing a coarse frequency adjustment and a signal ?=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Abstract: A scannable virtual rail method and ring oscillator circuit for measuring variations in device characteristics provides the ability to study random device characteristic variation as well as systematic differences between N-channel and P-channel devices using a ring oscillator frequency measurement. The ring oscillator is operated from at least one virtual power supply rail that is connected to the actual power supply rail by a plurality of transistors controlled by a programmable source. The transistors are physically distributed along the physical distribution of the ring oscillator elements and each can be enabled in turn and the variation in ring oscillator frequency measured. The ring oscillator frequency measurements yield information about the variation between the transistors and N-channel vs. P-channel variation can be studied by employing positive and negative virtual power supply rails with corresponding P-channel and N-channel control transistors.

Abstract: A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.

Abstract: A delay cell for use in a voltage controlled oscillator includes a differential amplifier having a pair of outputs, a common source resistive element supplying current to said differential amplifier, a varactor arrangement between the outputs having a control input, and a pair of load resistive elements connected to the respective outputs. The delay cell has a simple design, a small die area, low power dissipation, constant amplitude of oscillation versus control voltage, and a Figure of Merit (FOM) comparable to that of LC oscillators.

Abstract: A wide tuning range and constant swing VCO is described that is based on a multipass Ring Oscillator enhanced with feed-backward connections. This VCO is designed to overcome tuning range limitations of prior-art “feed-forward” ring oscillators. The Feedback multipass Ring Oscillator of the invention provides decreasing frequency when tuned by increasing the feedback, thus covering a much wider tuning range irrespective of the speed limit of the technology while at the same time providing almost constant amplitude.

Abstract: A mixing device includes a mixing circuit and a ring oscillation circuit. The mixing circuit includes “M” mixers connected to the input terminal of the mixing device at one input. The ring oscillation circuit includes (2×M) inverters connected in series in a ring shape. The other input of the K-th mixer where “K” is a natural number of 1 to “M” balance-inputs an oscillation signal which is phase-shifted by (?K?/M) radian and outputted from the K-th inverter and an oscillation signal which is phase-shifted by (?(M+K)?/M) radian and outputted from the (M+K)th inverter. Between the output of the K-th mixer and the output terminal is provided a phase shifter having a phase shift amount of (?2?+K?/M) radian.

Abstract: An injection locked frequency divider includes a ring oscillator, a first injection unit and a second injection unit. The ring oscillator includes a first delay cell and a second delay cell each including differential input terminals and differential output terminals. The differential input terminals and the differential output terminals of the first delay cell are respectively coupled to the differential output terminals and the differential input terminals of the second delay cell. The first injection unit connected between the differential output terminals of the first delay cell receives and injects a first injection signal to the differential output terminals of the first delay cell. The second injection unit connected between the differential output terminals of the second delay cell receives and injects a second injection signal to the differential output terminals of the second delay cell.

Abstract: Noise generation is reduced further. Oscillation control circuit 11 generates a modulation signal modulating oscillation frequency of an oscillation signal generated by oscillation circuit 12 and outputs modulation signal to same. Preferably, the modulation signal fluctuates period of the oscillation signal sequentially. The oscillation circuit 12 is composed of a ring oscillator, for example, and the power supply voltage or power supply current of the ring oscillator is controlled to fluctuate sequentially by the modulation signal output from the oscillation circuit 11. Buffer 14 of charge pump circuit 13 generates signals /? and ? by the oscillation signal and drives capacitors C1 and C2 for supplying a higher voltage than the voltage of the power supply Vcc to gate of N-channel MOSFET Q1.

Abstract: A ring oscillator includes an odd number of unit circuits connected in series each of which includes an inverter. Each of the unit circuits includes the inverter and a MOSFET. The MOSFET is an FET which is a temperature sensor, and uses a drain-source leakage current in a state that the FET is normally turned off.

Abstract: Disclosed is an internal voltage generating circuit that pumps charge to generate an internal driving voltage. The internal voltage generating circuit includes: a first oscillation signal generating unit that provides a first oscillation signal in response to a detected internal voltage and a predetermined test mode signal; a second oscillation signal generating unit that divides an external clock to provide a second oscillation signal having a variable oscillation period; and a switching unit that selects the first oscillation signal or the second oscillation signal in response to the predetermined test mode signal and provides the selected signal as a pumping period signal.

Abstract: Systems and methods which provide an oscillator circuit outputting non-overlapping trigger signals throughout a range of operating voltages using a reset-set (RS) flip-flop type circuit configuration are shown. Embodiments utilize output driver buffers internal to the RS flip-flop circuit configuration to provide oscillator feedback delay. Feedback control circuitry may be implemented to ensure that the delay associated with any one driver buffer does not solely provide the feedback delay. Embodiments further implement input delay circuitry adapted to maintain a relatively constant reset and set input feedback delay ratio throughout a large range of operating conditions.

Abstract: It is desired that the temperature dependency of the frequency of a oscillator in a semiconductor IC is compensated in high precision. First signal voltage having temperature dependency and second signal voltage set to be constant independently from the temperature are outputted and A/D converted into first and second converted signals. And the compensation code is generated in response to the ratio between the first and second converted signals. The temperature dependency of the frequency of the oscillator can be compensated by using the compensation code.

Abstract: A variable frequency multi-phase oscillator for providing multi-phase signals is disclosed. The variable frequency multi-phase oscillator includes a correlator, a plurality of delay cells, and a NOR circuit. Each delay cell includes a current supply, a capacitor, a comparator, a switch, and a logic unit. The plurality of delay cells generate the multi-phase signals that are phase correlated within a large frequency range. The frequency and duty cycles of the multi-phase signals are adjustable.

Abstract: A voltage controlled oscillator (VCO) for generating a clock of a 50% duty includes a VCO unit and a duty correction unit. The VCO unit generates first and second signals having a 180° phase difference to each other with an oscillation frequency according to a control voltage to output the first and second signals through first and second oscillation output terminals. The duty correction unit generates a clock signal of a 50% duty according to the first and second signals through the first and second oscillation terminals.

Abstract: A voltage controlled oscillator includes a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN, a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP, a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor. A first PMOS transistor includes a base terminal connected to the output node OUTP and a drain terminal connected to the output node OUTN. A second PMOS transistor includes a base terminal connected to the output node OUTN and a drain terminal connected to the output node OUTP.

Abstract: In a differential-to-single-ended (D2S) converter having reduced power consumption and excellent duty ratio characteristics, and a phase-locked loop (PLL) circuit having the same, the D2S converter includes a differential amplifier and a latch circuit. The differential amplifier amplifies a differential input signal to generate a differential output signal. The latch circuit latches the differential output signal to generate a single output signal. A bias current of the differential amplifier may be determined according to a bias voltage proportional to a voltage which is provided to a delay cell of a voltage-controlled oscillator (VCO). The D2S converter may have reduced power consumption and excellent duty ratio characteristics, and the PLL circuit having the D2S converter may have a simple circuit configuration and less power consumption.

Abstract: The present invention provides a current source device capable of cutting off an output current upon its stop and obtaining a desired output current upon its start-up. The current source device comprises a first series circuit comprising a first FET and resistors connected in series with the first FET and having both ends between which a source voltage is applied, a second series circuit which comprises a second FET and a third FET connected in series with the second FET and which includes a connecting point of the second and third FETs and a gate of the third FET both being short-circuited to each other and includes both ends between which the source voltage is applied, a drive circuit which supplies a common drive voltage to both gates of the first and second FETs, and first and second current source circuits operated in response to first and second drive voltages with gate voltages of the second and third FETs as the first and second drive voltages.

Abstract: Techniques for inline measurement of switching delay history effects in an integrated circuit device are provided. A pulse is launched down a delay chain. The pulse is substantially synchronized with a signal of a ring oscillator. The delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain. At least one difference in a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain is measured when the pulse reaches the far end of the delay chain. One or more switching histories in the integrated circuit device are determined in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse.

Abstract: A FET oscillator with increased frequency stability. This is accomplished by using a controlled voltage supply with error correction to power the amplifier stage of the oscillator. This voltage changes as the oscillator temperature increases in order to reduce the variation in frequency, caused by the amplifier and other frequency determining components changes. By using this compensated amplifier as the active section of an oscillator, the oscillator frequency stability is increased.

Abstract: Provided is a voltage detection circuit that outputs a detection result when a voltage to be measured exceeds a predetermined voltage or falls below the predetermined voltage at a speed higher than that of a conventional case. The voltage detection circuit according to the present invention includes an input buffer that outputs a detection voltage to be input as an input voltage, and a voltage detection section that accelerates a rising of the input voltage in a transient state where the input voltage exceeds a predetermined threshold value, and accelerates a dropping of the input voltage in a transient state where the input voltage falls below the predetermined threshold value. The voltage detection circuit accelerates a change in the input voltage to output the detection result from an output buffer at high speed.

Abstract: A phase locked loop with a voltage controlled oscillator, where the voltage controlled oscillator includes a feedback loop and delay cells connected in a ring. Each delay cell has a biased pMOSFET to provide pull-up current and a biased nMOSFET to provide pull-down current. For each delay cell, the gate of the biased nMOSFET is biased by the control voltage provided by the phase locked loop, and the gate of the biased pMOSFET is biased at a bias voltage provided by the feedback loop. The biasing of the pMOSFETs is adjusted so that the pull-up and pull-down currents for each delay cell are matched, thereby providing a 50% duty cycle and good jitter performance over process, supply voltage variations, and temperature variations. Because only the feedback loop has non-zero static current, low power is expected. Other embodiments are described and claimed.

Abstract: The present invention discloses a high-frequency ring coupled Quad comprising at least two transistors, which are cascaded to form a ring and bonded to resonators to form an oscillation source. The open loop feedback gain of the ring coupler of the present invention is higher than that of a conventional cross-coupled pair oscillator because the present invention adopts at least two cascaded transistors. The present invention can solve the problems of low transistor gain and high substrate loss occurring at a high frequency. The present invention has a fully symmetric circuit topology and is free of additional interconnections lines, which can obviously reduce the stray effect of interconnection lines.

Abstract: Provided is a variable frequency oscillating circuit which has a small circuit size and is unlikely to cause a semiconductor device to malfunction. One oscillating circuit (3) is used, and thus the circuit size is not increased. When a frequency control signal (SF) is switched, constant currents (I2 and I3) are each switched, and ringing is generated in the constant currents (I2 and I3), a pulse signal (SP) becomes high to be input to the oscillating circuit (3) during the ringing, and a clock signal (CLK) output from the oscillating circuit (3) in response to the pulse signal (SP) is fixed to low, with the result that the oscillating circuit (3) stops a regular oscillation. As a result, a clock signal having an unintended frequency is not generated.

Abstract: A microelectronic die including a CMOS ring oscillator thereon, and a method of using the same. The microelectronic die includes: a die substrate; and a plurality of CMOS ring oscillators on the die substrate, the ring oscillators being disposed at regions of the die substrate that are adapted to exhibit differing strain responses to package-induced stress with respect to one another.

Abstract: A voltage-controlled oscillator (VCO) of ring-connected stages, where each stage in the VCO has a first set of differential inverters biased by variable bias voltages, and a second set of differential inverters biased by fixed bias voltages. The differential inverters in each stage are connected in parallel with each other. Each set of differential inverters in a stage may contain only one differential inverter. The variable bias voltages are provided by charge pumps and associated circuits as used in well-known self-biasing schemes for phase locked loops. The fixed bias voltages are provided by a biasing circuit, matched to the circuits associated with the charge pumps, but where a fixed control voltage is applied to provide the fixed bias voltages.

Abstract: A clock distribution circuit and a method thereof. The clock distribution circuit comprises a comparator, a filter, a scaling unit, and an oscillator. The comparator compares a reference signal and a feedback signal to generate an error signal. The filter is coupled to the comparator and outputs a filtered signal based on the error signal. The scaling unit is coupled to the comparator, and scales down the filtered signal by a scaling factor to form a control signal. The oscillator is coupled to the scaling unit, and produces the feedback signal based on the control signal. And the scaling factor is less than 1.

Abstract: A High Frequency Digital Oscillator contains a ring oscillator having an output fn, and having coarse and fine frequency adjustments, wherein the input signal f1 is the input to both the ring oscillator and the High-Frequency Digital Oscillator, which has a multiplicity of output signals including f2, f4, and f8 at one-half, one fourth, and one-eighth the frequency of fn respectively, and wherein an input gating signal causes the oscillator to start or stop, a signal fc=¼*(f4) causing a coarse frequency adjustment and a signal ?=(1/f1?1/fc) making a fine adjustment, and by stopping the new output before the rising edge of f1; and then restarting starting the new output at the rising edge of so that the output and input are synchronized.

Abstract: A voltage controlled oscillator includes at least one input port for receiving a control voltage and at least one voltage-to-current coupled to the input port for generating a control current in response to the control voltage. At least one current controlled oscillator generates an oscillating frequency output in response to the control current. At least one compensation branch is coupled to the voltage-to-current converter for generating a compensation current that increases the control current when the control voltage exceeds a predetermined value.

Abstract: A ring oscillation circuit, which can operate the ring oscillation due to a positive feedback stably and continuously, is provided and it is applied to an accurate measurement of delay time and a measurement of timing accuracy in a jitter of a clock signal or the like with a high accuracy. A ring oscillation circuit comprises a delay circuit and a monostable multivibrator. An output of the delay circuit is connected to an input of the monostable multivibrator, an output of the monostable multivibrator is connected to an input of the delay circuit, and the delay circuit and the monostable multivibrator configure a positive feedback loop. An oscillation starting circuit for starting oscillation upon receipt of an input of a trigger pulse for triggering oscillation is provided on the positive feedback loop, or in the inside of the delay circuit or the monostable multivibrator.

Abstract: A circuit may comprise an amplifier powered by a first supply voltage, with a first input of the amplifier coupled to a stable reference voltage, and the output voltage of the amplifier provided as a designated supply voltage to an oscillator configured to produce a periodic signal having a specified frequency. The circuit may further include a control circuit coupled to a second input of the amplifier, to the output of the amplifier, and to ground, and configured to control the rate of change of the output voltage of the amplifier with respect to temperature. This rate of change may be specified according to a characterization of the oscillator over supply voltage and temperature, and may result in stabilizing the specified frequency across temperature. The periodic signal may therefore be unaffected by variations in the first supply voltage, and the amplitude of the periodic signal may be proportional to the stable reference voltage.

Abstract: An integrated circuit device including: an oscillation circuit that generates a first clock signal; a frequency comparison section that compares a frequency of the first clock signal with a frequency of a second clock signal; and a clock signal generation section that generates a third clock signal based on the first clock signal. The clock signal generation section corrects a frequency of the third clock signal to be a value within a predetermined range based on the comparison result. For example, the frequency comparison section counts a predetermined period based on the first clock signal, the predetermined period being defined based on the second clock signal, and the clock signal generation section generates the third clock signal by dividing the frequency of the first clock signal based on the count result.

Abstract: System and method are provided for continually monitoring reliability, or aging, of a digital system and for issuing a warning signal if digital system operation degrades past a specified threshold. The technique includes implementing a ring oscillator sensor in association with the digital system, wherein logic and/or device percent composition of the ring oscillator sensor mirrors percent composition thereof within the digital system.

Abstract: A system for generating a multiple phase clock. The system includes a ring oscillator structure for generating multiple phases. The structure includes two or more unit oscillators, each unit oscillator implemented by a ring oscillator having M stages. The structure also includes a horizontal loop coupling the two or more unit oscillators to generate multiple phases. The number of phases generated is equal to the product of the number of unit oscillators and M.

Abstract: A self refresh period signal generator includes: a voltage detection unit for detecting a voltage level of a power supply voltage in order to generate a plurality of period control signals according to the detected voltage level; and an oscillation unit for generating a ring oscillation signal having a constant period determined by a resistance of a period control resistor when a self refresh signal is activated, wherein the resistance of the period control resistor is controlled according to logic levels of the plurality of period control signals.

Abstract: There is provided an oscillator circuit capable of obtaining stable frequency by avoiding output having unstable frequency that is likely to occur to an operation/stop-control-feasible type oscillator circuit when oscillation begins. In such an oscillator circuit, an oscillation permitting signal (EN) sets an oscillator section in oscillation-operable state, whereby a controller section starts operation. The controller section that has stared its operation change an oscillation- frequency control signal (VR) into a signal value corresponding to predetermined oscillation frequency so as to set oscillation frequency at an oscillator section. Further on, the oscillator section outputs an oscillation signal in response to a detection signal (MON) that is outputted after a detector section compares a signal inputted therein with a predetermined signal value and detects that the inputted signal reaches a predetermined signal value.

Abstract: A VCO buffer circuit comprising a first loading means receiving a first signal for loading the VCO at a first input node; a second loading means receiving a second signal for loading the VCO at a second input node; a third loading means coupled to said first loading means for loading the VCO at third input node to thereby balance a load distribution on three nodes of VCO. At least three current controlling means are coupled to each other to form a symmetrical configuration and receive input signals from said first and second loading means for minimizing variations in the oscillation frequency of the VCO. A buffering means is connected to the output of the controlling means for buffering the output of the current controlling means.

Abstract: Disclosed are a method and a structure for testing location-specific wire delay at a chip-level independent of silicon delay. The invention incorporates the use of a tester embedded in a metal layer of a chip. The tester comprises a ring oscillator that is selectively connected to either a first wire or a second wire by a multiplexer. A monitor measures ring frequencies of the ring oscillator when connected to either the first or second wire. A processor determines the wire delay based upon differences in the ring frequencies. Additional testers or multiple stages of a single tester may be embedded into either the same metal layer at a different location or into a different metal layer to allow for intra-metal layer or inter-metal layer comparisons of wire delay. Since metal capacitance and silicon load remains constant for both the first and second wires and the transient voltage change along the wire is hold small, metal delay is separable from delay due to silicon device performance.

Abstract: An injection-locked frequency divider includes a ring oscillator, a signal injection circuit, a first adjustable load circuit and a second adjustable load circuit. The ring oscillator generates an oscillation signal according to a differential signal outputted by the signal injection circuit. According to an adjustable voltage, the first and second adjustable load circuits can respectively change equivalent impedances of the first adjustable load circuit and the second adjustable load circuit so that a free-running frequency of the oscillation signal of the ring oscillator is adjusted and an injection-locked frequency range of the injection-locked frequency divider is expanded.

Abstract: The present invention provides a highly accurate oscillation circuit. For example, the oscillation circuit includes plural ring oscillator units RO1 and RO2 including inverter circuits IV of an odd number of stages, and an adding unit ADD that adds signals of output nodes RO—01 and RO—02 of the RO1 and RO2. It outputs an addition result of the ADD from an output node OSC_O as a clock signal, and feeds the output node OSC_O back to input nodes RO_I1 and RO_I2 of the RO1 and RO2. Thereby, for example, when each of delay times of the RO1 and RO2 disperses based on a normal distribution of standard deviation ?, the dispersion of a clock signal obtained from the OSC_O can be confined to ?/?{square root over (2)}.

Abstract: A method for measuring intrinsic capacitance of a MOS device is provided. The MOS device includes a first terminal, a second terminal, a third terminal and a fourth terminal. First, provide a first input signal to the second terminal and ground the third terminal and fourth terminal. Then, charge the first terminal and measure a first current required for charging the first terminal. Afterward, provide a second input signal to the second terminal, ground the third terminal and the fourth terminal, and measure a second current required for charging the first terminal, wherein the first input signal and the second input signal have the same low level, but different high levels. Finally, determine intrinsic capacitance between the first terminal and the second terminal according to the first current, the second current and a high level difference between the first input signal and the second input signal.

Abstract: A controllable oscillator includes an output oscillation adjust module operably coupled to an oscillator for producing an effective output oscillation based on an oscillation control signal. The output oscillation adjust module includes an output select block that produces the effective output oscillation from a sequence of selected taps from the plurality of taps of the oscillator. A tap adjust control generator, responsive to the oscillation control signal generates a sequence of tap adjust control signals that command the output select block to select the sequence of selected taps from the plurality of taps. The tap adjust control generator includes an integrator having an integrator output, responsive to the oscillation control signal and a modulo(x) module for producing the sequence of tap adjust control signals based on the integrator output.

Abstract: This invention discloses a CMOS ring oscillator which comprises an odd number of inverting modules serially connected with each other with an output of a last stage inverting module coupled to an input of a first stage inverting module, each of the plurality of inverting modules always outputting a logic low voltage whenever being inputted a logic high voltage, all the forward signal paths of each of the plurality of inverting modules being formed by metal-oxide-silicon (MOS) transistors wherein all the gates of the MOS transistors being directly connected to the input of the respective inverting module, and at least one of the plurality of inverting modules having a negative feedback circuit.

Abstract: An oscillator circuit includes an enable circuit to generate an initialization signal and includes a ring oscillator responsive to the initialization signal and having a plurality of synchronous elements connected in a loop, wherein each synchronous element comprises a synchronous input terminal, a clock terminal, a first asynchronous input terminal, and an output terminal coupled to the clock terminal of a next synchronous element and coupled to the first asynchronous input terminal of a previous synchronous element. The enable circuit is independent of a delay path of the ring oscillator, and the ring oscillator generates a test clock signal having a period that does not include any signal delays associated with the enable circuit.

Abstract: An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signals. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

Abstract: A voltage controlled oscillator includes a first NMOS transistor having a base terminal configured to receive an input signal INP and a drain terminal connected to an output node OUTN, a second NMOS transistor having a base terminal configured to receive an input signal INN and a drain terminal connected to an output node OUTP, a third NMOS transistor having a source terminal connected to a low voltage supply VSS and a drain terminal connected to source terminals of the first NMOS transistor and the second NMOS transistor. A first PMOS transistor includes a base terminal connected to the output node OUTP and a drain terminal connected to the output node OUTN. A second PMOS transistor includes a base terminal connected to the output node OUTN and a drain terminal connected to the output node OUTP.

Abstract: An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Abstract: A plurality of variable load capacitance circuits is connected to each node between adjacent delay circuits of a ring oscillator, and changes load capacitance according to an external control signal. The control circuit adjusts timing the control signal is inputted to these variable load capacitance circuits, using a clock signal of one or more nodes of the ring oscillator.

Abstract: A counter-controlled delay line includes a main oscillator for delaying edges of an input signal to generate a main clock signal. The main oscillator includes a plurality of gated delay elements connected in a ring. Each gated delay element includes a first control terminal to receive a corresponding load signal, and includes a second control terminal to receive a release signal. The release signal may simultaneously enable and disable state transitions in all delay elements, and the load signals may simultaneously drive an output of each delay element to any selected logic state.

Abstract: Calibrating a filter is disclosed. The filter is reconfigured as an oscillator during calibration. Switches and/or other implementations of reconfiguring a filter are used to reconfigure the negative feedback loop of the filter to a positive feedback loop. The oscillation parameters are then measured to adjust the components of the filter to achieve an oscillation that corresponds to a desired filter characteristic.