Abstract: According to some embodiments, system and methods are provided including receiving, via a communication interface of an event detection and classification module comprising a processor, data from one or more sensors in a system; determining an event occurred based on the received data; applying a coherency similarity process to the received data via a classification module; determining whether the event is an actual event or a mal-doer event based on an output of the classification module; transmitting the determination of the event as the actual or the mal-doer event; and modifying operation of the system based on the transmitted output. Numerous other aspects are provided.

Abstract: An apparatus includes a first receiver frequency conversion stage and a second receiver frequency conversion stage. The first receiver frequency conversion stage may be configured to generate at least four first intermediate frequency signals in response to a radio frequency (RF) input signal and respective phases of a first local oscillator signal. The second receiver frequency conversion stage may be configured to generate at least four output signals in response to the at least four first intermediate frequency signals and one or more phases of a second local oscillator signal. Each of the at least four output signals is generated in an independent channel in response to a respective one of the at least four first intermediate frequency signals and a respective one of the one or more phases of the second local oscillator signal.

Abstract: An apparatus includes a first receiver and a second receiver. The first receiver may be configured to generate a plurality of first intermediate frequency signals in response to a radio frequency (RF) input signal and a first local oscillator signal. The second receiver may be configured to generate a plurality of output signals in response to the first intermediate frequency signals. Each of the output signals is generated in an independent channel in response to a respective one of the first intermediate frequency signals and a respective second local oscillator signal.

Abstract: A circuit includes a first input terminal, a first transmission line, a first sampling switch coupled to the first input terminal through the first transmission line, a first sampling capacitor coupled to the sampling switch, and a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength stub configured to reduce kickback noise on the first transmission line. A method for reducing kickback noise in a circuit includes determining a frequency associated with a kickback noise on a first transmission line of the circuit, the circuit having an input terminal coupled to the first transmission line, configuring a length of an open-circuit quarter wavelength stub to correspond to the determined frequency, and coupling the open-circuit quarter wavelength stub to the first transmission line to filter the frequency associated with the kickback noise.

Abstract: The oscillator is provided with an oscillator 10 which generates an oscillation signal, a first frequency division part 11 which generates a first frequency-divided signal by dividing the oscillation signal by a first frequency division ratio, a second frequency division part 12 which generates a second frequency-divided signal by dividing the oscillation signal by a second frequency division ratio, a first delay part 13 which generates a first delay signal, whose signal level changes at a timing different from the second frequency-divided signal, by delaying the first frequency-divided signal, a first output terminal 21 which outputs the first delay signal, and a second output signal 22 which outputs the second frequency-divided signal. Therefore, it is possible to prevent the levels of a plurality of signals from changing at the same time.

Abstract: A differential oscillator includes a resonator, a differential amplifier circuit, and a filter. The filter is disposed in parallel to the resonator and the differential amplifier circuit. The filter has a first resonance frequency in the first resonance mode and a second resonance frequency in the second resonance mode. The filter has a lower impedance at one frequency in one of the first resonance frequency and the second resonance frequency than an impedance at one frequency at another in the first resonance frequency and the second resonance frequency. The differential oscillator has a negative resistance at a frequency at which the impedance of the filter is higher while the differential oscillator does not have a negative resistance at a frequency at which the impedance of the filter is lower among the first resonance frequency and the second resonance frequency.

Abstract: Herein is presented, a low power on-die 60 GHz distribution network for a beamforming system that can be scaled as the number of transmitters increases. The transmission line based power splitters and quadrature hybrids whose size would be proportional to a quarter wavelength (˜600 ?m) if formed using transmission lines are instead constructed by inductors/capacitors and reduce the area by more than 80%. An input in-phase I clock and an input quadrature Q clock are combined into a single composite clock waveform locking the phase relation between the in-phase I clock and quadrature Q clock. The composite clock is transferred over a single transmission line formed using a Co-planar Waveguide (CPW) coupling the source and destination locations over the surface of a die. Once the individuals the in-phase I and quadrature Q clocks are required, they can be generated at the destination from the composite clock waveform.

Abstract: Described herein is a wireless transceiver and related method that enables ultra low power transmission and reception of wireless communications. In an example embodiment of the wireless transceiver, the wireless transceiver receives a first-reference signal having a first-reference frequency. The wireless transceiver then uses the first-reference signal to injection lock a local oscillator, which provides a set of oscillation signals each having an oscillation frequency that is equal to the first-reference frequency, and each having equally spaced phases. Then the wireless transceiver combines the set of oscillation signals into an output signal having an output frequency that is one of (i) a multiple of the first-reference frequency (in accordance with a transmitter implementation) or (ii) a difference of (a) a second-reference frequency of a second-reference signal and (b) a multiple of the first-reference frequency (in accordance with a receiver implementation).

Abstract: An orthogonally referenced integrated ensemble for navigation and timing includes a dual-polyhedral oscillator array, including an outer sensing array of oscillators and an inner clock array of oscillators situated inside the outer sensing array. The outer sensing array includes a first pair of sensing oscillators situated along a first axis of the outer sensing array, a second pair of sensing oscillators situated along a second axis of the outer sensing array, and a third pair of sensing oscillators situated along a third axis of the outer sensing array. The inner clock array of oscillators includes a first pair of clock oscillators situated along a first axis of the inner clock array, a second pair of clock oscillators situated along a second axis of the inner clock array, and a third pair of clock oscillators situated along a third axis of the inner clock array.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: A periodic signal generator is configured to generate high frequency signals characterized by relatively low temperature coefficients of frequency (TCF). This generator may include an oscillator containing a pair of equivalent MEMs resonators therein, which are configured to support bulk acoustic wave and surface wave modes of operation at different resonance frequencies. Each resonator includes a stack of layers including a semiconductor resonator body (e.g., Si-body), a piezoelectric layer (e.g., AIN layer) on the resonator body and interdigitated drive and sense electrodes on the piezoelectric layer. The oscillator is configured to support the generation of first and second periodic signals having unequal first and second frequencies (f1, f2) from first and second resonators within the pair. These first and second periodic signals are characterized by respective first and second temperature coefficients of frequency (TCf1, TCf2), which may differ by at least about 10 ppm/° C.

Abstract: Digital spur reduction in which spurs are kept outside selected channels of interest, with illustrative embodiments relating to an integrated radiofrequency transceiver circuit having digital and analogue components, the circuit having a radiofrequency signal receiver with a local oscillator signal generator configured to provide a local oscillator signal at a frequency fLO and a mixer configured to combine an input radiofrequency signal with the local oscillator signal to produce an intermediate frequency signal; and a clock signal generator configured to generate a digital clock signal at a frequency fDIG for operation of the digital components, where the local oscillator signal and/or a reference signal from which the local oscillator signal is derived are generated such that digital spurs lie outside a band selected by the receiver.

Abstract: Techniques for decimating a first periodic signal to generate a second periodic signal. In an exemplary embodiment, the first periodic signal is divided by a configurable integer ratio divider, and the output of the divider is delayed by a configurable fractional delay. The configurable fractional delay may be noise-shaped using, e.g., sigma-delta modulation techniques to spread the quantization noise of the fractional delay over a wide bandwidth. In an exemplary embodiment, the first and second periodic signals may be used to generate the transmit (TX) and receive (RX) local oscillator (LO) signals for a communications transceiver from a single phase-locked loop (PLL) output.

Abstract: A system includes a first clock module, a global positioning system (GPS) module, a phase-locked loop (PLL) module, a cellular transceiver, and a baseband module. The first clock module generates a first clock reference. The GPS module operates in response to the first clock reference. The WLAN module operates in response to the first clock reference. The PLL module generates a second clock reference by performing automatic frequency correction (AFC) on the first clock reference in response to an AFC signal. The cellular transceiver receives radio frequency signals from a wireless medium and generates baseband signals in response to the received radio frequency signals. The baseband module receives the baseband signals, operates in response to a selected one of the first clock reference and the second clock reference, and generates the AFC signal in response to the baseband signals.

Abstract: Adjusting a clock source of a device clock to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The device clock may be derived from an input clock to a serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, it may be determined that the serial interface clock is or will interfere with wireless communication. Accordingly, temporary clock signals may be provided to the device clock while the first clock is modified. Once modified, the modified clock signals may be provided to the device clock to reduce wireless communication interference.

Abstract: A master clock generation unit for satellite navigation systems, comprises a plurality of frequency inputs for receiving a respective atomic clock signal, each having a first or a second reference frequency, and a number of frequency converters each having an input connected to one of the frequency inputs and an output. Each of the frequency converters receives an offset frequency (selected according to the first and second reference frequency at the assigned frequency input) from at least one frequency synthesizer, for providing the same intermediate frequency at each of the converter outputs. A switching matrix is connected to each of the converter outputs for selecting one of the intermediate frequencies as a primary clock provided at a first matrix output, and another of the intermediate frequencies as a secondary clock provided at a second matrix output.

Abstract: An integrated circuit frequency generator is disclosed. In some embodiments, the frequency generator comprises an electronic oscillator configured to generate an oscillator frequency, calibration circuitry configured to periodically calibrate the electronic oscillator with respect to a reference frequency at a first calibration frequency when at a steady state temperature and at a second calibration frequency when at a transient temperature, and circuitry configured to generate an output frequency from the oscillator frequency.

Abstract: A system comprises a first clock module configured to generate a first clock reference that is not corrected using automatic frequency correction (AFC). A global position system (GPS) module is configured to receive the first clock reference. An integrated circuit for a cellular transceiver includes a system phase lock loop configured to receive the first clock reference, to perform AFC, and to generate a second clock reference that is AFC corrected.

Abstract: A radio frequency (RF) receiver includes an oscillator for outputting an oscillation signal from an output port thereof, a limiter for dividing the oscillation signal output from the oscillator into a branch signal at a predetermined dividing ratio outputting the branch signal, an amplifier for amplifying the branch signal output from the limiter, a frequency multiplier for outputting a local oscillation signal having a frequency obtained by multiplying a frequency of the amplified signal by a predetermined multiplicand, a mixer for mixing the local oscillation signal and a signal supplied from an antenna, a band-pass filter for receiving a signal output from the mixer and outputting an intermediate frequency (IF) signal, a detector for producing a detected signal by detecting the IF signal, and a controller connected directly with the output port of the oscillator for performing an operation according to the detected signal based on the oscillation signal as a clock signal.

Abstract: An apparatus including a ring oscillator and related methods are disclosed. The ring oscillator includes at least two ring loops. A first ring loop includes a plurality of series coupled delay cells. At least one additional ring loop includes a plurality of series coupled delay cells. The at least one additional ring loop is coupled to the first ring loop by one or more common delay cells shared between the first ring loop and the at least one additional ring loops.

Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.

Abstract: A communications device (100) includes a frequency divider circuit (106) having a plurality of frequency division ratios. The device also includes at least one phase-lock loop (PLL) circuit (101, 102, 103, 104, 110, 112) coupled to at least a signal input of the frequency divider circuit. The PLL circuit includes a local oscillator (LO) circuit (104) including a plurality of voltage controlled oscillators (VCOs) having different frequency tuning ranges. The device further includes at least one control input (105) coupled to at least the frequency divider circuit and the PLL circuit for specifying one of the plurality of VCOs and one of the plurality of frequency division ratios of the frequency divider circuit.

Abstract: An oscillator is provided. The oscillator comprises a flip-flop module, a first and a second setting module. The first setting module comprises: a first switch device to generates a first switch signal according to a first oscillating signal, an NMOS and an inverter. The NMOS comprises a drain to receive a first charging current and a gate to receive the first switch signal, wherein the drain is charged or discharged according to the first switch signal. The inverter is connected to the drain to generate a first setting signal. The second setting module comprises a second switch device to generate a second switch signal according to a second oscillating signal and a comparator to generate a second setting signal according to the second switch signal and a reference voltage. The flip-flop module generates the first and the second oscillating signal according to the first and the second setting signal.

Abstract: Provided are a multi-output oscillator using a single oscillator, and a method of generating multiple outputs. The multi-output oscillator includes: an oscillator outputting the single frequency; a multiplier multiplying the single frequency to output a first frequency; a first frequency divider dividing the single frequency by a first division factor; a first mixer outputting a second frequency by mixing an output of the first frequency divider and an output of the multiplier; a second frequency divider dividing the single frequency by a second division factor; a second mixer mixing the output of the second frequency divider and the output of the first mixer to output a third frequency; and a third mixer mixing the output of the second frequency divider and the output of the multiplier to output a fourth frequency.

Abstract: In a surface-mount crystal oscillator, an IC chip having an IC terminal at each of at least four corner portions is housed in a substantially rectangular recess. Circuit terminals to which the IC terminals are fixed via bumps are provided on an inner bottom surface of the recess, and external terminals electrically connected to the circuit terminals are provided at the four corner portions of an opening end surface surrounding the recess. In each of at least three vertices or corners on the inner bottom surface of the recess, an external terminal corresponding to the vertex is formed into an L-shape to be in contact with a longer side and a shorter side of an outer perimeter of the recess, and an exposed part in which the inner bottom surface is exposed is formed between the circuit terminal which is the closest to the vertex and its external terminal.

Abstract: A pulse signal circulates around a ring of delay elements with respective traversal signals being thereby successively outputted from the delay elements. The period of a reference signal is multiplied or divided by a real number to obtain control data specifying a required period of a clock signal as a value having an integer part and a fractional part. The control data are used to select the timings of specific traversal signal, and the clock signal is generated based these selected timings, with the timing selection being repetitively adjusted in accordance with the fractional part of the control data.

Abstract: Methods and apparatus for placing a non-volatile memory systems in one of a number of power-down modes in response to events being monitored are useful in reducing power consumption of the non-volatile memory system. The power-down modes provide for successively less functionality, thus providing for successively less power consumption. A non-volatile memory system thus can respond to the events to place the system in a mode that permits the desired operation or a desired response time for subsequent operations while seeking to minimize power consumption.

Abstract: An output terminal 6 is provided at the connecting point 5 between the collector terminal of a transistor 1 and an open-ended stub 4 by connecting the open-ended stub 4 to the collector terminal of the transistor 1, the open-ended stub 4 having a line length equal to a quarter of the wavelength of a signal of frequency 2N·F0 or 2N times the oscillation frequency F0. In addition, an output terminal 9 is provided at a connecting point 8 located at a distance equal to a quarter of the wavelength of a signal of oscillation frequency F0 from the end of an open-ended stub 7 by connecting the open-ended stub 7 to the base terminal of the transistor 1, the open-ended stub 7 having a line length longer than a quarter of the wavelength of the signal of oscillation frequency F0.

Abstract: A phase-locked loop (PLL) to provide clock generation for high-speed memory interface is presented as the innovate PLL (IPLL). The IPLL architecture is able to tolerate external long loop delay without deteriorating jitter performance. The IPLL comprises in part a common mode feedback circuit with a current mode approach, so as to minimize the effects of mismatch in charge-pump circuit, for instance. The voltage-controlled oscillator (VCO) of the IPLL is designed using a mutually interpolating technique generating a 50% duty clock output, beneficial to high-speed double data rate applications. The IPLL further comprises loop filter voltages that are directly connected to each VCO cell of the IPLL. Conventional voltage-to-current (V-I) converter between loop filter and VCO is hence not required. A tight distribution of VCO gain curves is therefore obtained for the present invention across process corners and varied temperatures.

Abstract: A voltage-controlled oscillator comprises an inductor and a group of variable capacitance elements forming a resonance circuit. The group of variable capacitance elements includes first and second variable capacitance elements connectable in parallel and having mutually different absolute values of a ratio of control-voltage sensitivity to capacitance. The first and second variable capacitance elements both have a first end supplied with a control voltage for controlling resonance frequency of the resonance circuit and have a second end selectively connected to the inductor by a band selection signal for deciding a band in which the resonance frequency exists.

Abstract: Apparatus to generate signals with multiple phases are described. The apparatus includes a fixed multilayer stack providing a varying magnetic field and at least two sensors adjacent the fixed multilayer stack to sense the varying magnetic field and generate at least two output signals. The frequency of the output signals can be tuned by an input current.

Abstract: An integrated resonance circuit is provided for providing a high-frequency output signal, comprising a first output for providing a first high-frequency output signal with a first frequency and a first amplitude, a first inductive unit connected to the first output, and a first capacitive unit connected to the first output. According to the invention, a second output for providing a second high-frequency output signal with a second frequency and a second amplitude is provided, whereby the second frequency matches the first frequency and the second amplitude differs from the first amplitude, and a second inductive unit, connected to the first output and to the second output, and a second capacitive unit, connected to the second output, are provided. The invention relates furthermore to a voltage-controlled oscillator and to an integrated circuit.

Abstract: Disclosed is a multi-loop PLL circuit and a related method of which, the circuit includes: a first loop for generating a first control current; a second loop for generating a second control current; a loop filter for generating a control signal according to the first control current or the second control current; a voltage control oscillator for generating a first oscillating signal or a second oscillating signal according to the control signal; a first frequency divider for generating a first feed back clock signal; a second frequency divider for generating a second feed back clock signal; and a control circuit for switching the first loop or the second loop to generate the control signal. The frequency of the second reference clock signal is higher than which of the first reference clock signal. The control circuit turns on the second loop first and then turns on the first loop.

Abstract: The invention relates to a dual band frequency synthesizer for generating either a first output frequency fhigh or a second output frequency flow, where fhigh=2 flow, comprising an oscillator circuit for generating at its output a frequency fVCO=(fhigh+flow)/2, a divide by three (3) circuit, coupled to the output of the oscillator circuit, for generating at its output an offset frequency fDB3=fVCO/3, and a double quadrature mixer circuit, coupled to the output of the oscillator circuit and to the output of the divide by three circuit, for generating either the first output frequency fhigh=fVCO+fDB3 or the second output the frequency flow=fVCO?fDB3.

Abstract: Oscillators (10) which oscillate at a fundamental frequency also generate harmonics. The fundamental frequency or a lower harmonic is used for feedback purposes, and a harmonic higher than either the fundamental frequency or the lower harmonic is used for output purposes. As a result, the oscillators (10) operate at a lower frequency than an output frequency and are low cost. Synthesizers (20) coupled to the oscillators (10) also operate at this lower frequency, and modulators (5) comprising such oscillators (10) and synthesizers (20) are low cost. A lower power consumption and less sensitivity to disturbing fields are further advantages. Filtering has become less complicated, and a smaller number of components has resulted in smaller dimensions. The oscillators (10) comprise tuning circuits (11) and amplifiers (12), which amplifiers (12) are fed back via feedback circuits (13). Such an amplifier (12) may comprise just a single transistor (40).

Abstract: A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.

Abstract: The crystal oscillator device for simultaneously generating oscillator signals with a plurality of oscillation modes of a crystal unit, comprising: a primary resonator unit filtering the oscillator signal with a primary oscillation mode, which is one of the oscillation modes, from the output of the crystal unit, a secondary resonator unit filtering the oscillation signal, bearing a different resonance frequency from that of the primary resonator unit, with the primary oscillation mode from the output of the crystal unit, a primary phase synthesis unit, synthesizing the phases of the output signal of the primary resonator unit and the output signal of the secondary resonator unit, a tertiary resonator unit, a quaternary resonator unit, and a secondary phase synthesis unit.

Abstract: System and method for providing clocks to digital circuitry with a need for multiple clocks. A preferred embodiment comprises an oscillator controller (oscillator clock domain block 305) distributes a system clock generated by an oscillator to a plurality of clock domain blocks (GSM clock domain block 310 and so forth). The clock domain blocks use the system clock to generate specific clocks needed by attached hardware. The clock domain blocks may be programmed after manufacture to permit customized clock generation to meet requirements.

Abstract: The voltage controlled oscillator includes an oscillating transistor, and first and second inductance elements which are connected in series and provided between an output terminal of the oscillating transistor and a high frequency ground point Vcc. Oscillating signals are output from the output terminal of the oscillating transistor and a connecting point between the first inductance element and the second inductance element, respectively. The output terminal of the oscillating transistor outputs a fundamental wave having a high level, and the connecting point between two inductance elements outputs the harmonic wave, suppressing the fundamental wave.

Abstract: A crystal is loaded with capacitance in such a way that it begins to oscillate at a desired frequency with a resonance circuit (2). Capacitive voltage division is carried out with a voltage divider to at least one terminal (3) of the crystal (1). From the voltage divider, the signal of the crystal (1) is supplied to a second circuit (7).

Abstract: A dual data rate dynamic random access memory (DDR DRAM) device may operate in dual DDR modes via a mode selection circuit configured to enable a Dual Data Rate (DDR) 1 mode of operation for the DDR DRAM or a DDR2 mode of operation for the DDR DRAM.

Abstract: A system and method are provided for reducing power consumption within a video processing portion of a system. Activity associated within a video-processing portion of a personal digital assistant is analyzed. As reduced activity is identified, power conservation modes are implemented. In a normal mode of operation, a clock signal generated through an external oscillator is provided to a phase locked loop (PLL). An output clock signal from the PLL is then provided to several dividers to generate system clock signals. In a reduced mode of operation, the output clock from the external oscillator is provided to a divider, bypassing the PLL. Video processing components then use clock signals based on the external oscillator. In a suspend mode, both the PLL and the external oscillator are disabled.

Abstract: Methods and arrangements for a low power, phase-locked loop (PLL) are disclosed. Embodiments include a multi-phase oscillator like a voltage-controlled oscillator (VCO) to generate multiple phases of a clock signal. The multiple phases are then combined to generate a single clock signal having a frequency substantially equivalent to the number of phases multiplied by the frequency of the clock signal generated by the multi-phase VCO. Advantageously, embodiments can generate clock signals having frequencies that are multiples of the frequency generated by the VCO, reducing the power consumed by the VCO to produce a clock signal having the same frequency as a clock signal generated by a single phase VCO. Further, the achievable frequency for the VCO is increased. In many embodiments, a high speed, n-bit frequency divider that implements a pulse latch facilitates the use of the multi-phase VCO to generate the very high frequency clock signals.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: In a shift clock signal generating apparatus, a delay line includes a plurality of unit delay elements connected in cascade. A reference clock signal propagates in the delay line while being successively delayed by the unit delay elements. Switches have first ends connected with output terminals of the unit delay elements respectively, and second ends connected with a shift clock signal output path. When specified one among the switches is in its on position, a delayed clock signal which results from delaying the reference clock signal by a prescribed time interval is transmitted via the specified switch to the shift clock signal output path as a shift clock signal. The specified one among the switches is determined on the basis of data representing a phase difference of the shift clock signal from the reference clock signal. The specified switch is set in its on position.

Abstract: A circuit provides a programmable phase shift feature, where the phase shift is programmably selectable by a user. This circuitry may be incorporated in a programmable logic device (PLD) or field programmable gate array (FPGA) to provide additional programmability features. The programmable phase shift circuitry may be implemented within a phase locked loop (PLL) or delay locked loop (DLL) circuit.

Abstract: An apparatus and method for generating a plurality of output signals that can be used for driving a corresponding plurality of charge pumps from a signal oscillating between a first and second logic state. The apparatus includes a plurality of shift register stages coupled in series, where the shift register stages shift a latched logic state in response to the oscillating signal. Further included in the apparatus is a duty cycle correcting circuit coupled to the output terminals of the shift register stages which generates each of the output signals that can be used to drive a charge pump based on the latched logic state of two of the shift register stages.

Abstract: An IrDA modulation/demodulation integrated circuit device designed for use in a portable telephone receives a clock used in a base-band integrated circuit device for processing a base-band signal, and converts the frequency of the received signal by using a PLL circuit 5 to produce a clock. This helps reduce the number of resonators incorporated in the portable telephone, and thereby reduce the cost thereof and the area of the circuit board provided therein.

Abstract: A clock generating apparatus and method for generating clock signals of different frequency. The clock generating apparatus and method receives and divides a main clock signal to obtain a reference clock signal. Then, the reference clock signal and the first feedback clock signal are phase-locked to obtain the first clock signal. Moreover, the reference clock signal and the second feedback clock signal are phase-locked to obtain the second clock signal. The reset signal and the first clock signal are received by a divider. The divider then outputs the first feedback clock signal. Another divider receives the reset signal and the second clock signal and then outputs the second feedback clock signal.

Abstract: A delay locked loop (DLL) is provided that generates an internal clock signal in synchronization with an external clock signal. First through third amplifiers convert the swing width of the external clock signal to a small swing width and re-convert the external clock signal to an external signal level. A basic clock generator generates a plurality of basic clock signals that are progressively shifted apart by a predetermined phase. First through third duty correctors correct the external clock signal, a first internal clock signal, and a second internal clock signal to satisfy 50% duty. First and second mixers generate a first clock signal and a second clock signal which is 90 degrees out-of-phase with the first clock signal. Finally, the first internal clock signal is 90 degrees out-of-phase with the second internal clock signal. Thus, the first internal clock signal is synchronous with the external clock signal.