Abstract: A pulse width modulation control circuit of the present invention causes variation amplitudes of a sawtooth voltage in a sawtooth oscillator being synchronized by an external signal to be lowered thereby improving characteristics with respect to both a noise and a system control. The pulse width modulation control circuit includes a sawtooth oscillating means for generating a sawtooth voltage after receiving the synchronizing signal, that is, a synchronizing frequency; a sawtooth controller for receiving the sawtooth voltage generated from the sawtooth oscillating means, also receiving a reference voltage with respect to the sawtooth voltage, and outputting a current controlling constantly an amplitude of the sawtooth voltage to the sawtooth oscillating means; and a pulse width modulating means for receiving an output voltage, also receiving a reference voltage with respect to the output voltage, then receiving the sawtooth voltage generated from the sawtooth oscillating means 100, modulating a pulse width.

Abstract: A pulse width modulation system provides for enhanced output resolution through software control. The pulse width modulation control system normally has a control period during which the pulse width modulation state assumes a predetermined one of a plurality of output states. The method herein toggles between two adjacent output states during any single control period to effectuate a resultant system response characteristic of a system having a greater number of available output states. Furthermore, certain preferred implementations may also suppress undesirable harmonic excitation of the system through quasi-random toggling.

Abstract: The present invention teaches an oscillator and transmitter. The balanced oscillator comprises a resonator for generating a reference signal having a resonating frequency, a first oscillator for providing a first oscillating output in response to the resonating frequency, and a second oscillator for providing a second oscillating output in response to the resonating frequency. The second oscillating output has a magnitude equal to the first oscillating output while oscillating 180 degrees out of phase with the first oscillating output. The transmitter comprises an antenna for radiating the first and second oscillating output signals.

Abstract: For triggering analog actuators with pulse-width modulation, a pulse duty factor (TV) is specified as relative ratio of pulse time (t.sub.PU) to period duration (T) of a triggering period. An add value (AW) is defined as product of the specified pulse duty factor (TV) and a maximum add value (AMW). Adding steps with specific cycle time (t.sub.z) and specified add value (AW) in each case follow one another successively. In an adding step, the add value (AW) is added, using an adding element with memory function and overflow detection, to the value stored in the adding element. The result of the adding operation is stored as a new memory value in the adding element. The logic state at the output of the adding element is defined by the overflow that occurs in the adding step, and the actuator is triggered according to the respective logic state at the output of the adding element.

Abstract: A signal convertor comprising a pulse modulator, and a modifier for modifying the signal input thereto in dependence upon the error in previous values of the output thereof, to reduce the effects of said error within a desired signal band.

Abstract: A fixed impedance load is provided with a signal having a variable frequency F from a line capable of supplying a variable available power. The device comprises a pulse width modulator that operates at frequency F and supplies the load with pulses, the width of which varies in the same way as the available power, so that the consumed power on the line remains lower than the available power.

Abstract: Disclosed is an improved digital data modulating method appropriate for stable and high-speed communication. It comprises the step of allotting each of N sequential digital data bit combinations to a corresponding period-and-phase discriminating signal, thereby providing a modulated signal in the form of a series of different single-periods, which modulated signal is insensitive to noise signals appearing in communication mediums.

Abstract: A heater driving device for supplying AC power to a heater of a fixing device of an image forming apparatus. The heater driving device has self arc suppression type elements between an AC power source and the heater for controlling supply of AC power to the heater in accordance with a control signal supplied to the self arc suppression type elements. The control signal is obtained by modifying signal voltage corresponding to the temperature of the heater in accordance with an absolute value signal which is generated by reducing AC power and converting the reduced AC power to an absolute value, and then comparing the modified signal voltage and a pulse signal generated by a triangular wave oscillator.

Abstract: A pulse width controller comprising a circuit for generating a carrier signal; a carrier synchronization circuit for generating a carrier synchronous variable pulse signal that varies in accordance with the voltage level of the carrier signal; an integrator for integrating a reference signal, the carrier signal and the carrier synchronous variable pulse signal to generate an integrated input signal; a comparator for comparing the integrated input signal with a comparison signal to generate a compared input signal; and a circuit for synchronizing the compared input signal with one or more of the carrier signal and carrier synchronous variable pulse signal to generate a synchronous input signal and providing the synchronous input signal to the input of the integrator to be integrated with other signals.

Abstract: The present invention is a digital electronics system for generating multiple pulses within a predefined pixel clock period in a digital output device, where both a leading edge delay and a trailing edge delay are specified for a first pulse to be generated during the predetermined clock period. Pulse forming circuitry generates the first pulse during the portion of the clock period between the leading edge delay and the trailing edge delay, and an inverting circuit, selectable on a clock period basis, is activated to produce complimentary pulses within the selected clock period. The system is depicted as a two phase embodiment which enables high-speed operation.

Abstract: A triangular wave generator circuit having a triangular wave generator unit for generating a triangular wave signal, and a comparator for comparing the generated triangular wave signal with a predetermined level. The triangular wave generator unit controls the generated triangular wave signal in accordance with the comparison result by the comparator.

Abstract: A switched-inverter modulator for use in driving a load that comprises master and slave high voltage power supplies for providing output pulses that directly drive the load. A synchronized pulse generator provides pulse width tinting and synchronized amplitude commands to the master power supply. The timing pulse instructs the power supplies when to initiate high voltage and for what time interval. The analog waveform instructs the master power supply as to what high voltage level to obtain. The master power supply may have multiple slaves connected in parallel for additional current capacity. A low voltage DC capacitor bank is connected in parallel with each of the power supplies to supplement energy storage. Isolation resistors are coupled between outputs of the respective high voltage power supplies and the load to minimize temporary shorts from ringing back into the power supplies.

Abstract: A balanced oscillator and transmitter circuit is provided which includes a pair of balanced Colpitts-type oscillators for generating an enhanced power radiating output signal. The balanced oscillators share a series resonance input tank. Each oscillator has an amplification stage which preferably includes a Colpitts-type configured transistor. The transmitter circuit further includes first and second output tanks having first and second radiating elements which may include a pair of inductors. An oscillating current signal is generated by the oscillator and is commonly transmitted through the pair of radiating elements. Each radiating element transmits radiating output signals which are combined and summed in total to provide an efficient radiating output signal. Alternately, the first and second output tanks may include a center-tapped transformer coupled to a third radiating element.

Abstract: A pulse width modulator (20) includes a reconfigurable counter (30) whose width is determined by mode control bits. In one embodiment, a decoder (24) decodes the mode control bits to provide decoded width control signals to the reconfigurable counter (30). The width control signals enable selected least significant counter cells (101-107) of the reconfigurable counter (30) in a binary-to-thermometer fashion. Thus, unused counter cells are disabled, reducing power. The pulse width modulator (20) also includes an output circuit (25) which provides a pulse width modulated output signal having a duty cycle determined by a proportion of a cycle of the reconfigurable counter (30) during which a comparator (23) detects that an output of the reconfigurable counter (30) has reached a value of an input number. A portion of the comparator (23) may also be disabled in response to the width control signals.

Abstract: A digital modulation process and apparatus for converting an input signal comprising a time variable series of sampling values, each of which sampling values remains constant within a fixed sampling period, into output signals representing a sequence of positive and/or negative pulses having a constant amplitude and a variable pulse width and frequency. The input signal and modulator parameters are supplied to a data processor. In order to reduce computing expenditures and at the same time achieve an increase in precision, by means of the computing system, the switch-on and switch-off points in time t.sub.se, t.sub.sa of the pulses as well as their operational signs are computed in one operation directly for each sampling period .DELTA.t.sub.k.

Abstract: The present invention an apparatus provides a pulse width modulated signal to a load in response to an input signal. The apparatus receives the input signal and a feedback signal, determines a difference between the received signals, integrates the difference, and responsively produces an error signal. The error signal is compared with a reference wave signal and a correction signal is produced. The apparatus produces the pulse width modulation signal by conditioning the correction signal. The apparatus determines the feedback signal by attenuating the pulse width modulation signal in a manner similar to the attenuation caused by the load.

Abstract: A pulse width modulation apparatus outputs an output pulse having an arbitrary width with respect to an arbitrary point in a pulse period. A delay means associated with a pulse cycle have multi-stage delay output means. Before a control pulse CLKP is fed to each of multi-stage delay output means, a delay time for the delay output means can be set. A rising or falling to be latched by a latch means is controlled based on delay control pulses obtained by the delay output means. An output pulse having an arbitrary pulse width with respect to an arbitrary point can be supplied without occurrence of an offset pulse or a blank duration at the start of each pulse duration.

Abstract: A pulse width modulator (PWM) (20) receives a two's complement input number and separates a sign bit from remaining less significant bits. The PWM converts these bits into an unsigned number in dependence on the sign bit. A comparator (41) provides a compare output signal in response to an output of a counter (30) equaling the unsigned number. An output circuit (25) provides first and second pulse width modulated signals for a length of time determined by the output of the comparator (41) in dependence on whether the sign bit indicates a positive or negative sign. In one embodiment, the PWM (20) converts a negative two's complement number to the unsigned number by one's complementing the least significant bits, and the output circuit (25) keeps the second pulse width modulated signal active for one additional clock cycle to fully convert to two's complement form, without the need for a carry operation.

Abstract: A pulse width modulation circuit apparatus of a digital type using a delay circuit and a decoder, which is provided with a delay control circuit for driving the reset-set type flip-flop of a last output stage and which provides the flip-flop with a mode determination function, whereby the range of the operation frequency is broadened, the generation of a blank pulse and offset pulse can be suppressed, and a higher precision gradation expression can be realized.

Abstract: A circuit for generating pulse width modulation (PWM) signal is formed of an U/D counter 4 for regulating a control cycle of a PWM waveform, a register 1C for storing on-timing information of the PWM waveform, and a register 1D for storing off-timing information of the PWM waveform. The circuit is actuated by one of first and second modes. In the first mode, the PWM waveform is outputted by comparing output of the counter 4 with the respective outputs of the registers 1C, 1D. In the second mode, the counter 4 counts down a signal, and after reaching zero, the counter counts up again, which is made within one cycle and is compared with only the output of the register 1C to output the PWM waveform. In the second mode, the reset level is not calculated, so that load to CPU is relieved, and the carrier cycle is shortened.

Abstract: An error signal isolator circuit for conveying an error signal across an electrical isolation boundary such as an external pulse transformer employs a level shifting process whereby a controllable voltage is measured with respect to a reference voltage and, with any gain implemented in the process, is level shifted upward such that the higher potential is referenced to a supply voltage and the lower potential is used dynamically to control the magnitude of voltage conveyed in a pulse amplitude modulation (PAM) process. In the PAM process, an ON pulse is terminated by monitoring when a PAM current has increased to a predetermined and controllable level. An ON pulse is initiated by monitoring when the voltage across a clamp diode has decayed below its normal forward bias level, indicating a commensurate decay in PAM current, following termination of the previous ON pulse.

Abstract: A transceiver device for use with a microcontroller and a symbol encoder decoder device (forming a node in a communications network) for transmitting and receiving variable pulse width modulated (VPWM) analog signals containing symbol messages over a communications bus. The transceiver accepts digital VPWM signals from the symbol encoder decoder device which were generated by the microcontroller and converts the digital signals into VPWM analog signals and then transmits the analog signal over the bus to other nodes. The transceiver also receives VPWM analog signals placed on the bus by other nodes of the network and transfers the signals in digital form to the symbol encoder decoder device which, in turn, communicates the decoded messages to the microcontroller. The transceiver contains a ground translation circuit for transferring transmitted signals to an independent bus ground return before a bus driver circuit sources message signals in the form of pulse currents over the bus.

Abstract: A pulse width modulation apparatus having a storage circuit for temporarily storing pulse width data inputted over a data bus and then inverting it, the pulse width data determining a pulse width, a counting circuit for counting a clock signal in response to an external pulse width modulation enable signal and an external reset signal, a comparison circuit for comparing the number of logical 0 bits of the inverted pulse width data from the storage circuit with the number of logical 1 bits of count data from the counting circuit and outputting a high signal when the number of the logical 0 bits of the inverted pulse width data is greater than or equal to the number of the logical 1 bits of the count data and a low signal when the number of the logical 0 bits of the inverted pulse width data is smaller than the number of the logical 1 bits of the count data, and an output circuit for latching an output signal from the comparison circuit to output a pulse width modulation signal.

Abstract: A pulse width modulator generates a linear sawtooth ramp waveform from a pulse signal to compare against an amplified input signal derived from a transducer output voltage signal. A first circuit generates the linear ramp waveform in response to the pulse signal. First and second amplifiers receive the differential transducer signal and provide the amplified input signal to one input of a comparator. The comparator has another input receiving the linear ramp waveform, and an output for providing a pulse width modulated output signal having a duty cycle proportional to the differential transducer signal. If the amplified input signal is greater than the sawtooth ramp then the output signal of the pulse width modulator goes to one state; otherwise, the output signal goes to an opposite state. The pulse width of the output signal is thus linearly proportional to the amplitude of the transducer output signal.

Abstract: A pulse width modulator comprises: a reload register (8) which stores data D1 set as an initial value of data D and loads to a waveform timer (3), every time one waveform cycle is counted; a comparing circuit (10) which compares the data D1 and data D2 when the data D1 is changed to the data D2; and an incrementer/decrementer (9) which functions as an increment when the data D2 is larger than the data D1 as the comparing result, and as an decrementer when smaller, and every time the one waveform cycle is counted by a cyclic timer (7), increments or decrements the data D1 held in the waveform timer (3); and changes the ratio of an "H" level period and an "L" level period of an output waveform relatively slowly, against the rate of change (from D1 to D2) of a set value D of a timer register (2) for setting the "H" level period and the "L" level period of a pulse width modulation waveform.

Abstract: A microcomputer having a signal generating circuit which generates pulse width modulation signals defined by a carrier wave, and which controls controlled portions according to pulse width modulating signals. The signal generating circuit comprises a carrier wave defining timer which outputs a value varying the same as a waveform providing a carrier wave, a control register which controls the time period of the timer, a reload register which holds a count value, control blocks which generate pulse width modulation signals according to the value of the timer and the count value of the reload register.

Abstract: A dynamically selectable multimode pulse width modulation system includes ramp generator means for generating a ramp; pulse edge modulation means responsive to the ramp generator means for defining a leading edge modulated pulse, a trailing edge modulated pulse and a dual edge modulated pulse; and mode selection means responsive to the pulse edge modulation means for selecting one of the leading edge modulation, trailing edge modulation, and dual edge modulation modes of pulse width modulation.

Abstract: An image signal processing apparatus including an image signal output device activated in synchronism with a pixel synchronizing signal for outputting therefrom an image signal which defines, as a variable region, a d.c. level formed between a first d.c. level and a second d.c. level exceeding the first d.c. level, a triangle-shaped wave signal generator activated in synchronism with the pixel synchronizing signal for outputting therefrom a triangle-shaped wave signal which defines, as a variable region, a d.c. level formed between a third d.c. level less than the first d.c. level and the second d.c. level, and a comparator supplied with the image signal and the triangle-shaped wave signal so as to output a pulse-width modulated signal therefrom.

Abstract: A pulse width modulating circuit including a shift register and a subtraction circuit, with first and second binary counters respectively connected to the outputs of the shift register and the subtraction circuit, and a logic circuit connected to the outputs of the binary counters. Pulse width control data bits are input to the shift register and the subtraction circuit. The shift register processes the pulse width control data bits by shifting them one bit to the right and dividing the control data bits in half. The output of the shift register is also connected to the subtraction circuit and provides one-half of the pulse width control data bits to the inputs of the subtraction circuit and the first counter. A load signal is respectively applied to the first and second binary counters which are responsive thereto for sensing the left and right edges of a pulse width modulation signal based upon the outputs from the shift register and the subtraction circuit.

Abstract: A pulse shaping system for a pulse width modulation system includes: a ramp generator for generating a ramp signal having a ramp portion and a rest portion; a latch signal generator providing a latch signal coincident with the ramp portion; an indicator circuit for indicating desired pulse width; a pulse edge modulator responsive to the ramp portion and to the indicator circuit for providing a pulse width modulated pulse having at least one of its edges modulated; and including one or both of a fill circuit and a blanking circuit. In response to an indication from the indicator circuit of a desired maximum pulse width, the fill circuit causes the latch signal and the pulse generated by the pulse edge modulator to be combined for producing a maximum width pulse at the full width of the latch signal and the ramp portion.

Abstract: A dual edge pulse width modulation system includes a ramp generator for generating a voltage ramp; an n bit digital to analog converter having a normal and an inverted output for establishing a leading edge and a trailing edge reference; a comparator responsive to the ramp and the leading edge and trailing edge references, respectively, for defining the leading edge and the trailing edge of a pulse; and a pulse generator for producing a pulse having the width determined by the defined leading and trailing edges.

Abstract: An anti-false triggering system for a pulse width modulation system includes a ramp generator for generating a ramp signal having a ramp portion and a rest portion; a latch enable signal generator for providing a latch enable signal only during the ramp portion of the ramp signal; and a pulse edge modulator responsive to the ramp portion of the ramp signal for providing a pulse with at least one of its edges modulated, the pulse edge modulator being enabled by the latch enable signal only during the ramp portion of the ramp signal for suppressing false triggering of the pulse edge modulator during the rest portion of the ramp signal.

Abstract: An improved binary data communication system employs an improved VPSK encoding procedure wherein each input data bit has a bit period of M clock periods, and the data bit polarity changes are phase shift key coded with waveform widths of M/M, M+1/M, and M+2/M bit periods wherein M is an even integer greater than 3. Each of the data bits (except the last one in an encoding cycle) is encoded in an encoding signal which switches back and forth between "1" and "0" polarities and has assigned widths representing whether or not the polarity of the data bit is changed from that of the previous data bit, and whether it is the last (M-1th) polarity change in the encoding cycle. At the receiving end, a complementary procedure is used to decode the encoded signal. For transmission, the encoded signal is filtered for higher order harmonics and integrated in order to provide a sine wave output shifted 90 degrees in phase.

Abstract: A digital-to-analog converter utilizing a PWM system for converting input digital data to PWM signals and finally to an analog signal divides the sampling period of the input digital data into an even number of sampling periods and produces PWM signals with equal pulse widths corresponding to the input digital data each divided sampling period, whereby a simple structure is provided to reduce harmonic distortion and obtain a high quality analog signal.

Abstract: Improved pulse width modulation technique provides for an increased sampling rate without an increased ON/OFF rate at associated control devices. Both ON/OFF and OFF/ON edges in a PWM signal are modulated. The system then samples at twice the pulse turn-on rate to provide more frequent sampling. System response time may be decreased without an increase in the operating frequency for the associated control device. Particular application of the present invention may be found in continuously variable transmission systems which utilize PWM-controlled electrohydraulic valves for ratio control, line pressure control and clutch control. A system for implementing the PWM signal has a duty-cycle calculator coupled with timing circuits to control input data reading functions and circuit enabling, leading edge and trailing edge regulators and an output pulse generator.

Abstract: Transmissions of synchronous digital data from a master control unit (50A) to a slave, network termination unit (50B) are via a pulse width modulated data stream including pulse width modulated binary code pulses (20, 22) with a pulse width modulated synchronization pulse (24) all of which have a preselected leading edge transition (28) at the same point in each cycle of a master clock signal. A clock signal is derived at the network termination unit (50B) from the received pulse width modulated binary data stream for decoding and for nonself-clocking, synchronous transmissions from the slave, network termination unit (50B) to the master, control unit (50A). The phase synchronization pulse (24) is employed to maintain phase sychronization between the transmission to and from the control unit (50A).

Abstract: A pulse width modulation circuit comprising a voltage control type oscillator composed of a ring oscillator which comprises a plurality of delay elements and generates a plurality of output signals having different phases respectively. The PWM circuit further comprises a tap selection circuit for selecting one signal having a phase closest to that of a specific detect signal from the output signals of the oscillator. The PWM circuit further comprises a phase shift circuit for generating a plurality of delay signals having different phases shifted by a regular time in order in response to the selection signal output from the tap selection circuit. The PWM circuit further comprises a waveform shaping circuit for forming a plurality of pulse signals having different pulse widtsh respectively from the delay signals output from the phase shift circuit. And the PWM circuit further comprises a waveform selection circuit for selecting one desired pulse signal from the signals output from the waveform shaping circuit.

Abstract: A pulse width modulation circuit includes an operation unit which generates a compensation signal based on the product of a deviation of an input signal from a first reference value and a deviation of a power supply voltage from a second reference. A level change unit changes the level of at least one of an error signal from an error amplifier and a reference wave signal generated by a reference wave signal generator in accordance with the compensation signal so that a relative level defined by a level difference between the error signal and the reference wave signal changes in accordance with the compensation signal. The pulse width modulation circuit also includes a unit for comparing the level of the error signal and the level of the reference wave signal having a changed relative level with each other and for generating a pulse width modulated signal based on a comparison result.

Abstract: A PWM circuit of programmable subframe system includes a control circuit 20 for generating control signals Cm-CO according to the number of subframes, a PWM data register 60 for storing PWM data, a comparison/correction circuit 40 for determining the sequence of connections of the counter and then comparing the value of a counter 30 with the value of the register 60 to generator overflows under the control of the control signals and also simultaneously generate correction signals, a counter 30 for determining the seqence of connections by the circuit 40 and counting-up to return th e overflows to the circuit 40, a CMP OR Gate 70 for OR operating the correction signals generated in the circuit 40, a modulator 50 for setting and resetting the output and giving correction output.

Abstract: A pulse-width modulator accepts a 7 bit binary signal input which is gated to an adder circuit. The adder is also supplied with a constant binary 1 input and has an output that is coupled to an 8 bit delay circuit that has its output coupled back to another input of the adder. The delay circuit and adder act as a recursive filter that is reset when the gate circuit is opened every 128th count. The most significant bit in the output of the delay circuit is a direct measure of the corresponding pulse width of the binary signal and is coupled to an integrating circuit.

Abstract: A modem implementation a high data transmission rate is implemented by means of pulse width modulation. The timing magnitude for each baud is weighted by the binary value of the data input. Minimal components are employed and the entire circuit is comprised of digital components except for a few analog components including a comparator for detecting transitions in the received pulse width modulation signal. This modem is particularly applicable to digital transmission of a digital video picture data via telephone lines to implement a video telephone. The video picture along with the synchronization signals from a video source are digitized and stored in a memory. The video telephone operates by sending and receiving by pulse width modulation both the video data and the synchronization signals.

Abstract: Apparatus and method for remotely controlling electrical loads having resistive or complex impedances. The apparatus features a controller having a transmitter and a companion receiver. The transmitter is preferably hand-held and includes a command generator at which commands are selected; a modulator responsive to the command signals for generating modulation signals containing the load control information; an oscillator responsive to the modulation signals for generation short-duration bursts of r.f. carrier whose positions in time convey the load control information; and an antenna for radiating the modulated, r.f. carrier.

Abstract: An apparatus is provided which is responsive to a multiple bit sample of digital information for producing a pulse width modulated signal, the apparatus comprising: a first signal match detector, responsive to a first subset of the multiple bit sample, for producing a first signal that can transition between first and second logical states; a second signal match detector, responsive to a second subset of the multiple bit sample, for producing a second signal that can transition between the first and second logical states; and a voltage summing circuit for producing a first voltage that is substantially proportional to a magnitude of the first signal in one of the first logical state and the second logical state and for producing a second voltage that is substantially proportional to a magnitude of the second signal in one of the first logical state and the second logical state and for producing an output voltage that is substantially proportional to a sum of the first voltage and the second voltage.

Abstract: A PWM waveform generator generates the digitized waveform which may control an inverter so that the inverter output is pulse width modulated and generates a sine wave after filtering. A frequency controlling means includes a cycle clock cycling an address counter which addresses step data in a ROM, and the ROM data is fed to a PWM counter. This PWM counter has a clock input to reset a flip-flop and the output passes through a polarity switch to obtain the digitized waveform. This frequency controlling means is modified by an amplitude controlling means wherein the PWM counter is clocked at a variable frequency rate to control the width of the pulses directly proportional to the desired effective amplitude of the output waveform. The foregoing abstract is merely a resume of one general application, is not a complete discussion of all principles of operation or applications, and is not to be construed as a limitation on the scope of the claimed subject matter.

Abstract: An image processing apparatus comprising a pixel data output for releasing pixel data, synthesis means for synthesizing a plurality of pixel data released from the pixel data output, a pattern signal generator for generating a pattern signal of a predetermined period, and means for forming a pulse-width modulated signal by utilizing the synthesized pixel data released from the synthesis means and the pattern signal.

Abstract: An RF-AM transmitter of the type including a power pulse amplifier driving an RF amplifier with a modulating voltage via a low pass filter includes a pulse width modulator for deriving variable frequency pulses having a frequency that is a direct function of an RMS like function of the amplitude and frequency of an information source; the width of the pulses is determined by the instantaneous amplitude of the information signal source. The pulse width modulator includes a constant amplitude, variable frequency triangular wave voltage controlled oscillator responsive to a DC signal representing the frequency and amplitude of the information source. In response to amplitude crossovers between the variable frequency triangular wave and the information source, transitions in the pulse width modulated wave are derived.