Abstract: An object of the present invention is to provide a digital amplifier which is capable of preventing a reproduction of an analogue audio signal from a loud speaker, when an output sound volume from the loud speaker is set to zero and when inputting of a digital audio signal or an input signal is stopped. In order to achieve the object, in the digital amplifier of the present invention, a silent PWM signal output section 7 outputs a PWM signal having a duty ratio of 50%, instead of a PWM signal generated by the PWM signal generating section 6, in the following cases: the factor detecting section 3 detects that the digital audio signal is multiplied by the factor “0” in the gain regulation section 2, the silent signal determining section 4 determines that the signal input from the reproducing unit 13 is stopped, and the silent signal determining section 4 determines that the digital audio signal is a signal at a silent level.

Abstract: A fractional N synthesizer is disclosed. The synthesizer includes a phase detector that receives first and second input signals and generates a pulse width modulated (PWM) output signal having a pulse width indicative of the phase relationship between the input signals. A pulse-width-to-amplitude (PW/A) conversion circuit connected to a loop filter where the conversion circuit receives the phase detector output signal and generates a PW/A output signal having an amplitude indicative of the phase detector output signal pulse width. The phase detector output signal may comprise a periodic series of pulses having varying pulse widths and the PW/A output signal amplitude changes at the end of each pulse to reflect the corresponding pulse width. The conversion circuit may include a current circuit connected to a capacitor, where the current signal receives the phase detector output and sources a constant current during a charging phase of the phase detector output signal.

Abstract: In a modulation system,.in order to provide a two-level signal with a desired modulation which is suited to be amplified by a switching mode power amplifier, the modulation system may include a first constant envelope modulator modulating a signal according to a first control signal, a second constant envelope modulator modulating a signal according to a second control signal, and a combining portion combining the output signal of the first and said second constant envelope modulator to a single, two-level pulse-width-modulated signal. The information which is to be represented by the modulation of the single, two-level pulse-width-modulated signal is coded in the first and the second control signals. The invention relates equally to a corresponding method for generating a modulated signal.

Abstract: A digital technique for pulse width modulation (PWM) utilizes a tapped delay line 304 receiving a reference clock and generating a plurality of time delayed reference clock transitions having finer time resolution than the reference clock signal. A multiplexer 120 receives the plurality of time delayed reference clock transitions as an input thereto and producing an output when one of the plurality of time delayed reference clock transitions is addressed. An accumulator circuit 524 generates control timing signals associated with the input signal sampling rate Fsample that are used to select outputs from the delay line 304 representing a pulse width modulated output signal.

Abstract: A variable aperture coding/decoding system suitable for use in a spread spectrum system provides multiple phase coding of an input NRZ bitstream. Each bit of a coded output signal is coded to encompass a predetermined different number of clock periods depending on the logic level of the input signal. A coded bit exhibits a predetermined reference number of clock periods, eg., 9, when the input signal does not exhibit a logic level transition. When the input signal exhibits a phase change from a 0 to a 1 logic level, the bit width of an associated coded bit is increased by 1 clock period, to 10 clock periods. When the input signal exhibits a phase change from a 1 to a 0 logic level, the bit width of an associated coded bit is decreased by 1 clock period, to 8 clocks periods. Thus the coded output signal may contain three types of information represented by a bit width change proportional to predetermined factor N.

Abstract: To correct for any source of non-linearity and noise introduced in the power amplification of a pulse modulated signal, a correction unit is applied in-between the pulse modulator and the switching power amplification stage. The correction unit is controlled to have a compensating effect, by introducing continuous delays on the individual pulse edges on the basis of error information provided by an error processing block. One preferred embodiment of the invention comprises: a Correction Unit with means to control the delays of the individual pulse edges as a function of a control input signal Ve; a state feedback block A with compensation; a reference shaping block R to modify the pulsed reference vr for optimized error estimation; a difference block to generate an error signal and a compensator C to shape this error.

Abstract: A pulse width modulation circuit of the present invention includes: pulse generation means being provided with a first power supply and charged with a first current and a second current between which a constant current is distributed to turn ON/OFF a switching element, thereby generating a pulse from a first output section; pulse modulation means for controlling the charging while controlling a distribution ratio between the first current and the second current based on an input signal, thereby changing a pulse width of the output pulse; and first short circuit means for shorting the first output section with the first power supply when the pulse being output from the first output section transitions to a voltage of the first power supply.

Abstract: A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an ‘open-loop’ tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

Abstract: A digital data modulator is coupled to a source of a digital data signal having a data bit period, and a source of an auxiliary data signal. An encoder encodes the digital data using a variable pulse width code having edges occurring in an interval within the data bit period. A pulse signal generator, generates respective pulses representing the edges of the encoded digital data signal. A carrier signal generator generates a carrier signal having carrier pulses corresponding to the respective pulses during the interval, and modulated by the auxiliary data signal otherwise. A digital data demodulator is coupled to a source of a modulated signal including successive bit periods, each having a first interval containing a carrier pulse, spaced relative to other carrier pulses, to represent a variable pulse width encoded digital data signal, and a second interval during which the carrier is modulated with an auxiliary data signal.

Abstract: A method for driving at least one inductive load using pulse width modulated control signals, via a PWM control unit, the control pulses of the PWM control signals connecting the load to and disconnecting it from a d.c. supply voltage via a semiconductor output stage. To prevent the formation of an a.c. voltage occurring on the d.c. supply voltage in the case of pulse-wise loading of the same by the PWM control signal, the PWM control unit is assignable a supplementary device including a storage capacitor and/or storage inductor having a semiconductor switch, and the semiconductor switch is controllable by the PWM control unit switch on one charging current circuit powered by the d.c. supply voltage for the storage capacitor and/or the storage inductor.

Abstract: A PWM control circuit, microcomputer and electronic equipment which can generate high-resolution PWM signals through a small-sized scale of circuit. The PWM control circuit includes a PWM period value setting register, a counter, an edge-point value setting register, a PWM output circuit for varying the level of the PWM signal at a first edge-point, and a delay value setting register provided on low order side of the edge-point value setting register, for specifying a delay time of the first edge-point. The PWM output circuit delays the first edge-point by a period smaller than one clock period of CLK, in accordance with the value in the delay value setting register. This can improve the resolution of the PWM signal. One-bit or two-bit value is stored in the delay value setting register. Based on the stored value, the first edge-point can be delayed by 1/2, 1/4, 2/4 or 3/4 clock period.

Abstract: When pulsewidth modulation is performed with a digital data pattern, appropriate pulsewidth modulation is performed in accordance with variations of a device or a driving system. In a case of inputting data where one pixel is expressed by, e.g., 4 bits (16 tones), a 32-bit pattern having twice as many number of bits as a 16-bit pattern is prepared as a pattern corresponding to input data, and stored in digital data output unit 1001. Pulsewidth addition circuit 1007 is provided for adding a fine-adjustment pulsewidth so as to achieve a target amount of light. The pulsewidth addition circuit 1007 is set so as to achieve a minimum pulsewidth that can generate a laser beam when input data is 0.

Abstract: A pulse width modulation integrated circuit (PWM IC) chip available as an 8-pin DIP or a 14-pin SOP package is characterized by simplified circuit complexity, high package density, more voltage regulation functions and more pin functions. The PWM IC of the present invention uses several internal control circuit to create and define the pin functions thereof and is capable of controlling the switch of the internal power control circuit therein, modulating the operation frequency of the PWM IC, accomplishing the voltage feedback operation of the power supply, sensing the external current and increasing the pulse width of the output pulse signal tardily as the PWM IC starts up. More specifically, because the PWM IC of the present invention employs internal current sources to create and define the pin functions thereof, the PWM IC can be equipped with less pin numbers, simpler circuit complexity and higher package density.

Abstract: A method and drive unit for controlling a modulator (128) in which the working point of the modulator (128) is regulated using a regulating circuit (124) in such a way that the working point is stable in relation to the transmission characteristic curve of the modulator (128) for a long time and under different operating conditions.

Abstract: The present invention relates to a modulation device MD, which is designed to produce an output signal Vout comprising a succession of pulses. According to the invention, a device of this type includes: two transistors T1 and T2, which are arranged as a differential pair; a capacitive element C, which is connected between the two transistors T1 and T2; adjusting means LC1, LC2, UC1, UC2, in order to adjust the potential of at least one of the terminals of the capacitive element C; and comparing means CMP, which supply the output signal Vout, which is representative of the sign of the voltage Vc, which is present at the terminals of the capacitive element C. By means of a simple and substantially analog structure, the invention permits rapid, flexible control of the width of the pulses of the output signal Vout.

Abstract: A pulse width modulation (PWM) circuit has a PWM output signal that features accurate timing even in the face of interference imposed upon the control signal representative of the desired PWM duty cycle. The PWM circuit includes or has a first or switching section and a second or analog section. The second section has an operational amplifier with a summing circuit that sums two input signals, namely a triangular wave signal and the control input signal, and then amplifies the summed signal to produce a trapezoidal waveform output delivered to the second section. The first section features a two-input comparator that produces a PWM signal output with a fast transition in response to trapezoidal output fed as an input and compared to a stable reference signal. Due to the speed of the op amp, timing errors on the PWM output signal due to interference on the control signal are minimized.

Abstract: A control signal (66, 70) for an amplifier (42, FIG. 6) can be switched between a high and a low level to control the shape of the pulse envelope (64, 68) of the amplifier output signal. The duration over which the control signal attains its high level is varied to control the shape of the envelope.

Abstract: An integrated circuit includes a frequency prescaler for producing an infrared transmission carrier; a duty-cycle selector for adjustably setting the carrier's duty cycles; as well as a pulse generator and hardware modulator to generate a signal of desired waveform for infrared transmission. The integrated circuit also includes a multiplexer for receiving the signal of desired waveform from the hardware modulator and a data output signal in producing a selected output signal responsive to a control signal. The integrated circuit further includes an output buffer coupled to the multiplexer for transferring data to an output terminal.

Abstract: A DC brushless motor operation speed control method is disclosed. First, a linearly voltage dependent current source is used to charge a capacitor and the terminal voltage of the capacitor is coupled to a linearly voltage dependent base frequency level detector. When the output voltage of the capacitor reaches the base frequency reference voltage, the signal output from the base frequency level detector will make the capacitor discharge, outputting a series of base frequency triangular waves. Under different supply voltages, all the generated base frequency triangular waves have the same cycle time. The base frequency triangular waves are transmitted to a speed control comparator. Through pulse width modulation, the speed control reference voltage adjusts the output pulse width of the comparator and thereby controls the speed of the motor.

Abstract: A pulse width modulation circuit of the present invention includes: pulse generation means being provided with a first power supply and charged with a first current and a second current between which a constant current is distributed to turn ON/OFF a switching element, thereby generating a pulse from a first output section; pulse modulation means for controlling the charging while controlling a distribution ratio between the first current and the second current based on an input signal, thereby changing a pulse width of the output pulse; and first short circuit means for shorting the first output section with the first power supply when the pulse being output from the first output section transitions to a voltage of the first power supply.

Abstract: A method is provided for driving a load in a pulse width modulation (PWM) mode as a function of numeric command values having a predetermined number of N-bits. The method includes the step of incrementing by more than a unit the number of bits on which a selected command value is mapped, wherein a unit equals N-bits plus a plurality of additional bits. The N most significant bits of the selected command value are converted. The plurality of additional bits are decoded by generating a corresponding plurality of intermediate levels of variation in the duty cycle. Each intermediate level has a duration of half a clock period and produces a plurality of signals out of phase among each other by half a clock period. A driving PWM signal is generated by multiplexing the signals out of phase among each other by half a clock period, and carrying out logic combinations of these signals as a function of a most significant bit of the selected command value and as a function of the plurality of additional bits.

Abstract: A modulated signal source for implementing A modulated signal method of a generating a modulated signal having a radio frequency based upon a linear mixing of signals is disclosed. An in-phase pulse signal modulator of the modulated signal source provides an in-phase pulse modulated signal in response to a reception of a baseband in-phase signal and an in-phase clock signal with the in-phase clock signal and the in-phase pulse modulated signal being synchronized. A quadrature pulse signal modulator of the modulated signal source provides a quadrature pulse modulated signal in response to a reception of a baseband quadrature signal and a quadrature clock signal with the quadrature clock signal and the quadrature pulse modulated signal being synchronized.

Abstract: A Pulse Width Modulated power amplifier which has a random or pseudo-random comparator switching mechanism for reduced distortion and radiated RF emissions is disclosed.

Abstract: A digital signal modulator modulates a digital input signal to drive a load, such as an opposed current amplifier or other opposed current converter. The combinations of frequency relationships and digital signal modulator elements provide significant digital signal processing capabilities and flexible output signal timing. In one embodiment, a digital signal modulator modulates a digital input signal. Even and odd samples of the input signal propagate along two respective channels (signal paths), which include further digital processing capabilities, such as pulse width modulation, to generate output signals appropriate for the topology of a load. Additionally, a bias signal may be modulated with the digital input signal. By utilizing digital signal processing to modulate the input signal, various processing technologies are applied to the input signal. For example, noise shaping may be implemented using a delta-sigma modulator as an input stage to the two channels.

Abstract: Pulse width modulation of a digital signal using a nonlinear type of pulse generator is described. The nonlinear pulse generator is characterized by its transfer characteristic which has alternating stable and unstable operating regions. The pulse width modulated signal is generated by varying the operating point between among the unstable and stable operating regions.

Abstract: Method for controlling the operating range of a modulator, and an associated drive unit, the operating range of the modulator being controlled via a control circuit such that the operating range is stable over a long period of time and in different operating conditions, relative to the transmission characteristic of the modulator.

Abstract: A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor.

Abstract: A device for implementing a method for generating a pulse width modulated signal based upon a natural sampling technique is disclosed. First, a complex baseband signal is received by the device. Second, the device computes a first pulse edge vector and a second pulse edge vector as a function of the baseband signal. Third, the device computes a first set of natural sampling points as a function of the first pulse edge vector and computes a second set of natural sampling points as a function of the second pulse edge vector. These computations can involve one or more detections of a jump k&pgr; within the first pulse edge vector and/or the second pulse edge vector. Finally, the pulse width modulated signal is generated with pulse edges corresponding to the first set of natural sampling points and the second set of natural sampling points.

Abstract: An object of the present invention to provide a pulse width modulation waveform generating circuit that it is possible to reduce circuit size and power consumption. A pulse width modulation waveform generating circuit comprises a ring oscillator having 64 pieces of inverters connected in series, inverters connected to output terminals of odd numbered stages of inverters in the ring oscillator, a multiplexer, a change detecting circuit, and an RS flip-flop. The multiplexer is supplied with output signals of even numbered stages of the inverters in the ring oscillator and output signal of the inverter. One of their signals is selected in accordance with logic of a digital signal. The RS flip-flop is set at time an edge detecting pulse is outputted from the change detecting circuit, and is reset at time an edge detecting pulse is outputted from the change detecting circuit.

Abstract: A circuit for generating a pulse-width-modulated signal comprises a phase-locked loop (PLL) having a duty-cycle-insensitive phase comparator and a Sigma-Delta pulse width modulation circuit suitable for providing the voltage-controlled oscillator function of the PLL. Thereby, frequency of the signal generated is synchronized by the PLL to the specified frequency of a synchronization signal, and is thus independent of the duty cycle.

Abstract: When a PWM signal is generated by PWM generators which are provided for the number of channels, each PWM generator outputs the PWM start schedule data showing the timing of startup of the PWM signal to the CPU. When the number of PWM signals which start at substantially the same time exceeds a predetermined number on the basis of the PWM start schedule data, the CPU outputs delay setting data with respect to a channel corresponding to a portion exceeding the predetermined number to the PWM generator as the one showing that the generation of the PWM signal is to be delayed. The PWM generator delays the PWM signal, when the delay setting data shows a delay. As a result, a multi-channel pulse width modulation apparatus which can prevent a decrease in the operational reliability due to simultaneous start of the pulse width modulation signals can be provided.

Abstract: A device for transmitting a pulse signal via a metallic line to a receiver end at which equalization is applied to the received pulse signal. The device includes a waveform adjustment unit which adjusts a pulse width in accordance with differences between characteristics of the metallic line and characteristics that are assumed for the equalization at the receiver end. The device further includes a transmission driver unit which transmits a pulse having the adjusted pulse width to the metallic line.

Abstract: A PWM (Pulse Width Modulation) circuit of the present invention includes a reference pulse sequence generating section for outputting a reference pulse sequence, an up-down counter, a trigger signal generating section for generating from an input signal a trigger signal for the up-down counter having a period which is a natural number multiple of one cycle the period of PWM, and a comparator for comparing the output of the up-down counter and the reference pulse sequence.

Abstract: A pulse width modulation integrated circuit (PWM IC) chip available as an 8-pin DIP or a 14-pin SOP package is characterized by simplified circuit complexity, high package density, more voltage regulation functions and more pin functions. The PWM IC of the present invention uses several internal control circuit to create and define the pin functions thereof and is capable of controlling the switch of the internal power control circuit therein, modulating the operation frequency of the PWM IC, accomplishing the voltage feedback operation of the power supply, sensing the external current and increasing the pulse width of the output pulse signal tardily as the PWM IC starts up. More specifically, because the PWM IC of the present invention employs internal current sources to create and define the pin functions thereof, the PWM IC can be equipped with less pin numbers, simpler circuit complexity and higher package density.

Abstract: The present invention monitors the average switching frequency at the output of the comparator and adjusts the delay compensation accordingly. That is, the switching frequency monitoring circuit looks at the average switching frequency and maintains the average switching frequency in a “frequency zone” which corresponds to a high elbow and a low noise floor.

Abstract: When pulsewidth modulation is performed with a digital data pattern, appropriate pulsewidth modulation is performed in accordance with variations of a device or a driving system. In a case of inputting data where one pixel is expressed by, e.g., 4 bits (16 tones), a 32-bit pattern having twice as many number of bits as a 16-bit pattern is prepared as a pattern corresponding to input data, and stored in digital data output unit 1001. Pulsewidth addition circuit 1007 is provided for adding a fine-adjustment pulsewidth so as to achieve a target amount of light. The pulsewidth addition circuit 1007 is set so as to achieve a minimum pulsewidth that can generate a laser beam when input data is 0.

Abstract: Apparatus and methods are disclosed for adding minimum pulse widths to the coarse resolution output of a multi-reference switching amplifier. This acts to null any detectable resultant differential by addition of a dynamic offset pulse width to the fine resolution output; thus extending operation to zero while presenting the imposed minimum pulse widths as a common-mode (null) signal. A preferred method according to the invention includes the steps of separating the input signal into coarse and fine resolution outputs, adding a minimum pulse width to the coarse resolution output; and adding a dynamic offset pulse width to the fine resolution output so as to null differential signals which would otherwise be present across the load. In terms of circuitry, a data separator is employed for separating the input signal into coarse and fine resolution outputs, and a summer adds the minimum pulse width to the coarse resolution output.

Abstract: A processor that has pulse width modulation generation circuitry that provides an improved capability to deal with fault conditions, and particularly with multiple concurrent fault conditions, occurring in external circuitry and devices that are connected to PWM hardware included in a processor.

Abstract: A pulse-width-modulated signal is generated out of a sampled reference signal. The least significant bits of a sample of the reference signal are stored in a comparison register. At the same time, a check is made in a test circuit to find out if the sample considered corresponds to a maximum amplitude of the reference signal. If this is the case, an overflow bit is given. The overflow bit and the least significant bits of the sample considered are then linked together to obtain a comparison word. The comparison word is compared with a number given by the counter to generate the pulse-width-modulated signal.

Abstract: Configuration bits are provided that configure PWM outputs of a processor incorporating a PWM module. The configuration bits cause the PWM module to put the PWM outputs into tri-state, active high or active low modes when the PWM module is inactive or when individual PWM outputs are not enabled. The configuration bits are stored in non-volatile memory and perform the configuration after power-up of the processor and after a reset when the PWM module is generally in an inactive state.

Abstract: A device for transmitting a pulse signal via a metallic line to a receiver end at which equalization is applied to the received pulse signal. The device includes a waveform adjustment unit which adjusts a pulse width in accordance with differences between characteristics of the metallic line and characteristics that are assumed for the equalization at the receiver end. The device further includes a transmission driver unit which transmits a pulse having the adjusted pulse width to the metallic line.

Abstract: An apparatus for and method of generating a signal having a programmable period and a programmable duty cycle. The apparatus includes an update sequencer circuit. The update sequencer circuit is configured to detect an updated period value and an updated duty cycle value, and to receive a period match signal, and in accordance therewith selectively generate a period write signal and a duty cycle write signal. A storage element is configured to receive the updated period value, the updated duty cycle value, the period write signal, and the duty cycle write signal, and in accordance therewith replace a period value with the updated period value and a duty cycle value with the updated duty cycle value. The update sequencer circuit eliminates the requirement for associated software to have a polling loop or an interrupt.

Abstract: Two oscillators, such as in two pulse width modulator circuits of DC to DC power converters, are maintained in synchronization and at a predetermined phase shift from one another by a circuit incorporating a comparator. A sawtooth signal output from the master oscillator is fed to one comparator input while the sawtooth signal is filtered and applied to the second input of the comparator to generate an approximately 180° phase shift turn-on at the output of the comparator that is fed through a driver circuit to an input of a second oscillator. By insuring that the faster operating oscillator is the master, the slave oscillator will be triggered by the signal from the master.

Abstract: The present invention is related to an improved architecture of an integrated circuit with remote transmission function. For no additional carrier circuit is needed, for example in a preferred embodiment, an infrared signal is served as the medium for remote transmission to connect with other interfaces, so as for integration design of the infrared transmission arrangement and the integrated circuit, thereby saving elements in hardware design and the time and costs for design, and improving the working efficiency. Furthermore, a multiplexer receives a select control signal to control the output type, so as for the pin of the integrated circuit for remote transmission applicable for general input/output port in other situations in addition to the infrared transmission.

Abstract: A digital to analog converter is provided. The converter includes a multi-bit counter, a first and a second plurality of logic gates coupled to the multi-bit counter, a digital input selectively coupled to the first and second plurality of logic gates. The converter further includes a first AND gate coupled to an output of the first plurality of logic gates and a second AND gate coupled to an output of the second plurality of logic gates. In addition, the converter includes a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter and a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.

Abstract: A pulse width modulation apparatus and method operates a switch at one of four slew rates to minimize electromagnetic and harmonic interference or switching losses. One of the four slew rates is selected based on a detected over-current condition, with or without a start up operation condition, an over-temperature condition and a normal working mode.

Abstract: A method and apparatus to produce a pulse width modulated (PWM) signal from pulse code modulated (PCM) data. In one embodiment, a crossing point of an analog signal with the ramp portion of a sawtooth waveform is approximated by first extrapolating, or projecting, a line between two adjacent sample points across other sample points to produce an estimate of the crossing point. A magnitude difference between a crossing point of the extrapolated line and a sample point magnitude on each side of the crossing point is determined. The magnitude difference, multiplied by an empirically determined constant, is added to the estimate. A PWM signal is then produced using the estimate for the crossing point.

Abstract: A modulation circuit and an image display able to be set to match the relation of luminance data and a luminance of a LED with a &ggr;-characteristic of a CRT without increasing the bit length of the luminance data or performing pre-processing, such as making corrections to the luminance data. By the A/D converter, the digitalized luminance data is converted into serial data by the controller and is output to pulse width modulation circuits in cascade connection. In each pulse width modulation circuit, a pulse current of a pulse width corresponding to the luminance data is generated, and the LED connected to each pulse width modulation circuit is driven by the current to emit light. Further, the amplitude of the pulse current is variable in accordance with the count of a counter for counting clock signals in the period of the pulse current. As a result, the relation of the time-averaged pulse current flowing in the LED and the luminance data can be made to match the &ggr;-characteristic of a CRT.

Abstract: A pulse-width modulation technique uses a counter load value that alternates between a duty-cycle defining value and its complement. In one embodiment, a pulse-width modulated signal is produced as a function of a control signal used to reload the counter in response to the counter reaching an overflow threshold value. This approach includes storing the counter load value and counting relative to a logic circuit output value which corresponds to either the load value or its complement. The counting is reinitiated using the logic circuit output in response to the counter reaching an overflow threshold value. A specific example application of the above type of PWM approach is directed to implementation in otherwise conventional up/down digital counters such as exists in 80C51-type microcontrollers.

Abstract: A pulse width modulator (PWM) circuit is provided. The PWM circuit includes a selective synchronization circuit configured to receive vector signals, and selectively synchronize the vector signals. The synchronized vector signals are provided to a tap selection circuit configured to output tap selection signals that are logically combined by a transition generating circuit to produce a pulse width modulated signal based on logically detected transitions in the tap selection signals.