Abstract: A method is provided for generating a pulse signal with modulable-width pulses. A set-point signal is generated and compared with a control signal so as to produce the pulse signal. When the control signal is a two-state logical signal, a first reference voltage is taken as the set-point signal. When the control signal is a continuous analog voltage, the set-point signal is varied between the first reference voltage and a predetermined second reference voltage, which is higher than the first reference voltage. Also provided is a device for generating a pulse signal with modulable-width pulses. The device includes a set-point signal generator, a control signal generator, and a comparator that outputs the pulse signal. The set-point signal generator includes a first voltage source for generating a first reference voltage, and a second voltage source for generating a second reference voltage, which is higher than the first reference voltage.

Abstract: A pulse width modulation (PWM) amplifier of the type including power transistors connected in totem-pole fashion and a bootstrap capacitor used to bias at least one of the power transistors into the conductive state. The improvement wherein the bootstrap capacitor is refreshed only to the extent needed to provide a higher effective maximum duty cycle.

Abstract: A phase-locked loop applied as a phase modulator using an external analog control signal whereby a single-ended pulse-width modulated digital signal may be derived from the phase detector output, and two phase modulated square-wave digital signals may be derived from a reference oscillator and the feedback voltage controlled oscillator. The pulse width modulation and/or phase modulation in power applications can be achieved with far greater speed, precision, simplicity and economy than by existing techniques.

Abstract: In a double-sided pulse width modulator, an amplifier has a first input connected to a first reference potential, a second input, and an output. A first bank of storage elements have a first terminal connected to the second input of the amplifier, and a second terminal. A first bank of switches have an output terminal connected to a second terminal of the storage elements, an input terminal, and a control terminal connectable by a timing gate to an output of the modulator and a polarity control bit for a first value to be input into the input terminals. A feedback storage element is connected in parallel with a first timing switch between the second input of the amplifier and the output of the amplifier. A comparator has a first input connected to a second reference potential, a second input, a timing enable input, and an output. A second bank of storage elements have a first terminal connected to the second input of the comparator, and a second terminal.

Abstract: Method and device for generating bit information in a subscriber station of a bus system, in particular of the bus of the EIBA, essentially symmetrical AC voltage information being superposed as bit information on a DC voltage of the bus in that a DC voltage potential (19) of a line under inductive loading (9) is pulled, in each case in an active pulse (20) to the potential of another line and an equalizing pulse (22, 23) is formed with subsequent energy recovery. It is provided that the active pulse (20) of the bit information at a bit frequency is formed from individual pulses (17) of higher frequency.

Abstract: A circuit suitable for use in a regulated bi-directional output power supply requiring controlled transitions between states, such as in a Battery Polarity Switch is provided to utilize many of the same circuit components in regulating both opposing polarities of the output signal. An exemplary circuit achieves use of a single error amplifier and pulse width modulator circuit to obtain both positive and negative regulation of the battery polarity switch output, along with controlled transition between the two states. In a specific embodiment a logic inverter allows the single pulse width modulator to control in both directions. A ramped reference fed to the error amplifier allows the same amplifier to control the transitions.

Abstract: An integrated pulse-width modulation circuit with conditional temperature protection circuitry includes logic circuitry, a power output device, thermal shutdown circuitry to disable the power output device when the die temperature exceeds a predetermined limit, and a masking circuit that disables the thermal shutdown circuit during short term thermal increases such as those that occur when an inductive load turn off event takes place.

Abstract: A pulse width modulation type power supply modulator capable of operating at high switching frequencies (>10 MHz) is achieved by eliminating resonant circuits which limit the maximal switching frequency. The modulator includes a power circuit including a power transistor, a first control circuit connected to the gate of the power transistor and a second control circuit connected to the output of the power circuit. In a preferred embodiment the active components are isolated from each other by areas of metalization on a printed circuit to minimize unwanted coupling and the electrical lengths are minimized.

Abstract: A digital-to-analog converter includes a digital-to-pulse width converter that converts a desired digital set-point value to a corresponding signal having a pulse width indicative of the desired set-point value. The desired set-point value is fed to a comparator which compares that value to the current count value from a counter that is counting up in ascending integer order. However, instead of presenting the counter output signal lines to the comparator in a normal conventional manner wherein the count value of the counter is presented to the comparator in the conventional ascending integer order, the current value of the counter is presented to the comparator in other than a conventional ascending order. The result is a comparator output signal that transitions more than one time between binary logic levels. This effectively increases the frequency of the comparator output signal.

Abstract: The present invention an apparatus provides a pulse width modulated signal to a load in response to an input signal. The apparatus receives the input signal and a feedback signal, determines a difference between the received signals, integrates the difference, and responsively produces an error signal. The error signal is compared with a reference wave signal and a correction signal is produced. The apparatus produces the pulse width modulation signal by conditioning the correction signal. The apparatus determines the feedback signal by attenuating the pulse width modulation signal in a manner similar to the attenuation caused by the load.

Abstract: A pulse width modulation apparatus outputs an output pulse having an arbitrary width with respect to an arbitrary point in a pulse period. A delay means associated with a pulse cycle have multi-stage delay output means. Before a control pulse CLKP is fed to each of multi-stage delay output means, a delay time for the delay output means can be set. A rising or falling to be latched by a latch means is controlled based on delay control pulses obtained by the delay output means. An output pulse having an arbitrary pulse width with respect to an arbitrary point can be supplied without occurrence of an offset pulse or a blank duration at the start of each pulse duration.

Abstract: A pulse width modulation circuit apparatus of a digital type using a delay circuit and a decoder, which is provided with a delay control circuit for driving the reset-set type flip-flop of a last output stage and which provides the flip-flop with a mode determination function, whereby the range of the operation frequency is broadened, the generation of a blank pulse and offset pulse can be suppressed, and a higher precision gradation expression can be realized.

Abstract: A pulse width modulator generates a linear sawtooth ramp waveform from a pulse signal to compare against an amplified input signal derived from a transducer output voltage signal. A first circuit generates the linear ramp waveform in response to the pulse signal. First and second amplifiers receive the differential transducer signal and provide the amplified input signal to one input of a comparator. The comparator has another input receiving the linear ramp waveform, and an output for providing a pulse width modulated output signal having a duty cycle proportional to the differential transducer signal. If the amplified input signal is greater than the sawtooth ramp then the output signal of the pulse width modulator goes to one state; otherwise, the output signal goes to an opposite state. The pulse width of the output signal is thus linearly proportional to the amplitude of the transducer output signal.

Abstract: A pulse width modulating circuit including a shift register and a subtraction circuit, with first and second binary counters respectively connected to the outputs of the shift register and the subtraction circuit, and a logic circuit connected to the outputs of the binary counters. Pulse width control data bits are input to the shift register and the subtraction circuit. The shift register processes the pulse width control data bits by shifting them one bit to the right and dividing the control data bits in half. The output of the shift register is also connected to the subtraction circuit and provides one-half of the pulse width control data bits to the inputs of the subtraction circuit and the first counter. A load signal is respectively applied to the first and second binary counters which are responsive thereto for sensing the left and right edges of a pulse width modulation signal based upon the outputs from the shift register and the subtraction circuit.

Abstract: A switching modulator for a microwave radar transmitter is presented. In embodiment, a string of series connected transistors is controlled from an external source for pulse modulating the cathodes of transmitter microwave tubes. The individual components of the series string can be individually switched ON or OFF in order to maintain regulation of the modulation pulse. In a second embodiment, a pulse transformer has a plurality of individual primary windings and a single secondary winding wherein the primary windings are specially wound to provide isolation between the primary windings with the flux in the secondary winding and the voltage generated in the secondary winding being proportional to the sum of the excitation of the primary windings. Each of the primary windings are individually switchable for regulating the generated output voltage at the secondary winding.

Abstract: Apparatus for transmitting and receiving a period shift keyed data stream comprises a data processor such as a microprocessor which may control the generation of the waveform as well as the determination of the bit values of an incoming signal. When the data to be transmitted comprises a plurality of data values, each data value is represented by a different predetermined frequency. Further, each data value is represented by the transmission of the predetermined frequency for a predetermined transitionary interval plus one cycle or period. One portion of the transitionary interval precedes and the remaining portion follows the one cycle. For example, the data value may be represented by a three cycle burst of frequency such that, in determining the represented data value, two cycles of transitionary interval are detected but ignored and the central cycle of the three cycle burst is timed for determining the data value by edge detection techniques.

Abstract: A privacy signal transmission system having a transmitter portion and a receiver portion. The transmitter portion digitizes an analog message signal and enciphers the digitized signal into a privacy signal before modulation and transmission to the receiver portion. The transmitter portion also extracts and modulates an analog error signal representative of the digitization error for transmission to the receiver portion. The receiver portion demodulates the digitized privacy signal and analog error signal, and after the privacy signal is deciphered and reconverted to an analog signal it is added to the received analog error to reconstitute the original analog message signal.