Abstract: Aspects of the embodiments are directed to an on-chip loop antenna and methods of manufacturing the same. The on-chip loop antenna can be carried by a semiconductor package. The semiconductor package can include a printed circuit board coupled to an integrated circuit chip. The integrated circuit chip can include a semiconductor substrate, an integrated circuit; and a loop antenna surrounding the integrated circuit. In embodiments, the semiconductor package can include a metal shield enclosing the integrated circuit chip. In embodiments, the on-chip loop antenna can be impedance matched to the impedance of the integrated circuit. In embodiments, the integrated circuit can include an antenna driver to drive the antenna differentially, the on-chip loop antenna surrounding the antenna driver.

Abstract: A method for calibrating a transceiver includes selecting one of a plurality of available calibration paths on the transceiver to be active. The transceiver includes a transmitter and a receiver. The selected one of the plurality of available calibration paths couples the transmitter to the receiver through a circuit that is external to the transceiver. A calibration signal may be provided to enable calibration of the transceiver via the selected one of the plurality of available calibration paths. The calibration signal may be received after it has passed through the selected one of the plurality of calibration paths. Characteristics of the transceiver may be measured using the received calibration signal.

Abstract: Methods and systems for calibrating a multi-mode, multi-standard transmitter and receiver are disclosed. Aspects of the method may include configuring calibration paths in a transceiver on a chip including a plurality of Tx and Rx paths. IP2 distortion may be calibrated for the Rx paths utilizing a phase locked loops in the chip and the configurable calibration paths. Local oscillator leakage, Rx path DC offset and RSSI, Tx and Rx I and Q mismatch, and Tx and Rx path filters may be calibrated utilizing the plurality of configurable calibration paths. Cutoff frequency of the filters in the Tx and Rx paths may be calibrated. Blocker signals may be mitigated by calibrating amplifier gains in the Rx paths. The calibration paths may include an envelope detector. Local oscillator leakage and I and Q mismatch may be mitigated utilizing pre-distortion generated by an on-chip digital signal processor in the Tx paths.

Abstract: The present invention relates to a method of transmitting and a method of receiving signals and corresponding apparatus. One aspect of the present invention relates to an efficient L1 signaling method for an efficient transmitter and an efficient receiver using the efficient L1 signaling method for an efficient cable broadcasting.

Abstract: A quadrature out-phasing system comprising: a first baseband signal modifier (6) arranged to receive a first baseband signal component (2) and output a first constant envelope RF carrier (12) and a second constant envelope RF carrier (14); and a second baseband signal modifier (8) arranged to receive a second baseband signal component (4) and output a third constant envelope RF carrier (16) and a fourth constant envelope RF carrier (18). The system may further comprise: a first signal combiner (500) arranged to combine the first constant envelope RF carrier (12) and the second constant envelope RF carrier (14), and arranged to output a first RF PWM signal (94); and a second signal combiner (502) arranged to combine the third constant envelope RF carrier (16) and the fourth constant envelope RF carrier (18), and arranged to output a second RF PWM signal (96).

Abstract: A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.

Abstract: A multi-channel RF receiver uses an image rejection mixer (e.g. double quadrature mixer) in the IF down conversion stage for image side band rejection (whereby use of an IF narrow band filter for image rejection may be omitted if desired) and comprises a simplified frequency synthesizer which generates both a “wandering” IF oscillator frequency and an RF oscillator frequency for the up/down conversion stages (being, for down conversion, from RF to IF and from IF to base band. The IF used for a particular RF carrier (channel) is selected so as to be both an integer (N) sub-harmonic of that RF carrier and within the operating frequency band of the image rejection mixer. Advantageously, the synthesizer comprises only one loop and one VCO, wherein the IF oscillator signal is produced from the RF oscillator signal by means of a frequency divider.

Abstract: Disclosed is method of controlling an asymmetric waveform generator including the steps of providing a reference timer signal, and generating an asymmetric waveform as a combination of a first sinusoidal wave having a first frequency and a second sinusoidal wave having a second frequency approximately twice the first frequency. The generated asymmetric waveform is sampled to obtain a set of data points, which set of data points is indicative of the generated asymmetric waveform. The method includes analyzing the set of data points in terms of at least a first function relating to an ideal sinusoidal wave of the first frequency, to determine a first set of resultant values relating to the first sinusoidal wave, and analyzing the set of data points in terms of at least a second function relating to an ideal sinusoidal wave of the second frequency, to determine a second set of resultant values relating to the second sinusoidal wave.

Abstract: There is provided a VCO having a modulation function capable of easily constituting a correction circuit which can obtain a predetermined modulation degree even when element irregularities are present. A modulation current terminal is connected to an anode side connection point of a first and a second varactor diode. A first resistor is connected between the connection point and an anode side connection point (grounding voltage) of a third and a fourth varactor diode. Voltage deciding the oscillation frequency is input from the voltage input terminal via the second resistor to the cathode side connection point of the first and the third varactor diode and via the third resistor to the cathode side connection point of the second and the fourth varactor diode. A first and a second capacitor are connected from a power source via a first and a second inductor to the cathode side of the first and the second varactor diode.

Abstract: An orthogonal frequency division multiplex (OFDM) modulator of such a system as to add guard intervals to a temporal waveform generated by modulating an input data train into a large number of (sub)carriers, conducting quadrature modulation, and outputting an OFDM signal.

Abstract: A method and apparatus for continuously calibrating the modulation sensitivity of a voltage controlled oscillator (VCO) within a modulator of a transmitter. In accordance with the present invention, the transmitter is coupled to the receiver in order to loop back the transmit signal. The present invention includes a baseband signal generator which generates a reference baseband signal of known amplitude during periods when no other baseband information is being applied to the transmitter by the user. A Signal and Reference Comparison Circuit (SRCC) receives the output from the demodulator and determines whether the VCO within the transmitter has the proper modulation sensitivity. If the modulation sensitivity of the VCO is not within a desired range, then a signal generated by the SRCC is applied to a baseband level control circuit to adjust the level of the baseband signal that is applied to the VCO.

Abstract: A digital modulator and digital demodulator with quadrature amplitude modulation (QAM) schemes, which are designed to modulate or demodulate RZ-coded baseband signals. The digital modulator comprises first to fourth roll-off filters and a first and second inverters connected to the second and fourth roll-off filters. It also comprises a parallel-to-serial converter to successively selects the outputs of the first roll-off filter, third roll-off filter, first inverter, and second inverter. A D/A converter converts the selected digital signal stream into an analog signal. The roll-off filters and inverters operate at a predetermined clock frequency, while the parallel-to-serial converter and the D/A converter work at a frequency four times the predetermined clock frequency. The digital demodulator reverses the above modulation process to reproduce the baseband signals.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which receives the baseband signal and produces a compensation signal for canceling the frequency offset error. The demodulator/decoder performs the frequency-offset error compensation digitally. The demodulator/decoder includes an A/D converter which over-samples (samples at a rate of more than two samples per symbol period) the baseband signal and converts it to digital form.

Abstract: A system for transmitting FM signals comprised of apparatus for receiving an input data signal, apparatus for precompensating the received data signal, apparatus for applying the precompensated data signal to a constant envelope modulator to provide a modulated signal, apparatus for applying the modulated signal to a power efficient non-linear amplifier and transmitting a signal resulting therefrom, apparatus for receiving the transmitted signal in an I-Q receiver, and apparatus for filtering the received transmitted signal for the precompensation, to obtain an output data signal representative of the input data signal.

Abstract: A system for transmitting FM signals comprised of apparatus for receiving an input data signal, apparatus for precompensating the received data signal, apparatus for applying the precompensated data signal to a constant envelope modulator to provide a modulated signal, apparatus for applying the modulated signal to a power efficient non-linear amplifier and transmitting a signal resulting therefrom, apparatus for receiving the transmitted signal in an I-Q receiver, and apparatus for filtering the received transmitted signal for the precompensation, to obtain an output data signal representative of the input data signal.

Abstract: An interface device interacts between a digital data terminal and a frequency modulated analog transceiver module to control data flow between the digital data terminal and the transceiver module and to adapt the transceiver module to transmit digital data signals and to communicate messages containing digital signals to the digital data terminal. The interface circuit includes a digitally implemented signal shaping circuit which samples an analog quiescent state bias signal level of a voltage controlled oscillator circuit of the transceiver module. The signal shaping circuit samples and converts the sampled quiescent bias signal level to an equivalent digital data value. The digital equivalent value is increased by and decreased by a predetermined deviation value, thereby generating equivalent values of high and low modulation bias voltage levels.

Abstract: A signal processing device is arranged to form a first output modulated signal by modulating an input information signal in accordance with a modulation carrier signal, to form a second output modulated signal by modulating the first output modulated signal in accordance with a modulation carrier signal which is identical to the above-stated modulation carrier signal, and to correct the input information signal by using the second output modulated signal. The modulation circuit of the device is thus arranged to have a minimal amount of leakage of the modulation carrier signal for the information signal, so that the device can be easily arranged as an integrated circuit.

Abstract: A voltage controlled oscillator circuit including an oscillator circuit having first and second terminals to which an external inductance is connected. A frequency control voltage (V.sub.F) is applied through a bias circuit to the second terminal for varying the center frequency. The oscillator circuit may have an AGC circuit or a modulation circuit connected to it. An output amplifier is connected with the first terminal and has an adjustable output impedance for matching the input impedance of a load circuit.

Abstract: A signal amplitude shaping circuit is interposed between a signal source and a signal input terminal of a frequency modulation circuit of a typical voice radio transmitter or transceiver unit. The amplitude shaping circuit includes a high-impedance sampling circuit which senses the steady state bias voltage at the signal input terminal during periods when no data are being transmitted. Upon receipt of a transmit-enable signal, the most recently sensed bias voltage is stored and positive and negative offset voltages are generated with respect to the stored voltage. One of the offset voltages is adjusted as a precisely determined voltage with respect to the stored voltage. The other of the offset voltages is generated by inverting the first, adjusted voltage, such that the two offset voltages are offset by equal values in opposite directions.

Abstract: Several embodiments are disclosed of a modulation equalization network associated with a phase locked loop to achieve frequency independent modulation of the VCO. The equalization network is disposed to introduce the modulation signal into the control loop ahead of the loop filter but after the phase detector output. The interposed equalization network requires only a single input port to achieve a flat modulation response thereby lending itself to a modular implementation. The modulation processing is performed totally outside the phase locked loop. The network serves to provide a boost to low frequency signals from the modulation source using an integrator network while providing a high frequency response that is essentially the inverse of the phase locked loop filter response.