Semiconductor Mounts Patents (Class 333/247)
  • Patent number: 11950474
    Abstract: One embodiment of the present invention provides a highly reliable display device. In particular, a display device to which a signal or a power supply potential can be supplied stably is provided. Further, a bendable display device to which a signal or a power supply potential can be supplied stably is provided. The display device includes, over a flexible substrate, a display portion, a plurality of connection terminals to which a signal from an outside can be input, and a plurality of wirings. One of the plurality of wirings electrically connects one of the plurality of connection terminals to the display portion. The one of the plurality of wirings includes a first portion including a plurality of separate lines and a second portion in which the plurality of lines converge.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kensuke Yoshizumi
  • Patent number: 11831089
    Abstract: An antenna substrate and an antenna module including the same are provided. The antenna substrate includes an antenna unit including first and second pattern layers adjacent to each other and disposed on different levels and a first insulating layer providing a first insulating region between the first and second pattern layers, and a feed unit including third and fourth pattern layers adjacent to each other and disposed on different levels and a second insulating layer providing a second insulating region between the third and fourth pattern layers. Each of the first and second pattern layers includes an antenna pattern, and each of the third and fourth pattern layers includes a feed pattern. The antenna unit is disposed on the feed unit. The first insulating region is thicker than the second insulating region.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: November 28, 2023
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Moon Hee Yi, Tae Seong Kim
  • Patent number: 11736102
    Abstract: A compact RF switch with improved isolation is presented. According to one aspect, the RF switch includes a basic single-pole single-throw (SPST) switch element that includes an inductor in parallel with a series FET transistor. An inductance of the inductor is selected to provide in combination with an off capacitance of the series FET transistor a resonance at a specific frequency of interest. The frequency of interest can be in-band or out-of-band, including the band's fundamental frequency or a harmonic thereof. According to another aspect, the inductor is conditionally coupled to the series FET transistor via a reduced size FET transistor. Complex RF switches can include a plurality of the SPST switch elements, each tuned to a same or different frequency of interest. According to yet another aspect, SPST switch elements in their OFF states can provide matching to an SPST element in the ON state.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: August 22, 2023
    Assignee: PSEMI CORPORATION
    Inventor: Michael P. Gaynor
  • Patent number: 11705613
    Abstract: A waveguide structure includes a first waveguide section mechanically and electrically connected by a fixed connector to a second waveguide section. The waveguide sections include a dielectric material with a ground layer and a conductor structure with a pair of elongate conductors. The fixed connector includes a dielectric material with a pair of contact pads insulated from a ground layer. The fixed connector is attached by its top side to the bottom sides of interface sections of the waveguides sections forming a ground contact. The interface sections each comprise an intermediate conductor from each of the elongate conductors at the top side to the bottom side of the dielectric material. The intermediate conductors are connected via the contact pads.
    Type: Grant
    Filed: August 29, 2022
    Date of Patent: July 18, 2023
    Assignee: SCHLEIFRING GmbH
    Inventors: Iris Metzner, Holger Steffens
  • Patent number: 11612087
    Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). The present disclosure relates to connection structure for radio frequency components and electronic device including same According to various embodiments, a connection assembly for radio frequency (RF) components may include: a first RF component including an opening section and a protrusion formed in the opening section; an elastic structure; a printed circuit board (PCB); and a second RF component connected to the PCB. The elastic structure may be disposed on a first surface of the PCB, a first surface of the first RF component including the opening section may be coupled to the first surface of the PCB, and the protrusion of the first RF component may come in contact with the elastic structure, thereby forming an electrical connection between the first RF component.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: March 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongjoo Kim, Bonmin Koo, Jonghwa Kim, Seunghwan Yoon, Youngju Lee, Jongwook Zeong
  • Patent number: 11415626
    Abstract: A method of testing a semiconductor device. An apparatus comprising a semiconductor device and a test apparatus. The semiconductor device includes an integrated circuit and a plurality of external radiating elements at a surface of the device, the radiating elements include transmit elements and receive elements. The test apparatus includes a surface for placing against the surface of the device. The test apparatus also includes at least one waveguide, which extends through the test apparatus for routing electromagnetic radiation transmitted by one of the transmit elements of the device to one of the receive elements of the device. Each waveguide comprises a plurality of waveguide openings for coupling electromagnetically to corresponding radiating elements of the plurality of radiating elements located at the surface of the device. A spacing between the waveguide openings of each waveguide is larger than, or smaller than a spacing between the corresponding radiating elements.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: August 16, 2022
    Assignee: NXP B.V.
    Inventors: Jan-Peter Schat, Abdellatif Zanati, Henrik Asendorf, Maristella Spella, Waqas Hassan Syed, Giorgio Carluccio, Antonius Johannes Matheus de Graauw
  • Patent number: 11309837
    Abstract: Systems and methods for forming a mm wave resonant filter include a lithographically fabricated high Q resonant structure. The resonant structure may include a plurality of cavities, each cavity having a characteristic frequency that defines its passband. A filter may include a plurality of resonant structures, and each resonant structure may include a plurality of cavities. These cavities and filters may be fabricated lithographically.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: April 19, 2022
    Assignee: Innovative Micro Technology
    Inventors: Christopher S. Gudeman, Abbas Abbaspour Tamijani
  • Patent number: 11302648
    Abstract: Electromagnetic interference (EMI) shielding structures for use inside an electronic system are provided, which allow access for mold compound or cables by using baffle-like features on the shield's sides and/or top, as well as methods for shielding components from EMI, or for containing EMI. The structures block external RF from sensitive components and reduce EMI emission from internal, RF generating components.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: April 12, 2022
    Assignee: OCTAVO SYSTEMS LLC
    Inventors: Masood Murtuza, Peter Robert Linder, Gene Alan Frantz
  • Patent number: 11244913
    Abstract: A semiconductor package includes a substrate, an electronic component, a dielectric layer a transmitting antenna, a receiving antenna and a FSS (Frequency selective surface) antenna. The electronic component is disposed on and electrically connected with the substrate. The dielectric layer has a dielectric upper surface. The transmitting antenna and the receiving antenna are formed adjacent to the substrate. The FSS antenna is formed adjacent to the dielectric upper surface of the dielectric layer. The FSS antenna is separated from the substrate by the dielectric layer in a wireless signal emitting direction.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: February 8, 2022
    Assignee: MEDIATEK INC.
    Inventors: Ying-Chih Chen, Yen-Ju Lu, Che-Ya Chou, Hsing-Chih Liu
  • Patent number: 11239876
    Abstract: A high-frequency module (100) includes a multilayer board (110) including a plurality of insulator layers and at least one ground conductor layer (113); in the multilayer board (110), a transmission circuit (120) that is a first circuit provided in a first region and an antenna circuit (130) that is a second circuit provided in a second region different from the first region; and shielding conductor films (151 to 156) provided on sides of the multilayer board (110) and being partially in contact with the ground conductor layer (113). The ground conductor layer (113) is not in contact with the shielding conductor films (151 to 156) in, of a side of the multilayer board (110), a portion that is closest both to the first region and to the second region.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: February 1, 2022
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Dai Nakagawa
  • Patent number: 11233336
    Abstract: A chip antenna includes a first ceramic substrate, a second ceramic substrate disposed to face the first ceramic substrate, a first patch disposed on one surface of the first ceramic substrate to operate as a feeding patch, a second patch disposed on the second ceramic substrate to operate as a radiation patch, at least one feed via penetrating through the first ceramic substrate in a thickness direction to provide a feed signal to the first patch, and a bonding pad disposed on a second surface of the first ceramic substrate opposite the first surface. A thickness of the first ceramic substrate is greater than a thickness of the second ceramic substrate.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: January 25, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ju Hyoung Park, Kyu Bum Han, Jae Yeong Kim, Jeong Ki Ryoo, Sung Nam Cho, Sung Yong An
  • Patent number: 11204588
    Abstract: A millimeter wave apparatus, with a substrate, a transceiver in a first fixed position relative to the substrate, and a gas cell in a second fixed position relative to the substrate. The clock apparatus also comprises at least four waveguides.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: December 21, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Adam Joseph Fruehling, Juan Alejandro Herbsommer, Argyrios Dellis
  • Patent number: 11049823
    Abstract: An integrated circuit package apparatus deployed with an antenna and a method for manufacturing an integrated circuit package apparatus, where the integrated circuit package apparatus includes a package substrate, an antenna, a chip, and a connection circuit. The package substrate includes at least one ground plane, the antenna is deployed on an external surface of one side of the package substrate and is located on one side of the at least one ground plane, the chip and the connection circuit are deployed on the other side of the at least one ground plane, where the antenna is isolated from the chip and the connection circuit using the at least one ground plane, and the antenna is coupled to the chip using the connection circuit and a first metal through hole in a thickness direction of the package substrate.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: June 29, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Tewei Chen, Guowen Liu
  • Patent number: 11031675
    Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) disposed on a first surface of the connection member and electrically connected to at least one wiring layer; and an antenna package disposed on a second surface of the connection member, and including a dielectric layer, a plurality of antenna members, and a plurality of feed vias, wherein the antenna package further includes a chip antenna including a dielectric body and first and second electrodes, respectively disposed on first and second surfaces of the dielectric body, wherein the chip antenna is disposed to be spaced apart from the plurality of feed vias within the dielectric layer so that at least one of the first electrode or the second electrode is electrically connected to a corresponding wire of the at least one wiring layer.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: June 8, 2021
    Assignee: SAMSUNG ELECTRO-MECHANICS CO. LTD.
    Inventors: Doo Il Kim, Yong Ho Baek, Won Wook So, Young Sik Hur
  • Patent number: 10937748
    Abstract: The disclosed systems, structures, and methods are directed to a mm-Wave communication structure employing a first transmission structure employing a first ring transition structure followed by a first ground structure and a second ground structure configured to carry a ground signal, a second transmission structure employing a second ring transition structure followed by a third ground structure and a fourth ground structure configured to carry the ground signal, a third transmission structure configured to carry a mm-Wave signal, wherein the third transmission structure begins at the center of the first ring transition structure and the second ring transition structure and the third transmission structure is coplanar with the second transmission structure, and a fourth transmission structure configured to operatively couple an IC and the first transmission layer, the second transmission layer, and the third transmission structure.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: March 2, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Houssam Kanj, Wenyao Zhai, Hari Krishna Pothula, Morris Repeta
  • Patent number: 10930994
    Abstract: The present disclosure relates to a waveguide transition arrangement (1) comprising a first ground plane (6) with a first aperture (7), a feed probe (4) that crosses the first aperture (7), a second ground plane (8) with a second aperture (9), and a waveguide resonator part (10) that has an opening (11) that faces the second aperture (9). The first ground plane (6) faces the second ground plane (8) and is positioned between the feed probe (4) and the second ground plane (8), and the second ground plane (8) faces the waveguide resonator part (10). A wall structure (12) is at least partly arranged between the first ground plane (6) and the second ground plane (8) such that a first cavity (13) is formed in an enclosed volume between them.
    Type: Grant
    Filed: October 6, 2016
    Date of Patent: February 23, 2021
    Assignee: Telefonaktiebolaget LM Ericsson (Publ)
    Inventors: Per Ligander, Ola Tageman
  • Patent number: 10896861
    Abstract: An HPA MMIC assembly includes a MMIC device coupled to a thermal spreader. A ground plane is provided on the thermal spreader and coupled to FETs in the MMIC device. The multiple levels of metal separated by multiple dielectric layers provide low-loss broad-band microstrip circuits. The thermal spreader may include diamond, an air/wire-edm spreader or a multi-layer board (MLB) with heat sink vias and ground vias.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: January 19, 2021
    Assignee: Raytheon Company
    Inventors: David D. Heston, John G. Heston, Claire E. Mooney, Mikel J. White, Jon Mooney, Tiffany Cassidy
  • Patent number: 10862201
    Abstract: The antenna module comprises a communication circuit for processing a radio signal; a shield member covering the communication circuit; a conductive strip electrically connected with the communication circuit; a dielectric integrated with the shield member and the conductive strip; and an antenna formed on an outer surface of the dielectric and electrically connected with the conductive strip.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: December 8, 2020
    Assignee: Molex, LLC
    Inventor: Shuichi Sato
  • Patent number: 10833390
    Abstract: A set of superconducting devices is interconnected in a lattice that is fabricated in a single two-dimensional plane of fabrication such that a superconducting connection can only reach a first superconducting device in the set while remaining in the plane by crossing a component of a second superconducting device that is also located in the plane. A superconducting coupling device having a span and a clearance height is formed in the superconducting connection of the first superconducting device. A section of the superconducting coupling device is separated from the component of the second superconducting device by the clearance in a parallel plane. A potential of a first ground plane on a first side of the component is equalized with a second ground plane on a second side of the component using the superconducting coupling device.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Salvatore Bernardo Olivadese
  • Patent number: 10827607
    Abstract: An electronic device includes first printed circuit board (PCB) structure including first layer including first conductive strip, second conductive strip electrically separated from first conductive strip and extending at least partially in parallel with first conductive strip, and third conductive strip electrically separated from first conductive strip and extending at least partially in parallel with first conductive strip, such that first conductive strip is between second conductive strip and third conductive strip, and second layer including first conductive layer, first insulating layer interposed between and in contact with first region of first layer and first region of second layer facing first region of first layer, second insulating layer interposed between second region of first layer abutting first region of first layer and second region of second layer abutting first region of second layer while contacting first layer, and third insulating layer interposed between second insulating layer and se
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Sungwon Park, Seungyup Lee, Hesuk Jung
  • Patent number: 10818646
    Abstract: A power device includes a frame having an electrically insulative material, an opening in the electrically insulative material, and an electrical conductor extending through the electrically insulative material. A power stage module fixed in the opening has an output terminal at a first side of the power stage module, and a power terminal, a ground terminal and a plurality of input/output (I/O) terminals at a second side of the power stage module opposite the first side. A passive component has a first terminal attached to the output terminal of the power stage module and a second terminal attached to the electrical conductor of the frame. The passive component has a larger footprint than the power stage module. The frame expands the footprint of the power stage module to accommodate mounting of the passive component to the power device. The frame has a lower interconnect density than the power stage module.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: October 27, 2020
    Assignee: Infineon Technologies AG
    Inventors: Petteri Palm, Eung San Cho
  • Patent number: 10804850
    Abstract: Systems and methods for forming a compact gas sensor include using a lithographically fabricated high Q resonator coupled to at least one of a Gunn diode and an IMPATT diode. The resonator may include a plurality of cavities filled with a sample gas. A detector coupled to the resonator may measure the amplitude of the emitted mm wave radiation.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 13, 2020
    Assignee: Innovative Micro Technology
    Inventors: Christopher S. Gudeman, Abbaspour Tamijani
  • Patent number: 10748960
    Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. In one aspect of the present disclosure, a structure includes a first and a second interconnects provided over a surface of an interconnect support layer on which superconducting qubits are provided (which could be a substrate), a lower interconnect provided below such surface, and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. The lower interconnect includes a material of the interconnect support layer doped to be superconductive. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by doping the interconnect support layer, material for which could be selected, allows minimizing the amount of spurious TLS's in the areas surrounding below-plane interconnects.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: David J. Michalak, Jeanette M. Roberts, Ravi Pillarisetty, Zachary R. Yoscovits, James S. Clarke
  • Patent number: 10748961
    Abstract: Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 18, 2020
    Assignee: Intel Corporation
    Inventors: David J. Michalak, Ravi Pillarisetty, Zachary R. Yoscovits, Jeanette M. Roberts, James S. Clarke
  • Patent number: 10734332
    Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jon Bradley Lasiter, Ravindra Vaman Shenoy, Donald William Kidwell, Jr., Mohammad Ali Tassoudji, Vladimir Aparin, Seong Heon Jeong, Jeremy Dunworth, Alireza Mohammadian, Mario Francisco Velez, Chin-Kwan Kim
  • Patent number: 10693236
    Abstract: The present application discloses embodiments that relate to an electromagnetic apparatus. In one aspect, the present apparatus includes a circuit board configured to propagate an electromagnetic signal. The apparatus also includes a waveguide configured to propagate an electromagnetic signal. The apparatus further includes a coupling port configured to couple a signal between the circuit board and the waveguide, where the coupling port has dimensions based on a desired impedance of the port.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: June 23, 2020
    Assignee: Waymo LLC
    Inventor: Adam Brown
  • Patent number: 10488587
    Abstract: A photonic integrated circuit may include a silicon layer including a waveguide and at least one other photonic component. The photonic integrated circuit may also include a first insulating region arranged above a first side of the silicon layer and encapsulating at least one metallization level, a second insulating region arranged above a second side of the silicon layer and encapsulating at least one gain medium of a laser source optically coupled to the waveguide.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: November 26, 2019
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Alain Chantre, Sébastien Cremer
  • Patent number: 10356940
    Abstract: An air-cooled antenna comprising one or more separate antenna arrays (4) and a plurality of separate respective radio transmitter and/or receiver modules (3) each adapted for generating and/or receiving radio-frequency (RF) transmissions for an antenna array associated therewith. An antenna housing (2) contains the transmitter and/or receiver modules and has a ventilation inlet (8) for receiving air into the housing to an exhaust outlet (9) for outputting the air from the housing. A ventilation driver (6) drives an air flow rate through the housing from the ventilation inlet to the exhaust outlet.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: July 16, 2019
    Assignee: BAE SYSTEMS plc
    Inventor: Adrian Thomas Rowe
  • Patent number: 10319689
    Abstract: Embodiments are provided for a packaged semiconductor device that includes a package substrate that in turn includes an embedded die configured to process a radio frequency (RF) signal; a printed circuit board (PCB) attached to a front side of the package substrate, where the PCB includes a cavity; and an antenna enabling element attached to the front side of the package substrate within the cavity, the antenna enabling element configured to convey the RF signal through the cavity.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: June 11, 2019
    Assignee: NXP USA, Inc.
    Inventors: Weng Foong Yap, Jinbang Tang
  • Patent number: 10128557
    Abstract: The present invention relates to a microstrip circuit and a chip-to-chip interface apparatus comprising the same. According to one aspect of the invention, there is provided a microstrip circuit. The microstrip circuit includes a feeding line providing a signal, a probe being connected to one end of the feeding line, and a patch emitting the signal to a waveguide. The patch is disposed in a layer opposite to a layer in which the feeding line and the probe are disposed, with a core substrate being positioned therebetween. At least one of length of the probe, thickness of the core substrate, and permittivity of the core substrate is determined based on bandwidth of a transition between the microstrip circuit and the waveguide.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: November 13, 2018
    Assignee: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Hyeon Min Bae, Ha II Song, HuXian Jin, Joon Yeong Lee, Hyo Sup Won, Tae Hoon Yoon
  • Patent number: 9955581
    Abstract: A printed circuit board (PCB) assembly includes a PCB having a core substrate, a plurality of conductive traces on a first surface of the PCB, and a ground layer on the second surface of the PCB. The conductive traces comprise a pair of differential signal traces. An intervening reference trace is disposed between the differential signal traces. A connector is disposed at one end of the plurality of conductive traces. A semiconductor package is mounted on the first surface at the other end of the plurality of conductive traces.
    Type: Grant
    Filed: January 10, 2016
    Date of Patent: April 24, 2018
    Assignee: MEDIATEK INC.
    Inventors: Nan-Jang Chen, Yau-Wai Wong
  • Patent number: 9948238
    Abstract: A harmonic mixer that suppresses the degradation of the conversion efficiency is disclosed. That harmonic mixer includes an input transmission line, an output transmission line, and two transistors connected in parallel between the input transmission line and the output transmission line. Two transistors are complementarily driven by a local signal LO and generate an output signal RF with frequencies of 2×fLO±fIF, where fLO and fIF are frequencies of a local signal LO and an intermediate signal IF.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: April 17, 2018
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Osamu Anegawa
  • Patent number: 9917348
    Abstract: A PIFA is formed using a grounding plane in a printed circuit board and a metal chassis or shield. Rather than using the printed circuit board as the separator, an air gap or other gap than the printed circuit board is formed. The transmitter and/or receiver for the antenna may be mounted to the printed circuit board. The feed pin routes signals for the PIFA from the transmitter and/or receiver to the metal chassis or shield while being isolated from the grounding plane that acts as the radiating surface of the PIFA. Standoffs supporting the printed circuit board may be used to short, and another standoff may be used as the feed pin.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: March 13, 2018
    Assignee: Cisco Technology, Inc.
    Inventor: William Murphy
  • Patent number: 9913369
    Abstract: A circuit board structure with selectively corresponding ground layers includes a first ground layer, a second ground layer, and a dielectric layer arranged between the first ground layer and the second ground layer to define a ground layer height difference between the first ground layer and the second ground layer. The first ground layer includes a plurality of non-electromagnetic shield areas. The circuit board includes a plurality of conductor wires formed thereon and selectively classified and divided into a first group of conductor wires and the second group of conductor wires. The first-group conductor wires are arranged to correspond to and electromagnetically couple to the first ground layer, and the second-group conductor wires are arranged to correspond to and electromagnetically couple to the second ground layer through the non-electromagnetic shield areas respectively, so that impedance value control is achieved.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: March 6, 2018
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Chih-Heng Chuo, Kuo-Fu Su, Gwun-Jin Lin
  • Patent number: 9893761
    Abstract: Generally, this disclosure provides systems and devices for reduction of crosstalk between routed signals. A system may include a first pair of signal lines and a second pair of signal lines and each of the pairs of signal lines include a positive signal line and a negative signal line to transmit a differential signal. The system may also include an alternating current coupling capacitor (AC cap) associated with each of the positive signal lines and each of the negative signal lines. The system may further include a routing crossover of the positive signal line and the negative signal line of the second pair of signal lines, to decrease signal crosstalk between the first and second pairs of signal lines. The routing crossover may include at least one of the AC caps.
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Xiaoning Ye, Yunhui Chu, Zhenwei Yu
  • Patent number: 9893406
    Abstract: A waveguide interface comprising a support block configured to support a printed circuit board assembly. An interface is coupled to an end portion of the support block and extends from the support block. The interface includes a slot positioned to receive at least a portion of the printed circuit board assembly and one or more holes positioned to receive attachment devices to secure the interface to a waveguide component. The support block and interface are molded as a monolithic device. A method of forming the waveguide interface, a waveguide assembly including the waveguide interface, and a method of making the waveguide assembly including the waveguide interface are also disclosed.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: February 13, 2018
    Assignee: Vubiq Networks, Inc.
    Inventor: Michael Gregory Pettus
  • Patent number: 9865648
    Abstract: Superconductive interconnection structures providing continuous, uninterrupted superconducting signal paths between a superconducting chip and a superconducting chip carrier are described. The superconductive interconnection structures employ superconducting solder bumps and pillars of Under Bump Metal (“UBM”). The superconductive interconnection structures are employed in a two-stage solder bumping process in which the superconducting chip is first bonded to a testing module for screening and then bonded to a chip packaging module for operation. Either the testing module or the chip packaging module, or both, may include a multi-chip module for carrying multiple superconducting chips simultaneously.
    Type: Grant
    Filed: December 17, 2013
    Date of Patent: January 9, 2018
    Assignee: D-WAVE SYSTEMS INC.
    Inventor: Paul I. Bunyk
  • Patent number: 9839118
    Abstract: A wide bandwidth circuit board arrangement includes two coplanar substrates separated by a predetermined gap, and at least one bond wire arranged across the gap and interconnecting a respective conducting microstrip line on a first side of each respective substrate. Further, the arrangement includes at least one open stub arrangement configured on the first side of each respective substrate, each open stub arrangement comprising a microstrip extending at an angle from an end of each conducting strip on each respective substrate. Finally, the arrangement includes a ground layer on a second side of each respective substrate, and a defected ground structure arranged on the second side of each respective substrate and laterally overlapping each respective open stub arrangement arranged on the first side.
    Type: Grant
    Filed: November 1, 2013
    Date of Patent: December 5, 2017
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Bo Zhou, Junyou Chen, Kun Liu
  • Patent number: 9668346
    Abstract: A terminal portion configured to obtain electrical connection with a printed circuit board includes a first signal pad that is formed in a first conductor layer and is electrically separated from a ground layer, a pair of first ground pads that is formed in the first conductor layer to sandwich the first signal pad and is connected to the ground layer, a second signal pad that is formed in a second conductor layer and is connected to a signal line, a pair of second ground pads that is formed in the second conductor layer to sandwich the second signal pad and is electrically separated from the signal line, a third signal pad formed in a third conductor layer, and a pair of third ground pads formed in the third conductor layer to sandwich the third signal pad. The second signal pad is wider than the third signal pad.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 30, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Mizuki Shirao, Nobuo Ohata, Nobuyuki Yasui, Hiroshi Aruga
  • Patent number: 9622340
    Abstract: A flexible circuit board includes an insulating layer, a linear signal line, a plurality of grounding lines, a metal coating layer, a circuit layer and an electromagnetic shielding layer. The insulating layer includes a first face and a second face. The metal coating layer covers the linear signal line on the first face. The metal coating layer has a thickness less than that of the linear signal line, and an electrical conductivity larger than that of the linear signal line. The grounding lines are at two opposite sides of the linear signal line on the first face. The circuit layer is on the second face. The electromagnetic shielding layer covers the linear signal line and the grounding lines. The linear signal line and the grounding lines are between the electromagnetic shielding layer and the circuit layer. A method for manufacturing the flexible circuit board is also provided.
    Type: Grant
    Filed: September 18, 2015
    Date of Patent: April 11, 2017
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., GARUDA TECHNOLOGY CO., LTD., FuKui Precision Component (Shenzhen) Co., Ltd.
    Inventors: Xian-Qin Hu, Yan-Lu Li, Wen-Hsin Yu, Ming-Jaan Ho
  • Patent number: 9514881
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate; and a plurality of parallel first conductive layers formed on the substrate. The semiconductor structure also includes a composite magnetic structure having a plurality of magnetic layers and a plurality of insulation layers with a sandwich arrangement formed on a portion of the substrate and portions of surfaces of the plurality of first conductive layers. Further, the semiconductor structure includes a plurality of first conductive vias and a plurality of second conductive vias formed on the first conductive layers at both sides of the composite magnetic structure. Further, the semiconductor structure also includes a plurality of second conductive layers formed on a top surface of the composite magnetic structure, top surfaces of the first conductive vias, and top surfaces of the second conductive vias to form at least one coil structure wrapping around the composite magnetic structure.
    Type: Grant
    Filed: July 11, 2015
    Date of Patent: December 6, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Zhongshan Hong, Xianyong Pu
  • Patent number: 9515385
    Abstract: A coplanar waveguide (CPW) apparatus comprises a substrate having a first surface and an opposing second surface. The substrate comprises a metal layer proximate to the first surface. The metal layer comprises a conductive trace comprising a signal line coupled to a launcher element at a first end of the signal line, and a ground plane co-planar with the conductive trace. The ground plane defines a substantially rectangular first region surrounding the launcher element and defining a second region surrounding the signal line, the first and second regions substantially devoid of conductive material. The launcher element has a substantially rectangular shape with a width greater than a width of the signal line at the first end.
    Type: Grant
    Filed: March 18, 2014
    Date of Patent: December 6, 2016
    Assignee: PERASO TECHNOLOGIES INC.
    Inventors: Saman Jafarlou, Mohammad Fakharzadeh
  • Patent number: 9402301
    Abstract: A radio frequency (RF) module having a plurality of channels includes a heat sink having at least one tapered edge; a substrate disposed over a surface of the heat sink such that the tapered edge of the heat sink extends past a boundary of the substrate. RF, logic and power circuitry is disposed on the substrate and one or more RF signal ports are formed on an edge of the substrate to allow the RF module to be used in an array antenna having a brick architecture. The tapered edge heat sink provides both a ground plane for RF signal components and a thermal path for heat generating circuits disposed in the substrate.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: July 26, 2016
    Assignee: Raytheon Company
    Inventors: Waid Paine, James S. Wilson, Cary C. Kyhl, Robert S. Isom
  • Patent number: 9343794
    Abstract: A millimeter wave bands semiconductor package includes a metal base body, a circuit board, and a metal cover body. The base body has a first non-penetration hole and a second non-penetration hole. The circuit board is disposed on the base body and has an input signal line and an output signal line on a front side surface thereof. The cover body is disposed on the circuit board and has a first penetration hole and a second penetration hole. The cover body is disposed such that the first penetration hole is disposed directly above the first non-penetration hole of the base body and the second penetration hole is disposed directly above the second non-penetration hole of the base body. Further, the first penetration hole and the first non-penetration hole constitute a first waveguide, and the second penetration hole and the second non-penetration hole constitute a second waveguide.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: May 17, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Kazutaka Takagi
  • Patent number: 9287224
    Abstract: A high-frequency module includes a lower base member having a recess part formed in an upper face thereof, and having a base metal part formed on a lower face thereof that is to be grounded, an upper substrate disposed inside the recess part of the lower base member, a semiconductor device mounted on an upper face of the upper substrate, a first ground line connected to the semiconductor device and formed on the upper substrate, and a ground metal part connected to the base metal part and disposed in the lower base member, wherein the ground metal part is connected to the first ground line on the upper substrate.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: March 15, 2016
    Assignee: FUJITSU LIMITED
    Inventor: Satoshi Masuda
  • Patent number: 9240624
    Abstract: An integrated circuit includes a silicon-on-insulator wafer and interconnect layer providing a support for a coplanar waveguide formed above a top side of the support. A through-silicon via is formed from a back side of the support and passing through the silicon-on-insulator wafer to reach the interconnect layer. A trench is formed from the back side of the support underneath the coplanar waveguide. The trench extends over at least an entire length of the coplanar waveguide. The trench passes through the silicon-on-insulator wafer to reach the interconnect layer and may have a substantially same depth as the through-silicon via.
    Type: Grant
    Filed: May 30, 2012
    Date of Patent: January 19, 2016
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Pierre Bar
  • Patent number: 9082833
    Abstract: A stacked assembly includes a stacked structure stacked on a through via recessed reveal structure. The through via recessed reveal structure includes recesses within a backside surface of an electronic component that expose backsides of through vias. Pillars of the stacked structure are attached to the exposed backsides of the through vias through the recesses. The recesses in combination with the pillars work as a lock and key arrangement to insure self-alignment of the pillars with the backsides of the through vias allowing fine pitch interconnections to be realized. Further, by forming the interconnections to the backsides of the through vias within the recesses, the overall thickness of the stacked assembly is minimized. Further still, by forming the interconnections to the backsides of the through vias within the recesses, shorting between adjacent through vias is minimized or eliminated.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: July 14, 2015
    Inventors: David Jon Hiner, Ronald Patrick Huemoeller, Michael G. Kelly
  • Patent number: 9076790
    Abstract: An aluminum (Al) layer is formed over a semiconductor substrate. A selective portion of the Al layer is removed to form openings. The Al layer is anodized to obtain an alumina dielectric layer with a plurality of pores substantially perpendicular to a surface of the semiconductor substrate. The openings are filled with a conductive interconnect material. The pores are widened to form air gaps and a top etch stop layer is formed over the alumina dielectric layer.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Tien Wu, Tien-Lu Lin
  • Patent number: 9059516
    Abstract: A 3D package device of a photonic integrated chip matching circuit, comprising: a first carrier substrate; a first microwave transmission line array formed by evaporation on the top surface of the first carrier substrate to provide bias voltages and high-frequency modulation signals to the photonic integrated chip; a second carrier substrate formed perpendicularly to the first carrier substrate or to have a certain angle with respect to the first carrier substrate, so as to constitute a 3D structure; a second microwave transmission line array formed by evaporation on the bottom surface of the second carrier substrate to match electrodes of the first microwave transmission line array, the second microwave transmission line array being soldered or sintered with the electrodes of the first microwave transmission line array; an electrode array formed by evaporation on a side surface or two opposite side surfaces of the second carrier substrate; and a microwave circuit.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 16, 2015
    Assignee: Institute of Semiconductors, Chinese Academy of Sciences
    Inventors: Ninghua Zhu, Jiasheng Wang, Jianguo Liu, Yu Liu
  • Patent number: 9054078
    Abstract: A signal processing device includes: signal processing circuits. The signal processing circuit includes an input/output circuit configured by an input circuit serving as an input interface of a signal of a predetermined frequency band and/or an output circuit serving as an output interface of a signal of the frequency band and performs transmission of a signal of the frequency band between the signal processing circuit and another signal processing circuit. The output circuits of one and another signal processing circuits include circuits having the same configuration. The input circuits of the one and another signal processing circuits include other circuits having the same configurations. The input/output circuits of the one and another signal processing circuits can perform transmission of a signal of the predetermined frequency band even when any one of transmission media having mutually different characteristics is mediated.
    Type: Grant
    Filed: February 8, 2012
    Date of Patent: June 9, 2015
    Assignee: SONY CORPORATION
    Inventors: Kenichi Kawasaki, Yusuke Tanaka, Hiroyuki Yamagishi, Ali Hajimiri