Plural Balanced Circuits Patents (Class 333/5)
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Patent number: 12048093Abstract: A flexible wiring board includes a signal line and a conductive portion that overlaps the signal line in plan view. The conductive portion includes a first line portion extending in a first direction and having a first part and a second part, a second line portion extending in a second direction and having a third part and a fourth part, and a third line portion. The third line portion has a line width smaller than a line width of the first part and a line width of the second part, is connected to the first and second parts, and is provided between the first part and the second part. The conductive portion includes a fourth line portion that is connected to the third part and the fourth part and that is provided between the third part and the fourth part. The third line portion and the fourth line portion intersect.Type: GrantFiled: July 29, 2022Date of Patent: July 23, 2024Assignee: Canon Kabushiki KaishaInventors: Toshiyuki Yoshida, Yu Ogawa
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Patent number: 11658080Abstract: Systems and assemblies are provided for transposition channel routing where the characteristics of an escape route can be modified on a printed circuit board (PCB) in a manner that reduces crosstalk and realizes significant signal quality improvement. The techniques involve “transposition” of a signal line pair on the PCB, reduces effect coupling coefficients for individual aggressor signals, thereby reducing the crosstalk. Transposition channel routing techniques can also be applied to other areas on a PCB (e.g., other than escape routes) where space is constrained and other mitigation techniques are not possible. The PCB can include an array of contact pads, a plurality of signal line pairs that include an escape route. One or more transposition junctions disposed within the escape route can route a signal line pair from a first routing channel in the escape route into a second routing channel in the escape route.Type: GrantFiled: October 29, 2020Date of Patent: May 23, 2023Assignee: Hewlett Packard Enterprise Development LPInventors: Melvin K. Benedict, Karl J. Bois
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Patent number: 11640933Abstract: Embodiments are disclosed for providing a ball grid array pattern for an integrated circuit. An example integrated circuit apparatus includes an integrated circuit and a ball grid array. The integrated circuit includes at least a package substrate and a silicon chip. The ball grid array is disposed on the package substrate of the integrated circuit. The ball grid array includes a first set of solder balls that is configured to provide electrical connections for communication channels and a second set of the solder balls associated with an electrical ground. The first set of solder balls includes a first subset of solder balls configured in a first orientation and a second subset of solder balls configured in a second orientation. Furthermore, at least one solder ball from the second set of the solder balls is disposed between the first subset of solder balls and the second subset of solder balls.Type: GrantFiled: March 11, 2021Date of Patent: May 2, 2023Assignee: Mellanox Technologies, Ltd.Inventors: Pavel Vilner, Dmitry Fliter, Jacov Brener
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Patent number: 11533078Abstract: A method and circuit for providing adaptive suppression of signal crosstalk appearing on a common return wire in a signal cable connected to a device. The method steps comprise connecting an adjustable negative resistance circuit between the common wire terminal and a common point at the device; determining an auxiliary current (Iaux) such that is flowing through at least one of the cable wires and returns through the common wire; sensing the voltage between selected at least one of the cable wire terminals at the device port and the common point, while ensuring that this level is substantially affected by Iaux; measuring a level of the sensed voltage according to a predefined level measurement procedure; and adjusting the negative resistance so as to nullify said voltage level, thereby effectively cancelling the common wire ohmic resistance.Type: GrantFiled: May 3, 2022Date of Patent: December 20, 2022Assignee: ELBIT SYSTEMS LAND AND C4I LTD.Inventors: Yeheskel Chechik, Jacob Vintor
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Patent number: 11423825Abstract: A functional panel, a method of manufacturing the same, and a terminal are disclosed. The functional panel includes a base substrate, at least one differential signal line group on the base substrate, where each differential signal line group of the at least one differential signal line group includes two signal lines and at least one ground line group on the base substrate and on the same side of the base substrate as the at least one differential signal line group. Each ground line group of the at least one ground line group includes two ground lines. Each ground line group corresponds to each differential signal line group one-to-one, and orthographic projections of the two ground lines in each ground line group on the base substrate are on both sides of an orthographic projection of a corresponding differential signal line group on the base substrate, and two ground lines in the ground line group are connected to a same reference ground.Type: GrantFiled: July 26, 2019Date of Patent: August 23, 2022Assignees: CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Ying Zhang, Xianyong Gao, Sijun Lei, Yunsong Li, Shanbin Chen, Bo Ran
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Patent number: 10499492Abstract: A stubbed differential trace pair system includes a circuit board having a first differential trace pair with a first trace and a second trace, and a second differential trace pair with a third trace and a fourth trace, where the first trace located opposite the second trace and the third trace from the fourth trace. Second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite the second trace from the first trace. Third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite the third trace from the fourth trace. The second trace stubs and the third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.Type: GrantFiled: January 31, 2018Date of Patent: December 3, 2019Assignee: Dell Products L.P.Inventors: Umesh Chandra, Bhyrav M. Mutnury, Mallikarjun Vasa
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Patent number: 10396419Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.Type: GrantFiled: January 7, 2019Date of Patent: August 27, 2019Assignee: National Taiwan UniversityInventors: Tzong-Lin Wu, Po-Jui Li, Ying-Cheng Tseng, Chi-Hsuan Cheng
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Patent number: 10325053Abstract: A method and apparatus for matching the lengths of traces of differential signal pairs. The method includes determining that a first trace is longer than a second trace and modifying the second trace so that the length is substantially equal to the length of the first trace. In some implementations, the second trace can be modified by replacing one or more sections of the trace with two line segments that are substantially equal in length and meet at a vertex that is less than 180 degrees.Type: GrantFiled: June 9, 2017Date of Patent: June 18, 2019Assignee: CISCO TECHNOLOGY, INC.Inventors: Lin Shen, Yongming Xiong, Stephen Ong, Shahbaz Mahmood
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Patent number: 10305193Abstract: A high speed radio frequency signal interconnect device provides for signal communication within a system at cryogenic temperatures. The device includes a plurality of conductive traces provided on a first dielectric substrate where the ends of the traces have a predetermined shape. A second dielectric substrate covers the first dielectric substrate leaving the ends of the traces exposed. A connector is coupled to each respective end and includes pins coupled to a respective trace. Each connector is configured to define a respective isolating chamber about each of the first ends of the conductive traces where the pins are attached.Type: GrantFiled: February 22, 2018Date of Patent: May 28, 2019Assignee: Raytheon CompanyInventors: Amedeo Larussi, David A. Buell, Craig R. Adams, Christopher Moshenrose
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Patent number: 10158339Abstract: Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.Type: GrantFiled: December 11, 2015Date of Patent: December 18, 2018Assignee: Intel CorporationInventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Howard L. Heck, Wil Choon Song
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Patent number: 10141698Abstract: A circuit board for a high speed communication jack including a rigid circuit board in the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a middle layer in the substrate, with each trace extending from a corresponding one of the plurality of vias, a first shielding layer on a first side of the middle layer in the substrate, a second shielding layer on a second side of the middle layer in the substrate, and a third shielding layer adjacent to the second shielding layer.Type: GrantFiled: May 4, 2016Date of Patent: November 27, 2018Assignee: Sentinel Connector Systems, Inc.Inventor: Brett D. Robinson
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Patent number: 9596749Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.Type: GrantFiled: December 11, 2014Date of Patent: March 14, 2017Assignee: Intel CorporationInventors: Kuan-Yu Chen, Yun Ling, Mohd Muhaiyiddin Bin Abdullah, Jackson Chung Peng Kong, Chung-Hao Chen, Hao-Han Hsu, Xiang Li
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Patent number: 9548278Abstract: A passive equalization structure is provided. The passive equalization structure includes a semiconductor substrate having first and a differential pair having first and second signal conductors. The first signal conductor is formed in a first layer of the semiconductor substrate. The second signal conductor is formed in a second layer in the semiconductor substrate that is different than the first layer. The passive equalization structure further includes first and second reference planes, whereby the first and second signal conductors are formed between the first and second reference planes. The first reference plane has a first thickness, and the first signal conductor has a second thickness that is different than the first thickness. A conductive via may short the first and second reference to minimize uncertainty and variations in capacitance from the first and second signal conductors and unwanted stray capacitance effects.Type: GrantFiled: December 28, 2015Date of Patent: January 17, 2017Assignee: Altera CorporationInventors: Jian Liu, Hui Liu
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Patent number: 9369231Abstract: A method, system and computer program product to adjust transfer rates on conductors in a multi-conductor cable comprising monitoring signals received on each conductor, determining a Signal to Noise Ratio (SNR) for each conductor and adjusting a transfer rate on one or more conductors based on the corresponding SNR. In an embodiment the multi-conductor cable is a twisted pair Ethernet cable. The method further comprises determining whether a conductor is transmitting at an optimal transfer rate as a function of its SNR, calculating an optimal transfer rate for each conductor as a function of its SNR and periodically measuring a change in SNR on each conductor. If the change in SNR is greater than a predetermined threshold, then the transfer rate is re-calculated for the conductors requiring transfer rate adjustment as a function of SNR.Type: GrantFiled: January 12, 2006Date of Patent: June 14, 2016Assignee: Broadcom CorporationInventors: Kevin Brown, Scott R. Powell, Gottfried Ungerboeck
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Patent number: 9173283Abstract: A printed circuit board (PCB) includes a ground layer, a first layer, a second layer, a connector footprint, and a pair of differential signal lines. The connector footprint comprises first and second bonding pads. The PCB defines a first signal via in a central portion of a space bounded by the first bonding pad, and a second signal via in a central portion of a space bounded by the second bonding pad. A number of first ground vias on the first bonding pad and a number of second ground vias on the second bonding pad are electrically connected to the ground layer. First annular slots surrounding corresponding first ground via are defined in the ground layer. Second annular slots surrounding corresponding second ground vias are defined in the ground layer. Connection slots are defined in the ground layer and communicate between the first annular slots and the second annular slots.Type: GrantFiled: December 18, 2013Date of Patent: October 27, 2015Assignee: ShenZhen Goldsun Network Intelligence Technology Co., Ltd.Inventors: Shao-You Tang, Po-Chuan Hsieh
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Patent number: 9088116Abstract: In one embodiment, the present invention is a communication connector, comprising a compensation circuit for providing a compensating signal to approximately cancel an offending signal over a range of frequency, the compensation circuit including a capacitive coupling with a first magnitude growing at a first rate over the range of frequency and a mutual inductive coupling with a second magnitude growing at a second rate over the range of frequency, the second rate being greater than the first rate (e.g., the second rate approximately double the first rate).Type: GrantFiled: November 20, 2012Date of Patent: July 21, 2015Assignee: Panduit Corp.Inventors: Masud Bolouri-Saransar, Ronald A. Nordin
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Patent number: 9087840Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.Type: GrantFiled: November 1, 2010Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chin-Wei Kuo, Chewn-Pu Jou
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Publication number: 20150145745Abstract: According to the invention there is provided a balun including: a slotline which is coupled to an input line and an output line, in which at least a portion of the slotline is sandwiched between a first and a second layer of dielectric material.Type: ApplicationFiled: June 17, 2013Publication date: May 28, 2015Applicant: BAE SYSTEMS plcInventors: Mark Christopher Nguyen, Gareth Michael Lewis, Richard John Harper
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Publication number: 20150130551Abstract: A balanced-unbalanced conversion-type elastic wave device includes an unbalanced signal terminal, first and second balanced signal terminals, and first to fifth interdigital transducers disposed along an elastic wave propagation direction. One end of each of the first, third, and fifth interdigital transducers is connected in common to the unbalanced signal terminal, one end of each of the second interdigital transducer and the fourth interdigital transducer is connected to the first and second balanced signal terminals respectively, a first inductance is connected between the first interdigital transducer and a ground potential, and a second inductance is connected between the fifth interdigital transducer and the ground potential. First and second inductance values of the first and second inductances, respectively, are different.Type: ApplicationFiled: January 20, 2015Publication date: May 14, 2015Inventor: Minefumi OUCHI
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Publication number: 20150084712Abstract: A first filter channel with superior attenuation characteristics for transmission signals and is less susceptible to influence of transmission signals inputted to a transmission SAW filter device, is disposed closer to a transmission terminal, whereas a second filter channel with poor attenuation characteristics in a transmission band and is more susceptible to the influence of transmission signals inputted to the transmission SAW filter device, is disposed farther from a transmission terminal to improve isolation characteristics in a differential mode of a duplexer.Type: ApplicationFiled: December 4, 2014Publication date: March 26, 2015Inventor: Syuji YAMATO
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Patent number: 8981865Abstract: An exemplary transmission line system is provided. The system includes a first transmission line partially arranged on a first layer of a PCB including first structure units and partially arranged on a third layer of the PCB including second structure units, and a second transmission line arranged on a second layer of the PCB. Each first structure unit and each second structure respectively include a first connection line, a second connection line, and a first bent line; and a third connection line, a fourth connection line, and a second bent line. A second end of the first connection line and the second connection line of each of the first structure units are respectively connected to a second end of the third connection line and the fourth connection line of the adjacent second structure unit through respective vias.Type: GrantFiled: November 29, 2012Date of Patent: March 17, 2015Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Shao-Wei Wang
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Patent number: 8917148Abstract: A transmission unit with reduced crosstalk signal includes a first conductor group having at least one first conductor surrounded by a first sheath and at least one second conductor surrounded by a second sheath. The first and the second conductor are axially arranged corresponding to one another. The first sheath has a dielectric coefficient higher than that of the second sheath, so that a difference in dielectric property exists between the first and the second conductor to enable reduction of crosstalk occurred during high-speed signal transmission over the transmission unit.Type: GrantFiled: July 14, 2011Date of Patent: December 23, 2014Assignee: Yes Way Enterprise CorporationInventors: Da-Yu Liu, Da-Yung Liu, Teng-Lan Liu, Ben-Hwa Jang
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Patent number: 8907739Abstract: A differential signal line structure is disposed on a substrate including a signal layer, a filter layer and a grounding layer. The signal layer, the filter layer and the grounding layer are arranged from up to down and in parallel manner. The differential signal line structure accordingly includes a differential signal line group, a first wire and a first grounding circuit; the differential signal line group is disposed in the signal layer; and the first wire is disposed in the filter layer and is arranged in a corresponding position right underneath the differential signal line group. The first grounding circuit is disposed in the grounding layer and is electrically connected to an end point of the first wire through a first via.Type: GrantFiled: July 13, 2011Date of Patent: December 9, 2014Assignee: Chung Yuan Christian UniversityInventors: Guang-Hwa Shiue, Che-Ming Hsu, Cheng-Fu Hsu
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Patent number: 8890559Abstract: [Problems] In a connector to which unbalanced-type lines are connected, providing a connector which prevents crosstalk in the connector and an interface apparatus including the connector. [Solutions] Comprising terminals to be connected with connectors, a plurality of boards having a plurality of transmission lines, one ends of the transmission lines being connected with the terminals, a housing for fixing the plurality of boards, and common mode choke coils provided on the boards and connected with balanced-type lines.Type: GrantFiled: October 13, 2011Date of Patent: November 18, 2014Assignee: Advantest CorporationInventors: Yuichiro Iwamoto, Takayuki Nakamura
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Patent number: 8847696Abstract: A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The cable can be coupled to electronic components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.Type: GrantFiled: November 30, 2010Date of Patent: September 30, 2014Assignee: QUALCOMM IncorporatedInventors: James Leroy Blair, Jeffrey Thomas Smith
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Publication number: 20140285280Abstract: Disclosed is a grounding pattern structure for high-frequency connection pads of a circuit board. A substrate of the circuit board includes a component surface on which at least a pair of high-frequency connection pads. At least a pair of differential mode signal lines are formed on the substrate and connected to the high-frequency connection pads. The grounding surface of the substrate includes a grounding layer formed at a location corresponding to the differential mode signal lines. The grounding surface of the substrate includes a grounding pattern structure formed thereon to correspond to a location adjacent to the high-frequency connection pads. The grounding pattern structure is electrically connected to the grounding layer. The component surface of the substrate can be provided with a connector mounted thereto with signal terminals of the connector soldered to the high-frequency connection pads.Type: ApplicationFiled: May 16, 2013Publication date: September 25, 2014Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.Inventors: CHIH-HENG CHUO, GWUN-JIN LIN, KUO-FU SU
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Publication number: 20140266490Abstract: A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Kai Xiao, Jimmy Hsu, Yuan-Liang Li, Richard K. Kunze
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Publication number: 20140197899Abstract: A printed circuit board includes a plurality of wiring layers and a plurality of differential signal vias to establish connections between the plurality of wiring layers through via pairs and to be disposed so that paired-vias possessed by a specified differential signal via for transmitting a differential signal different from a signal of another differential signal via adjacent thereto are arranged on a locus of a point distanced equally from each of the paired-vias possessed by another differential signal via.Type: ApplicationFiled: November 18, 2013Publication date: July 17, 2014Applicant: FUJITSU LIMITEDInventor: Kenichi KAWAI
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Publication number: 20140184350Abstract: A device is provided for use with a signal, wherein the device includes a substrate, a first signal trace and a second signal trace. The first signal trace is disposed within the substrate at a first plane from the top surface by a distance d1. The second signal trace is disposed within the substrate at a second plane from the top surface by a distance d2, wherein d2<d1<t. The first signal trace includes a first portion, whereas the second signal trace includes a second portion. The first portion is parallel to the second portion. The first signal trace and the second signal trace form a differential pair. The first signal trace is operable to conduct a positive portion of the signal, whereas the second signal trace is operable to conduct a negative portion of the signal.Type: ApplicationFiled: December 27, 2012Publication date: July 3, 2014Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Gregory Eric Howard
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Patent number: 8742868Abstract: The invention is related to a microstrip line structure, which comprises: a first microstrip line and a second microstrip line, paralleled with the first mircostrip line for transferring a transmission signal, and a plurality of grooves periodically arranged on both sides of the second microstrip line by using subwavelength, and each period length in the plurality of grooves is smaller than the wavelength of the transmission signal.Type: GrantFiled: April 29, 2011Date of Patent: June 3, 2014Assignee: Chung Hua UniversityInventors: Chia-Ho Wu, Tzong-Jer Yang
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Publication number: 20140091873Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.Type: ApplicationFiled: December 5, 2013Publication date: April 3, 2014Inventor: Xiaoning Ye
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Patent number: 8674781Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.Type: GrantFiled: September 15, 2012Date of Patent: March 18, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Heung-Kyu Kim
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Publication number: 20140035701Abstract: A differential terminal 21a is connected to a branch line 33a which is provided in the main line close to the differential terminal 21a in the range from the intersection portion 39a to a start terminal on the line. A differential terminal 21b is connected to a branch line 37a which is provided in the main line close to the differential terminal 21b in the range from the intersection portion 39a to an end terminal on the line. A differential terminal 22a is connected to a branch line 33b which is provided in the main line close to the differential terminal 22a in the range from the intersection portion 39b to the start terminal. A differential terminal 22b is connected to a branch line 37b which is provided in the main line close to the differential terminal 22b in the range from the intersection portion 39b to the end terminal.Type: ApplicationFiled: July 31, 2013Publication date: February 6, 2014Applicant: ANRITSU CORPORATIONInventor: Fumihito Hirabayashi
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Publication number: 20140009240Abstract: A high-frequency module includes a mount board, a wave splitter chip mounted on one principal surface of the mount board and including a transmission filter and a reception filter, a first inductor chip mounted on one principal surface of the mount board and including an inductor, and a second inductor chip mounted on one principal surface of the mount board and including an inductor. The first and second inductor chips are disposed adjacent to each other and each has a polarity. The first and second inductor chips are disposed such that the polarities thereof are opposite to each other, as viewed from the reception filter.Type: ApplicationFiled: August 8, 2013Publication date: January 9, 2014Applicant: Murata Manufacturing Co., Ltd.Inventors: Tatsuro NAGAI, Masanori KATO, Takashi KIHARA
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Publication number: 20140011393Abstract: A communication connector comprising plug interface contacts having a plurality of conductor pairs, and corresponding cable connector contacts. A printed circuit board connects the plug interface contacts to respective cable connector contacts. The printed circuit board includes circuitry between a first conductor pair and a second conductor pair. The circuitry has a first mutually inductive coupling between a first conductor of the first conductor pair and a first conductor of the second conductor pair, a first capacitive coupling between the first conductor of the first conductor pair and the first conductor of the second conductor pair. The first capacitive coupling is approximately concurrent with the first mutually inductive coupling. A shunt capacitive coupling connects the first conductor of the second conductor pair to a second conductor of the second conductor pair.Type: ApplicationFiled: May 30, 2013Publication date: January 9, 2014Inventors: Frank M. Straka, Melanie M. Hagar, Masud Bolouri-Saransar, Ronald A. Nordin
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Publication number: 20140009239Abstract: A network signal processing circuit assembly includes a network-on-chip, a network connector, and a processing circuit including a plurality of channels respectively and electrically connected between the network-on-chip and the network connector, a plurality of signal coupling capacitors respectively electrically coupled to the channels, and a plurality of inductor sets electrically connected in parallel between the signal coupling capacitors and the network connector for causing a back-EMF (back-electro motive force) when receiving power supply from the signal coupling capacitors.Type: ApplicationFiled: November 21, 2012Publication date: January 9, 2014Applicant: AJOHO ENTERPRISE CO., LTD.Inventors: Chia-Ping MO, You-Chi LIU
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Patent number: 8624687Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.Type: GrantFiled: December 22, 2010Date of Patent: January 7, 2014Assignee: Intel CorporationInventor: Xiaoning Ye
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Patent number: 8587385Abstract: A printed wiring board includes a first terminal array and a second terminal array comprising a plurality of terminals, a first differential signal line connecting a first terminal of the first terminal array to a predetermined number of terminals including a second terminal of the second terminal array, a second differential signal line connecting a third terminal of the first terminal array to a number of terminals including a fourth terminal of the second terminal array, which is bigger than the predetermined number of terminals wherein at least one of a line width and a line interval of one pair signal lines configuring the first differential signal line and the second differential signal line is determined so that differential impedance of the second differential signal line becomes higher compared with differential impedance of the first differential signal line.Type: GrantFiled: December 10, 2010Date of Patent: November 19, 2013Assignee: Canon Kabushiki KaishaInventor: Kengo Umeda
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Publication number: 20130278348Abstract: Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout (for example, a section of a pinout, a socket, a connector, etc.) into at least one of the first differential signal pair and the second differential signal pair. Other embodiments are described and claimed.Type: ApplicationFiled: December 19, 2011Publication date: October 24, 2013Inventor: Xiaoning Ye
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Publication number: 20130200958Abstract: An electronic device comprising a laminate constituted by pluralities of insulation layers on which conductor patterns are formed; ground electrodes being formed on an upper-surface-side insulation layer and a bottom-surface-side insulation layer in the laminate; the laminate being partitioned to first and second regions by a first shield constituted by a line of via-holes electrically connecting the upper-surface-side ground electrode to the bottom-surface-side ground electrode; conductor patterns constituting a first filter for a first frequency band and conductor patterns constituting a first balun for the first frequency band being arranged in the first and second regions, respectively; pluralities of terminal electrodes being formed on bottom or side surfaces of the laminate; one of terminal electrodes of the first filter, which acts as an unbalanced port, being adjacent to a terminal electrode of the first balun, which acts as an unbalanced port, with no other terminal electrode than a ground electrodeType: ApplicationFiled: September 12, 2011Publication date: August 8, 2013Applicant: HITACHI METALS LTD.Inventor: Hirotaka Satake
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Patent number: 8502617Abstract: A printed circuit board includes a base, a signal layer lying on the base, and a number of pairs of differential signal traces positioned on the signal layer. The base is made of a grid of glass fiber bundles filled with epoxy resin. Each pair of differential signal traces includes a first signal trace and a second signal trace. Each of the first and second signal traces extends in a zigzag pattern. The first signal trace includes a number of wave crests and wave troughs. The wave crests define a reference straight line that connects all the wave crest of the first signal trace. The ratio of the distance from each wave crest to the reference straight line to the orthogonal distance between each wave crest and an adjacent wave trough along the reference straight line is 1:5.Type: GrantFiled: January 28, 2011Date of Patent: August 6, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventors: Ying-Tso Lai, Yung-Chieh Chen
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Publication number: 20130187725Abstract: An acoustic wave device is provided with a low-frequency side filter having a low-frequency side passband, a high-frequency side filter having a high-frequency side passband, and first and second balanced terminals. The low-frequency side filter is connected to a first unbalanced terminal. The low-frequency side passband is a frequency band from a first minimum frequency to a first maximum frequency. The high-frequency side filter is connected to a second unbalanced terminal. The high-frequency side passband is a frequency band from a second minimum frequency to a second maximum frequency. The low-frequency side filter includes a first longitudinally-coupled acoustic wave resonator and a first one-terminal pair acoustic wave resonator connected in series to the first longitudinally-coupled acoustic wave resonator. An antiresonant frequency of the first one-terminal pair acoustic wave resonator is set to be higher than the first maximum frequency and lower than the second minimum frequency.Type: ApplicationFiled: November 7, 2011Publication date: July 25, 2013Applicant: PANASONIC CORPORATIONInventor: Satoru Ikeuchi
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Publication number: 20130162364Abstract: A printed circuit board includes an outer signal layer, a first ground layer, a first ground layer located below the outer signal layer, an inner signal layer located below the first ground layer, an second ground layer located below the inner signal layer, and a first differential signal transmission pair and a second differential signal transmission pair laid on the outer signal layer and the inner signal layer. A value h is equal to a distance between the inner signal layer and its closest ground layer. A distance between the first pair and the second pair is not more than h×3.Type: ApplicationFiled: December 25, 2012Publication date: June 27, 2013Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: HON HAI PRECISION INDUSTRY CO., LTD.
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Publication number: 20130082796Abstract: The present invention relates to a component (BE) which has a first duplexer operating with acoustic waves and a second duplexer operating with acoustic waves, wherein the first and second duplexers are arranged in a single SMD housing. In addition, the invention relates to a module (MO), which interconnects such a component (BE) and at least three 90° hybrids (HYB1-HYB3) to form an enhanced duplexer. A further aspect of the invention relates to a 2in1 hybrid, in which two 90° hybrids (HYB3, HYB4) or one 90° hybrid (HYB3) and one 180° hybrid (BAL) are arranged on a single chip.Type: ApplicationFiled: September 28, 2012Publication date: April 4, 2013Applicant: EPCOS AGInventor: EPCOS AG
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Patent number: 8350637Abstract: A circuit substrate includes a first pair of ground lines, a second pair of ground lines, a plurality of first connection lines, a plurality of second connection lines and a plurality of conductive pillars. The first and second pairs of ground lines are located on first and second surfaces of the substrate, respectively. The pillars are located in the substrate and vertically conducted between the first pair of ground lines and the second connection lines and between the second pair of ground lines and the first connection lines, and the first and second pairs of ground lines are conducted, so that a 3-D grounding circuit loop is formed. Moreover, a first pair of signal lines is disposed between the first connection lines for grounding and a second pair of signal lines is disposed between the second connection lines for grounding to get a better signal integrity.Type: GrantFiled: April 15, 2010Date of Patent: January 8, 2013Assignee: Sunplus Technology Co., Ltd.Inventor: Ting-Hao Yeh
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Patent number: 8344821Abstract: A printed circuit board layout method includes the following steps. A printed circuit board with a signal layer and a pair of differential transmission lines positioned on the signal layer is provided. A first distance is determined; when the distance between the pair of differential transmission lines is greater than the first distance, an eye width and an eye height of an eye diagram nearly remains the same. When a distance between the pair of differential transmission lines is less than the first distance, an eye width and an eye height of an eye diagram decreases. A second distance that is less than the first distance is set between the pair of differential transmission lines which makes the eye width and the eye height greater than a predetermined value, and which is determined by a Far End Crosstalk (FEXT) on the eye diagram when the pair differential transmission lines transmit signals.Type: GrantFiled: August 13, 2010Date of Patent: January 1, 2013Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Yu-Hsu Lin
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Patent number: 8324979Abstract: A coupled microstrip line structure having tunable characteristic impedance and wavelength are provided. In accordance with one aspect of the invention, a coupled microstrip line structure comprises a first ground plane having a plurality of first conductive strips separated by a dielectric material, and a first dielectric layer over the first ground plane. The coupled microstrip line further comprises a first signal line over the first dielectric layer, wherein the first signal line is directly above the plurality of first conductive strips, and wherein the first signal line and the plurality of first conductive strips are non-parallel, and a second signal line over the first dielectric layer, wherein the second signal line is directly above the plurality of first conductive strips, and wherein the second signal line and the plurality of first conductive strips are non-parallel, and wherein the second signal line is substantially parallel to the first signal line.Type: GrantFiled: November 12, 2009Date of Patent: December 4, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Shu-Ying Cho
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Patent number: 8294529Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.Type: GrantFiled: January 29, 2009Date of Patent: October 23, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Heung-Kyu Kim
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Publication number: 20120262246Abstract: An elastic wave filter includes at least a piezoelectric substrate and a longitudinally coupled resonator-type elastic wave filter unit provided on the piezoelectric substrate. The longitudinally coupled resonator-type elastic wave filter unit includes first to fifth IDTs and first and second reflectors arranged on either side of the first to fifth IDTs. The third IDT includes first and second divided comb-shaped electrodes. The second and fourth IDTs are connected to an unbalanced signal terminal, the first IDT and the first divided comb-shaped electrode of the third IDT are connected to a first balanced signal terminal, and the fifth IDT and the second divided comb-shaped electrode of the third IDT are connected to a second balanced signal terminal. The first and fifth IDTs each have a constant electrode finger pitch, and the electrode finger pitch of the first IDT is less than that of the fifth IDT.Type: ApplicationFiled: October 11, 2011Publication date: October 18, 2012Applicant: MURATA MANUFACTURING CO., LTD.Inventor: Junpei YASUDA
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Patent number: RE43957Abstract: In a high-frequency module, mounting lands arranged to mount at least one filter device having at least one set of an unbalanced terminal and two balanced terminals are provided at one side of a substrate top surface, and mounting lands arranged to mount at least one element electrically connected to the filter device are arranged at the opposite side. At least two of a plurality of connection terminals provided on a substrate bottom surface are respectively connected to conductor patterns connected to via-hole conductors penetrating the substrate within a mounting area for mounting the filter device via connection lines and are arranged at a pitch which is less than the pitch of the via-hole conductors.Type: GrantFiled: June 10, 2011Date of Patent: February 5, 2013Assignee: Murata Manufacturing Co., Ltd.Inventor: Taturo Nagai