Plural Balanced Circuits Patents (Class 333/5)
  • Patent number: 10499492
    Abstract: A stubbed differential trace pair system includes a circuit board having a first differential trace pair with a first trace and a second trace, and a second differential trace pair with a third trace and a fourth trace, where the first trace located opposite the second trace and the third trace from the fourth trace. Second trace stubs extend in a spaced apart orientation relative to each other and from a side of the second trace that is opposite the second trace from the first trace. Third trace stubs extend in a spaced apart orientation relative to each other and from a side of the third trace that is opposite the third trace from the fourth trace. The second trace stubs and the third trace stubs are configured to reduce crosstalk generated by the transmission of signals through the first differential trace pair and the second differential trace pair.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: December 3, 2019
    Assignee: Dell Products L.P.
    Inventors: Umesh Chandra, Bhyrav M. Mutnury, Mallikarjun Vasa
  • Patent number: 10396419
    Abstract: The present invention provides a common-mode signal absorber, which comprises an impedance-matching network and a common-mode signal reflection circuit. A differential-mode signal is inputted into input ends of the impedance-matching network, and outputted from output ends of the common-mode signal reflection circuit. When a common-mode signal is inputted into the common-mode signal absorber, the common-mode signal reflection circuit is for reflecting the common-mode signal within a specific frequency band. Afterward, the reflection of the common-mode signal within the specific frequency band will be absorbed by an impedance element of the impedance-matching network. Thus, the common-mode signal within the specific frequency band may be absorbed by the impedance-matching network so as to avoid to interfere signals transmitted on a communication system.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: August 27, 2019
    Assignee: National Taiwan University
    Inventors: Tzong-Lin Wu, Po-Jui Li, Ying-Cheng Tseng, Chi-Hsuan Cheng
  • Patent number: 10325053
    Abstract: A method and apparatus for matching the lengths of traces of differential signal pairs. The method includes determining that a first trace is longer than a second trace and modifying the second trace so that the length is substantially equal to the length of the first trace. In some implementations, the second trace can be modified by replacing one or more sections of the trace with two line segments that are substantially equal in length and meet at a vertex that is less than 180 degrees.
    Type: Grant
    Filed: June 9, 2017
    Date of Patent: June 18, 2019
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Lin Shen, Yongming Xiong, Stephen Ong, Shahbaz Mahmood
  • Patent number: 10305193
    Abstract: A high speed radio frequency signal interconnect device provides for signal communication within a system at cryogenic temperatures. The device includes a plurality of conductive traces provided on a first dielectric substrate where the ends of the traces have a predetermined shape. A second dielectric substrate covers the first dielectric substrate leaving the ends of the traces exposed. A connector is coupled to each respective end and includes pins coupled to a respective trace. Each connector is configured to define a respective isolating chamber about each of the first ends of the conductive traces where the pins are attached.
    Type: Grant
    Filed: February 22, 2018
    Date of Patent: May 28, 2019
    Assignee: Raytheon Company
    Inventors: Amedeo Larussi, David A. Buell, Craig R. Adams, Christopher Moshenrose
  • Patent number: 10158339
    Abstract: Techniques for reducing multi-reflection noise via compensation structures are described herein. An example system includes a capacitive component. The example system further includes a capacitive compensation structure coupled to two ends of the capacitive component. The example system includes a partially meshed ground plane coupled to one side of a dielectric substrate. The example system also includes one or more signal conductors coupled to another side of the dielectric substrate and electrically coupled to the capacitive component. The one or more signal conductors are located parallel to a meshed length of the partially meshed ground plane.
    Type: Grant
    Filed: December 11, 2015
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Jackson Chung Peng Kong, Bok Eng Cheah, Khang Choong Yong, Howard L. Heck, Wil Choon Song
  • Patent number: 10141698
    Abstract: A circuit board for a high speed communication jack including a rigid circuit board in the housing having a substrate, a plurality of vias extending through the substrate with each via being configured to accommodate a pin on the housing, a plurality of traces on a middle layer in the substrate, with each trace extending from a corresponding one of the plurality of vias, a first shielding layer on a first side of the middle layer in the substrate, a second shielding layer on a second side of the middle layer in the substrate, and a third shielding layer adjacent to the second shielding layer.
    Type: Grant
    Filed: May 4, 2016
    Date of Patent: November 27, 2018
    Assignee: Sentinel Connector Systems, Inc.
    Inventor: Brett D. Robinson
  • Patent number: 9596749
    Abstract: Techniques for routing signal traces in a circuit board are described. An example of an electronic device in accordance with the described techniques includes a circuit board comprising a plurality of conductive layers. The conductive layers include a signal layer and a reference plane. The signal layer includes signal traces and the reference plane includes an additional signal trace.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 14, 2017
    Assignee: Intel Corporation
    Inventors: Kuan-Yu Chen, Yun Ling, Mohd Muhaiyiddin Bin Abdullah, Jackson Chung Peng Kong, Chung-Hao Chen, Hao-Han Hsu, Xiang Li
  • Patent number: 9548278
    Abstract: A passive equalization structure is provided. The passive equalization structure includes a semiconductor substrate having first and a differential pair having first and second signal conductors. The first signal conductor is formed in a first layer of the semiconductor substrate. The second signal conductor is formed in a second layer in the semiconductor substrate that is different than the first layer. The passive equalization structure further includes first and second reference planes, whereby the first and second signal conductors are formed between the first and second reference planes. The first reference plane has a first thickness, and the first signal conductor has a second thickness that is different than the first thickness. A conductive via may short the first and second reference to minimize uncertainty and variations in capacitance from the first and second signal conductors and unwanted stray capacitance effects.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: January 17, 2017
    Assignee: Altera Corporation
    Inventors: Jian Liu, Hui Liu
  • Patent number: 9369231
    Abstract: A method, system and computer program product to adjust transfer rates on conductors in a multi-conductor cable comprising monitoring signals received on each conductor, determining a Signal to Noise Ratio (SNR) for each conductor and adjusting a transfer rate on one or more conductors based on the corresponding SNR. In an embodiment the multi-conductor cable is a twisted pair Ethernet cable. The method further comprises determining whether a conductor is transmitting at an optimal transfer rate as a function of its SNR, calculating an optimal transfer rate for each conductor as a function of its SNR and periodically measuring a change in SNR on each conductor. If the change in SNR is greater than a predetermined threshold, then the transfer rate is re-calculated for the conductors requiring transfer rate adjustment as a function of SNR.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: June 14, 2016
    Assignee: Broadcom Corporation
    Inventors: Kevin Brown, Scott R. Powell, Gottfried Ungerboeck
  • Patent number: 9173283
    Abstract: A printed circuit board (PCB) includes a ground layer, a first layer, a second layer, a connector footprint, and a pair of differential signal lines. The connector footprint comprises first and second bonding pads. The PCB defines a first signal via in a central portion of a space bounded by the first bonding pad, and a second signal via in a central portion of a space bounded by the second bonding pad. A number of first ground vias on the first bonding pad and a number of second ground vias on the second bonding pad are electrically connected to the ground layer. First annular slots surrounding corresponding first ground via are defined in the ground layer. Second annular slots surrounding corresponding second ground vias are defined in the ground layer. Connection slots are defined in the ground layer and communicate between the first annular slots and the second annular slots.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: October 27, 2015
    Assignee: ShenZhen Goldsun Network Intelligence Technology Co., Ltd.
    Inventors: Shao-You Tang, Po-Chuan Hsieh
  • Patent number: 9088116
    Abstract: In one embodiment, the present invention is a communication connector, comprising a compensation circuit for providing a compensating signal to approximately cancel an offending signal over a range of frequency, the compensation circuit including a capacitive coupling with a first magnitude growing at a first rate over the range of frequency and a mutual inductive coupling with a second magnitude growing at a second rate over the range of frequency, the second rate being greater than the first rate (e.g., the second rate approximately double the first rate).
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: July 21, 2015
    Assignee: Panduit Corp.
    Inventors: Masud Bolouri-Saransar, Ronald A. Nordin
  • Patent number: 9087840
    Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.
    Type: Grant
    Filed: November 1, 2010
    Date of Patent: July 21, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chin-Wei Kuo, Chewn-Pu Jou
  • Publication number: 20150145745
    Abstract: According to the invention there is provided a balun including: a slotline which is coupled to an input line and an output line, in which at least a portion of the slotline is sandwiched between a first and a second layer of dielectric material.
    Type: Application
    Filed: June 17, 2013
    Publication date: May 28, 2015
    Applicant: BAE SYSTEMS plc
    Inventors: Mark Christopher Nguyen, Gareth Michael Lewis, Richard John Harper
  • Publication number: 20150130551
    Abstract: A balanced-unbalanced conversion-type elastic wave device includes an unbalanced signal terminal, first and second balanced signal terminals, and first to fifth interdigital transducers disposed along an elastic wave propagation direction. One end of each of the first, third, and fifth interdigital transducers is connected in common to the unbalanced signal terminal, one end of each of the second interdigital transducer and the fourth interdigital transducer is connected to the first and second balanced signal terminals respectively, a first inductance is connected between the first interdigital transducer and a ground potential, and a second inductance is connected between the fifth interdigital transducer and the ground potential. First and second inductance values of the first and second inductances, respectively, are different.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventor: Minefumi OUCHI
  • Publication number: 20150084712
    Abstract: A first filter channel with superior attenuation characteristics for transmission signals and is less susceptible to influence of transmission signals inputted to a transmission SAW filter device, is disposed closer to a transmission terminal, whereas a second filter channel with poor attenuation characteristics in a transmission band and is more susceptible to the influence of transmission signals inputted to the transmission SAW filter device, is disposed farther from a transmission terminal to improve isolation characteristics in a differential mode of a duplexer.
    Type: Application
    Filed: December 4, 2014
    Publication date: March 26, 2015
    Inventor: Syuji YAMATO
  • Patent number: 8981865
    Abstract: An exemplary transmission line system is provided. The system includes a first transmission line partially arranged on a first layer of a PCB including first structure units and partially arranged on a third layer of the PCB including second structure units, and a second transmission line arranged on a second layer of the PCB. Each first structure unit and each second structure respectively include a first connection line, a second connection line, and a first bent line; and a third connection line, a fourth connection line, and a second bent line. A second end of the first connection line and the second connection line of each of the first structure units are respectively connected to a second end of the third connection line and the fourth connection line of the adjacent second structure unit through respective vias.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: March 17, 2015
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Shao-Wei Wang
  • Patent number: 8917148
    Abstract: A transmission unit with reduced crosstalk signal includes a first conductor group having at least one first conductor surrounded by a first sheath and at least one second conductor surrounded by a second sheath. The first and the second conductor are axially arranged corresponding to one another. The first sheath has a dielectric coefficient higher than that of the second sheath, so that a difference in dielectric property exists between the first and the second conductor to enable reduction of crosstalk occurred during high-speed signal transmission over the transmission unit.
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: December 23, 2014
    Assignee: Yes Way Enterprise Corporation
    Inventors: Da-Yu Liu, Da-Yung Liu, Teng-Lan Liu, Ben-Hwa Jang
  • Patent number: 8907739
    Abstract: A differential signal line structure is disposed on a substrate including a signal layer, a filter layer and a grounding layer. The signal layer, the filter layer and the grounding layer are arranged from up to down and in parallel manner. The differential signal line structure accordingly includes a differential signal line group, a first wire and a first grounding circuit; the differential signal line group is disposed in the signal layer; and the first wire is disposed in the filter layer and is arranged in a corresponding position right underneath the differential signal line group. The first grounding circuit is disposed in the grounding layer and is electrically connected to an end point of the first wire through a first via.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: December 9, 2014
    Assignee: Chung Yuan Christian University
    Inventors: Guang-Hwa Shiue, Che-Ming Hsu, Cheng-Fu Hsu
  • Patent number: 8890559
    Abstract: [Problems] In a connector to which unbalanced-type lines are connected, providing a connector which prevents crosstalk in the connector and an interface apparatus including the connector. [Solutions] Comprising terminals to be connected with connectors, a plurality of boards having a plurality of transmission lines, one ends of the transmission lines being connected with the terminals, a housing for fixing the plurality of boards, and common mode choke coils provided on the boards and connected with balanced-type lines.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: November 18, 2014
    Assignee: Advantest Corporation
    Inventors: Yuichiro Iwamoto, Takayuki Nakamura
  • Patent number: 8847696
    Abstract: A high speed flexible interconnect cable for an electronic assembly includes a number of conductive layers and a number of dielectric layers. Conductive signal traces, located on the conductive layers, combine with the dielectric layers to form one or more high speed electrical transmission line structures. The cable can be coupled to electronic components using a variety of connection techniques. The cable can also be terminated with any number of known or standardized connector packages.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: September 30, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: James Leroy Blair, Jeffrey Thomas Smith
  • Publication number: 20140285280
    Abstract: Disclosed is a grounding pattern structure for high-frequency connection pads of a circuit board. A substrate of the circuit board includes a component surface on which at least a pair of high-frequency connection pads. At least a pair of differential mode signal lines are formed on the substrate and connected to the high-frequency connection pads. The grounding surface of the substrate includes a grounding layer formed at a location corresponding to the differential mode signal lines. The grounding surface of the substrate includes a grounding pattern structure formed thereon to correspond to a location adjacent to the high-frequency connection pads. The grounding pattern structure is electrically connected to the grounding layer. The component surface of the substrate can be provided with a connector mounted thereto with signal terminals of the connector soldered to the high-frequency connection pads.
    Type: Application
    Filed: May 16, 2013
    Publication date: September 25, 2014
    Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.
    Inventors: CHIH-HENG CHUO, GWUN-JIN LIN, KUO-FU SU
  • Publication number: 20140266490
    Abstract: A signal line design is described herein. A circuit board may include a first signal line and a second signal line. The first signal line includes a pair of signal lines at a first depth of a section of a circuit board, wherein a centerline extends lengthwise between the pair of signal lines. The second signal line is disposed at a second depth of the circuit board. The second signal line includes a first segment that runs parallel to the first signal line at a first displacement from the center line. The second signal line includes a second segment that runs parallel to the first signal line on the other side of the center line at a second displacement distance from the center line.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Kai Xiao, Jimmy Hsu, Yuan-Liang Li, Richard K. Kunze
  • Publication number: 20140197899
    Abstract: A printed circuit board includes a plurality of wiring layers and a plurality of differential signal vias to establish connections between the plurality of wiring layers through via pairs and to be disposed so that paired-vias possessed by a specified differential signal via for transmitting a differential signal different from a signal of another differential signal via adjacent thereto are arranged on a locus of a point distanced equally from each of the paired-vias possessed by another differential signal via.
    Type: Application
    Filed: November 18, 2013
    Publication date: July 17, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Kenichi KAWAI
  • Publication number: 20140184350
    Abstract: A device is provided for use with a signal, wherein the device includes a substrate, a first signal trace and a second signal trace. The first signal trace is disposed within the substrate at a first plane from the top surface by a distance d1. The second signal trace is disposed within the substrate at a second plane from the top surface by a distance d2, wherein d2<d1<t. The first signal trace includes a first portion, whereas the second signal trace includes a second portion. The first portion is parallel to the second portion. The first signal trace and the second signal trace form a differential pair. The first signal trace is operable to conduct a positive portion of the signal, whereas the second signal trace is operable to conduct a negative portion of the signal.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Gregory Eric Howard
  • Patent number: 8742868
    Abstract: The invention is related to a microstrip line structure, which comprises: a first microstrip line and a second microstrip line, paralleled with the first mircostrip line for transferring a transmission signal, and a plurality of grooves periodically arranged on both sides of the second microstrip line by using subwavelength, and each period length in the plurality of grooves is smaller than the wavelength of the transmission signal.
    Type: Grant
    Filed: April 29, 2011
    Date of Patent: June 3, 2014
    Assignee: Chung Hua University
    Inventors: Chia-Ho Wu, Tzong-Jer Yang
  • Publication number: 20140091873
    Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.
    Type: Application
    Filed: December 5, 2013
    Publication date: April 3, 2014
    Inventor: Xiaoning Ye
  • Patent number: 8674781
    Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: March 18, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Heung-Kyu Kim
  • Publication number: 20140035701
    Abstract: A differential terminal 21a is connected to a branch line 33a which is provided in the main line close to the differential terminal 21a in the range from the intersection portion 39a to a start terminal on the line. A differential terminal 21b is connected to a branch line 37a which is provided in the main line close to the differential terminal 21b in the range from the intersection portion 39a to an end terminal on the line. A differential terminal 22a is connected to a branch line 33b which is provided in the main line close to the differential terminal 22a in the range from the intersection portion 39b to the start terminal. A differential terminal 22b is connected to a branch line 37b which is provided in the main line close to the differential terminal 22b in the range from the intersection portion 39b to the end terminal.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 6, 2014
    Applicant: ANRITSU CORPORATION
    Inventor: Fumihito Hirabayashi
  • Publication number: 20140009239
    Abstract: A network signal processing circuit assembly includes a network-on-chip, a network connector, and a processing circuit including a plurality of channels respectively and electrically connected between the network-on-chip and the network connector, a plurality of signal coupling capacitors respectively electrically coupled to the channels, and a plurality of inductor sets electrically connected in parallel between the signal coupling capacitors and the network connector for causing a back-EMF (back-electro motive force) when receiving power supply from the signal coupling capacitors.
    Type: Application
    Filed: November 21, 2012
    Publication date: January 9, 2014
    Applicant: AJOHO ENTERPRISE CO., LTD.
    Inventors: Chia-Ping MO, You-Chi LIU
  • Publication number: 20140011393
    Abstract: A communication connector comprising plug interface contacts having a plurality of conductor pairs, and corresponding cable connector contacts. A printed circuit board connects the plug interface contacts to respective cable connector contacts. The printed circuit board includes circuitry between a first conductor pair and a second conductor pair. The circuitry has a first mutually inductive coupling between a first conductor of the first conductor pair and a first conductor of the second conductor pair, a first capacitive coupling between the first conductor of the first conductor pair and the first conductor of the second conductor pair. The first capacitive coupling is approximately concurrent with the first mutually inductive coupling. A shunt capacitive coupling connects the first conductor of the second conductor pair to a second conductor of the second conductor pair.
    Type: Application
    Filed: May 30, 2013
    Publication date: January 9, 2014
    Inventors: Frank M. Straka, Melanie M. Hagar, Masud Bolouri-Saransar, Ronald A. Nordin
  • Publication number: 20140009240
    Abstract: A high-frequency module includes a mount board, a wave splitter chip mounted on one principal surface of the mount board and including a transmission filter and a reception filter, a first inductor chip mounted on one principal surface of the mount board and including an inductor, and a second inductor chip mounted on one principal surface of the mount board and including an inductor. The first and second inductor chips are disposed adjacent to each other and each has a polarity. The first and second inductor chips are disposed such that the polarities thereof are opposite to each other, as viewed from the reception filter.
    Type: Application
    Filed: August 8, 2013
    Publication date: January 9, 2014
    Applicant: Murata Manufacturing Co., Ltd.
    Inventors: Tatsuro NAGAI, Masanori KATO, Takashi KIHARA
  • Patent number: 8624687
    Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: January 7, 2014
    Assignee: Intel Corporation
    Inventor: Xiaoning Ye
  • Patent number: 8587385
    Abstract: A printed wiring board includes a first terminal array and a second terminal array comprising a plurality of terminals, a first differential signal line connecting a first terminal of the first terminal array to a predetermined number of terminals including a second terminal of the second terminal array, a second differential signal line connecting a third terminal of the first terminal array to a number of terminals including a fourth terminal of the second terminal array, which is bigger than the predetermined number of terminals wherein at least one of a line width and a line interval of one pair signal lines configuring the first differential signal line and the second differential signal line is determined so that differential impedance of the second differential signal line becomes higher compared with differential impedance of the first differential signal line.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: November 19, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kengo Umeda
  • Publication number: 20130278348
    Abstract: Some embodiments include a first differential signal pair and a second differential signal pair. The first and second differential signal pairs are arranged relative to each other in a manner to intentionally reduce or cancel crosstalk introduced by a pinout (for example, a section of a pinout, a socket, a connector, etc.) into at least one of the first differential signal pair and the second differential signal pair. Other embodiments are described and claimed.
    Type: Application
    Filed: December 19, 2011
    Publication date: October 24, 2013
    Inventor: Xiaoning Ye
  • Publication number: 20130200958
    Abstract: An electronic device comprising a laminate constituted by pluralities of insulation layers on which conductor patterns are formed; ground electrodes being formed on an upper-surface-side insulation layer and a bottom-surface-side insulation layer in the laminate; the laminate being partitioned to first and second regions by a first shield constituted by a line of via-holes electrically connecting the upper-surface-side ground electrode to the bottom-surface-side ground electrode; conductor patterns constituting a first filter for a first frequency band and conductor patterns constituting a first balun for the first frequency band being arranged in the first and second regions, respectively; pluralities of terminal electrodes being formed on bottom or side surfaces of the laminate; one of terminal electrodes of the first filter, which acts as an unbalanced port, being adjacent to a terminal electrode of the first balun, which acts as an unbalanced port, with no other terminal electrode than a ground electrode
    Type: Application
    Filed: September 12, 2011
    Publication date: August 8, 2013
    Applicant: HITACHI METALS LTD.
    Inventor: Hirotaka Satake
  • Patent number: 8502617
    Abstract: A printed circuit board includes a base, a signal layer lying on the base, and a number of pairs of differential signal traces positioned on the signal layer. The base is made of a grid of glass fiber bundles filled with epoxy resin. Each pair of differential signal traces includes a first signal trace and a second signal trace. Each of the first and second signal traces extends in a zigzag pattern. The first signal trace includes a number of wave crests and wave troughs. The wave crests define a reference straight line that connects all the wave crest of the first signal trace. The ratio of the distance from each wave crest to the reference straight line to the orthogonal distance between each wave crest and an adjacent wave trough along the reference straight line is 1:5.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 6, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Ying-Tso Lai, Yung-Chieh Chen
  • Publication number: 20130187725
    Abstract: An acoustic wave device is provided with a low-frequency side filter having a low-frequency side passband, a high-frequency side filter having a high-frequency side passband, and first and second balanced terminals. The low-frequency side filter is connected to a first unbalanced terminal. The low-frequency side passband is a frequency band from a first minimum frequency to a first maximum frequency. The high-frequency side filter is connected to a second unbalanced terminal. The high-frequency side passband is a frequency band from a second minimum frequency to a second maximum frequency. The low-frequency side filter includes a first longitudinally-coupled acoustic wave resonator and a first one-terminal pair acoustic wave resonator connected in series to the first longitudinally-coupled acoustic wave resonator. An antiresonant frequency of the first one-terminal pair acoustic wave resonator is set to be higher than the first maximum frequency and lower than the second minimum frequency.
    Type: Application
    Filed: November 7, 2011
    Publication date: July 25, 2013
    Applicant: PANASONIC CORPORATION
    Inventor: Satoru Ikeuchi
  • Publication number: 20130162364
    Abstract: A printed circuit board includes an outer signal layer, a first ground layer, a first ground layer located below the outer signal layer, an inner signal layer located below the first ground layer, an second ground layer located below the inner signal layer, and a first differential signal transmission pair and a second differential signal transmission pair laid on the outer signal layer and the inner signal layer. A value h is equal to a distance between the inner signal layer and its closest ground layer. A distance between the first pair and the second pair is not more than h×3.
    Type: Application
    Filed: December 25, 2012
    Publication date: June 27, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventor: HON HAI PRECISION INDUSTRY CO., LTD.
  • Publication number: 20130082796
    Abstract: The present invention relates to a component (BE) which has a first duplexer operating with acoustic waves and a second duplexer operating with acoustic waves, wherein the first and second duplexers are arranged in a single SMD housing. In addition, the invention relates to a module (MO), which interconnects such a component (BE) and at least three 90° hybrids (HYB1-HYB3) to form an enhanced duplexer. A further aspect of the invention relates to a 2in1 hybrid, in which two 90° hybrids (HYB3, HYB4) or one 90° hybrid (HYB3) and one 180° hybrid (BAL) are arranged on a single chip.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 4, 2013
    Applicant: EPCOS AG
    Inventor: EPCOS AG
  • Patent number: 8350637
    Abstract: A circuit substrate includes a first pair of ground lines, a second pair of ground lines, a plurality of first connection lines, a plurality of second connection lines and a plurality of conductive pillars. The first and second pairs of ground lines are located on first and second surfaces of the substrate, respectively. The pillars are located in the substrate and vertically conducted between the first pair of ground lines and the second connection lines and between the second pair of ground lines and the first connection lines, and the first and second pairs of ground lines are conducted, so that a 3-D grounding circuit loop is formed. Moreover, a first pair of signal lines is disposed between the first connection lines for grounding and a second pair of signal lines is disposed between the second connection lines for grounding to get a better signal integrity.
    Type: Grant
    Filed: April 15, 2010
    Date of Patent: January 8, 2013
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Ting-Hao Yeh
  • Patent number: 8344821
    Abstract: A printed circuit board layout method includes the following steps. A printed circuit board with a signal layer and a pair of differential transmission lines positioned on the signal layer is provided. A first distance is determined; when the distance between the pair of differential transmission lines is greater than the first distance, an eye width and an eye height of an eye diagram nearly remains the same. When a distance between the pair of differential transmission lines is less than the first distance, an eye width and an eye height of an eye diagram decreases. A second distance that is less than the first distance is set between the pair of differential transmission lines which makes the eye width and the eye height greater than a predetermined value, and which is determined by a Far End Crosstalk (FEXT) on the eye diagram when the pair differential transmission lines transmit signals.
    Type: Grant
    Filed: August 13, 2010
    Date of Patent: January 1, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventor: Yu-Hsu Lin
  • Patent number: 8324979
    Abstract: A coupled microstrip line structure having tunable characteristic impedance and wavelength are provided. In accordance with one aspect of the invention, a coupled microstrip line structure comprises a first ground plane having a plurality of first conductive strips separated by a dielectric material, and a first dielectric layer over the first ground plane. The coupled microstrip line further comprises a first signal line over the first dielectric layer, wherein the first signal line is directly above the plurality of first conductive strips, and wherein the first signal line and the plurality of first conductive strips are non-parallel, and a second signal line over the first dielectric layer, wherein the second signal line is directly above the plurality of first conductive strips, and wherein the second signal line and the plurality of first conductive strips are non-parallel, and wherein the second signal line is substantially parallel to the first signal line.
    Type: Grant
    Filed: November 12, 2009
    Date of Patent: December 4, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Shu-Ying Cho
  • Patent number: 8294529
    Abstract: A printed circuit board having a micro strip line, a printed circuit board having a strip line and a method of manufacturing thereof are disclosed. The printed circuit board having a micro strip line in accordance with an embodiment of the present invention includes a first insulation layer, a signal line buried in one surface of the first insulation layer, a plurality of conductors penetrating through the first insulation layer and being disposed on both sides of the signal line in parallel with the signal line, and a ground layer formed to be electrically connected to the conductor on the other surface of the first insulation layer.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: October 23, 2012
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Heung-Kyu Kim
  • Publication number: 20120262246
    Abstract: An elastic wave filter includes at least a piezoelectric substrate and a longitudinally coupled resonator-type elastic wave filter unit provided on the piezoelectric substrate. The longitudinally coupled resonator-type elastic wave filter unit includes first to fifth IDTs and first and second reflectors arranged on either side of the first to fifth IDTs. The third IDT includes first and second divided comb-shaped electrodes. The second and fourth IDTs are connected to an unbalanced signal terminal, the first IDT and the first divided comb-shaped electrode of the third IDT are connected to a first balanced signal terminal, and the fifth IDT and the second divided comb-shaped electrode of the third IDT are connected to a second balanced signal terminal. The first and fifth IDTs each have a constant electrode finger pitch, and the electrode finger pitch of the first IDT is less than that of the fifth IDT.
    Type: Application
    Filed: October 11, 2011
    Publication date: October 18, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventor: Junpei YASUDA
  • Patent number: 8274340
    Abstract: A signal bus includes multiple interconnects for transporting electronic signals. The interconnects have different physical path lengths and different structures to equalize the different the physical path lengths, so that the electronic signals traverse the corresponding interconnects in same period of time.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: September 25, 2012
    Assignee: Agilent Technologies, Inc.
    Inventor: Nathaniel Guilar
  • Publication number: 20120161893
    Abstract: In some embodiments a second differential signal pair is located near a first differential signal pair. The second differential signal pair switches polarity near a middle point of a routing length of the second differential signal pair. Other embodiments are described and claimed.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventor: Xiaoning Ye
  • Patent number: 8198951
    Abstract: An integrated circuit having voltage isolation capabilities includes a plurality of communications channels for transceiving data from the integrated circuit. Each of the communications channel includes capacitive isolation circuitry located in conductive layers of the integrated circuit for providing a high voltage isolation link. The capacitive isolation circuitry distributes a first portion of a high voltage isolation signal across a first group of capacitors on a first link and a second link in the capacitive isolation circuitry and distributes a second portion of the high voltage isolation signal across a second group of capacitors in the first link and the second link in the capacitive isolation circuitry. A differential receiver on each of the plurality of communications channels receives the data on the first link and the second link.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: June 12, 2012
    Assignee: Silicon Laboratories Inc.
    Inventors: Zhiwei Dong, Shouli Yan, Axel Thomsen, William W. K. Tang, Ka Y. Leung
  • Publication number: 20120032749
    Abstract: A differential signal line structure is disposed on a substrate including a signal layer, a filter layer and a grounding layer. The signal layer, the filter layer and the grounding layer are arranged from up to down and in parallel manner. The differential signal line structure accordingly includes a differential signal line group, a first wire and a first grounding circuit; the differential signal line group is disposed in the signal layer; and the first wire is disposed in the filter layer and is arranged in a corresponding position right underneath the differential signal line group. The first grounding circuit is disposed in the grounding layer and is electrically connected to an end point of the first wire through a first via.
    Type: Application
    Filed: July 13, 2011
    Publication date: February 9, 2012
    Applicant: CHUNG YUAN CHRISTIAN UNIVERSITY
    Inventors: Guang-Hwa SHIUE, Che-Ming HSU, Cheng-Fu HSU
  • Publication number: 20120001701
    Abstract: To form a signal processing circuit and an antenna apparatus that do not need a circuit to adjust resonant frequency of a resonant circuit or resonant-frequency adjustment work and that are downsized, an antenna coil and a capacitor define an antenna resonant circuit. An impedance matching circuit including capacitors, a first coil, and a second coil is provided between the antenna resonant circuit and a wireless IC. The first coil and the second coil are magnetically coupled.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Katsumi TANIGUCHI, Noboru KATO
  • Patent number: RE43957
    Abstract: In a high-frequency module, mounting lands arranged to mount at least one filter device having at least one set of an unbalanced terminal and two balanced terminals are provided at one side of a substrate top surface, and mounting lands arranged to mount at least one element electrically connected to the filter device are arranged at the opposite side. At least two of a plurality of connection terminals provided on a substrate bottom surface are respectively connected to conductor patterns connected to via-hole conductors penetrating the substrate within a mounting area for mounting the filter device via connection lines and are arranged at a pitch which is less than the pitch of the via-hole conductors.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: February 5, 2013
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Taturo Nagai