Digital Signal To Analog Resolver Or Synchro Signal Patents (Class 341/117)
  • Patent number: 9847778
    Abstract: A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: December 19, 2017
    Assignee: STMicroelectronics Asia Pacific Pte Ltd
    Inventor: Beng-Heng Goh
  • Patent number: 9645195
    Abstract: An integrated circuit (IC) is connected to an automated test equipment (ATE) with pogo pins. The IC includes an analog-to-digital converter (ADC), a voltage controlled oscillator (VCO), and a compensation circuit. The ATE provides reference voltage signals to the ADC by way of the pogo pins. A potential drop across a pogo pin introduces an error in a reference voltage signal that is reflected in a digital signal generated by the ADC. The VCO generates reference frequency signals corresponding to the reference voltage signals. The compensation circuit receives the reference frequency signals and the digital signal and generates a compensation factor signal. The compensation circuit multiplies the compensation factor signal and the digital signal to generate a compensated digital signal to compensate for the error introduced by the potential drop across the pogo pins.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: May 9, 2017
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Kumar Abhishek, Kushal Kamal, Vandana Sapra
  • Patent number: 8797195
    Abstract: The present invention is typically embodied as a portable handheld unit that generates synchro signals for input into synchro motors and other synchro devices. A primary genre of inventive application is the testing of hardware and software in synchro systems. The inventive unit typically includes a numeric keypad, an LCD display, a microcontroller, a serial-to-parallel binary data converter, and at least one digital-to-synchro converter. The keypad and display are used to enter decimal data. The microcontroller converts the decimal data to serial binary data. The serial-to-parallel binary data converter converts the serial binary data to parallel binary data. The digital-to-synchro converter(s) convert(s) the parallel binary data to synchro analog data. Some inventive embodiments implement plural digital-to-synchro converters individually corresponding to channels for independently outputting synchro signals. Each channel can represent a specific type of synchro operation, e.g.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: August 5, 2014
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Bhavesh V. Patel
  • Patent number: 8643519
    Abstract: A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 4, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold Kutz, Warren Synder, Bert Sullam, Dennis Seguine, Gajender Rohilla, Eashwar Thiagarajan
  • Patent number: 8576102
    Abstract: An analog input signal is sampled, and the sampled analog input signal is converted to a digital value. A calibration value is also sampled, and a single bit of an N bit offset value is calculated from the sampled calibration value. The sampling operations are alternatively performed so that one bit of the offset value is generated for each generated digital value. For example, the process is repeated N times to calculate all N bits of the offset value while generating N digital values.
    Type: Grant
    Filed: December 5, 2011
    Date of Patent: November 5, 2013
    Assignee: STMicroelectronics International N.V.
    Inventors: Chandrajit Debnath, Pratap Narayan Singh
  • Patent number: 8514111
    Abstract: A digital-to-synchro converter (“DSC”) is a device that converts digital signals to analog signals suitable for use by a synchro device. A conventional DSC implements complex circuitry to take digital input and generate [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Cos(?)] analog signals, and a Scott-T transformer to transform these analog signals into [V Sin({acute over (?)}t) Sin(?)], [V Sin({acute over (?)}t) Sin(?+120)], and [V Sin({acute over (?)}t) Sin(?+240)] analog signals. An inventive DSC, as typically embodied, implements a microcontroller to take digital input and generate [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Sin(?+120)] digital signals, a digital-to-analog converter to convert these digital signals to [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Sin(?+120)] analog signals, and a regular transformer (i.e.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: August 20, 2013
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Bhavesh V. Patel
  • Patent number: 8451151
    Abstract: A capacitance mismatch calibrating method for a successive approximation register ADC which includes at least one array of capacitors is provided. The method includes the following steps: firstly, at least two compensating capacitors are configured. A capacitor from the array of capacitors is selected as a capacitor-under-test. Then, the terminal voltages on the terminals of the array of capacitors and on the terminals of the compensating capacitors are determined. A first comparison voltage is outputted based on the determined terminal voltages. Afterwards, a sequence of comparisons is controlled based on the first comparison voltage and a second comparison voltage to output a sequence of corresponding digital bits. Finally, a calibration value is calculated to calibrate the value of a capacitor-under-test according to the digital bits.
    Type: Grant
    Filed: August 15, 2011
    Date of Patent: May 28, 2013
    Assignee: Himax Technologies Limited
    Inventor: Jin-Fu Lin
  • Patent number: 8446303
    Abstract: An analog-to-digital converter system that includes a pipeline including N successively-cascaded signal converters, each converting, according to a first clock signal, a respective portion of an input signal of the pipeline into digital codes, a code aligner for receiving and aligning the digital codes from the signal converters in the pipeline into a digital output of the system, an error extractor coupled to an amplifier input node of a selected one signal converter via a first switch for extracting an error signal, and a load system coupled to the amplifier input node of the selected one signal converter via a second switch.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: May 21, 2013
    Assignee: Analog Devices, Inc.
    Inventors: Ahmed Mohamed Abdelatty Ali, Bryan Scott Puckett, Joseph Michael Hensley
  • Patent number: 8441378
    Abstract: Various embodiments of methods and devices for reducing capacitor mismatch errors in a pipeline analog-to-digital converter (ADC) are disclosed. A plurality of pipeline element circuits are provided, where each pipeline element circuit corresponds to a given bit of the pipeline ADC. A first pipeline element circuit is configured to digitize analog A and B capacitor mismatch error calibration voltages generated by all the pipeline element circuits of the ADC when the pipeline ADC is operating in a capacitor mismatch calibration phase. According to one embodiment, digital representations corresponding to A and B capacitor mismatch error calibration voltages for each of the pipeline element circuits are provided to an output shift register and summing circuit, which generates capacitor mismatch error correction codes corresponding to each bit and pipeline element circuit.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: May 14, 2013
    Assignee: Pixart Imaging, Inc.
    Inventor: Vitali Souchkov
  • Patent number: 8332451
    Abstract: A CORDIC processor has a plurality of stages, each of the stages having a X input, Y input, a sign input, a sign output, an X output, a Y output, a mode control input having a ROTATE or VECTOR value, and a stage number k input, each CORDIC stage having a first shift generating an output by shifting the Y input k times, a second shift generating an output by shifting X input k times, a multiplexer having an output coupled to the sign input when the mode control input is ROTATE and to the sign of the Y input when the mode input is VECTOR, a first multiplier forming the product of the first shift output and the multiplexer output, a second multiplier forming the product of the second shift output and an inverted the multiplexer output, a first adder forming the X output from the sum of the first multiplier output and the X input, and a second adder forming the Y output from the sum of the second multiplier output and the Y input.
    Type: Grant
    Filed: November 27, 2008
    Date of Patent: December 11, 2012
    Assignee: Redpine Signals, Inc.
    Inventors: Phanimithra Gangalakurti, Karthik Vaidyanathan, Partha Sarathy Murali, InduSheknar Ayyalasomayajula
  • Patent number: 8289197
    Abstract: A system has a corrected unit, and a correction unit that performs binary search of a correction value with which an output of the corrected unit gets close to a reference value and feeds back the correction value to the corrected unit. The correction unit performs the additional comparison for comparing a first output of the corrected unit corresponding to a first correction value searched by the binary search and a second output, which is an output of the corrected unit corresponding to a second correction value that is adjacent to the first correction value and is an output that the voltage relationship to the reference value is opposite to the first output, and for selecting the first or second correction value corresponding to the first or second output closer to the reference value, and feeds back the selected correction value to the corrected unit.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: October 16, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Hiroyuki Nakamoto
  • Patent number: 8279097
    Abstract: A method of operating an analog-to-digital converter (ADC) includes providing the ADC including a plurality of stages, each including an operational amplifier, and a first capacitor and a second capacitor including a first input end and a second input end, respectively. Each of the first capacitor and the second capacitor includes an additional end connected to a same input of the operational amplifier. The method further includes performing a plurality of signal conversions. Each of the signal conversions includes, in an amplifying phase of one of the plurality of stages, applying a first voltage to the first input end of the one of the plurality of stages, randomly selecting a second voltage from two different voltages; and applying the second voltage to the second input end of the one of the plurality of stages.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: October 2, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Shi Jordan Lai, Kuo-Ming Wang, Hsu-Feng Hsueh, Cheng Yen Weng, Yung-Fu Lin
  • Patent number: 8264388
    Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 11, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Hanan Cohen, Simon Pang
  • Patent number: 8248281
    Abstract: A method for compensating a linearity error of a dual digital-to-analog converter, including the steps of receiving a digital data signal which include a plurality of bits, the digital data signal indicating a voltage signal to be generated, the plurality of bits representing a set of consecutive bits being confined within a highest bit and a lowest bit, applying a high-bit-array to a first digital-to-analog converter, the high-bit-array being composed of a consecutive sub-set of the plurality of bits of the digital data signal, the sub-set including the highest bit of the digital data signal, using at least a part of a correction data of a look-up-table for manipulating at least a part of a low-bit-array, being composed of a consecutive sub-set of the plurality of bits of the digital data signal, where the sub-set includes the lowest bit of the digital data signal.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: August 21, 2012
    Assignee: Advantest Corporation
    Inventor: Atsushi Nakamura
  • Patent number: 8144041
    Abstract: An electronic device includes a frequency variable circuit, a filter, and an output voltage decision circuit. The frequency variable circuit changes the sampling frequency of an analog-digital converter. The filter limits a pass band of an output signal of the analog-digital converter. The output voltage decision circuit determines the noise level of the output signal of the analog-digital converter after the output signal passes through the filter. The electronic device performs a self-diagnosis as follows. The frequency variable circuit changes the sampling frequency of the analog-digital converter to a frequency outside of the pass band of the filter so as to change the quantization noise level of the analog-digital converter. Then, the output voltage decision circuit determines whether the integral of the quantization noise level is within a predetermined range.
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: March 27, 2012
    Assignee: Panasonic Corporation
    Inventor: Keisuke Kuroda
  • Patent number: 8130871
    Abstract: An integrated circuit includes a radio receiver for receiving a received radio signal having a plurality of channel signals, each of the plurality of channel signals being modulated at one of a corresponding plurality of carrier frequencies. The radio receiver converts a selected one of the plurality of channel signals into a demodulated signal. An interface clock generator generates a first interface clock at a first interface clock frequency that varies based on the selected one of the plurality of channel signals. The first interface clock frequency, and integer multiples of the first clock frequency are not substantially equal to the carrier frequency of the selected one of the plurality of channel signals. A driver module drives a device interface with a device based on the first interface clock.
    Type: Grant
    Filed: January 9, 2006
    Date of Patent: March 6, 2012
    Assignee: Sigmatel, Inc.
    Inventors: Michael R. May, Erich Lowe
  • Patent number: 8125360
    Abstract: A system for the calibration of a programmable system-on-a-chip is described. More specifically, embodiments of the present invention relate to a system that calibrates a programmable analog block in a system-on-a-chip without the use of external components.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: February 28, 2012
    Assignee: Cypress Semiconductor Corporation
    Inventors: Harold Kutz, Warren Synder, Bert Sullam, Dennis Seguine, Gajender Rohilla, Eashwar Thiagarajan
  • Patent number: 8022847
    Abstract: A signal processing device, even when a steep difference in DC level is included in a signal read from a disc such as a DVD-RAM format, cuts off the DC level and pulls the read signal into an appropriate A/D input level. A steep difference in DC level between a data section and a CAPA section is absorbed by a first offset unit, and an asymmetry which occurs due to variations in the disc manufacturing stage is corrected by a second offset unit. Further, a control signal for operating the two offset units exclusively is generated by a controller, thereby controlling both offset units.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: September 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Rie Kaihara, Youichi Ogura
  • Patent number: 8018360
    Abstract: Methods and systems for mitigating latency in a data detector feedback loop are included. For example, a method for reducing latency in an error corrected data retrieval system is included. The method includes performing an analog to digital conversion at a sampling instant to create a digital sample, and performing a data detection on the digital sample to create a detected output. The detected output is compared with the digital sample to determine a phase error. During an interim period, the digital sample is adjusted to reflect the phase error to create an adjusted digital sample. After the interim period, the sampling instant is adjusted to reflect the phase error.
    Type: Grant
    Filed: May 19, 2008
    Date of Patent: September 13, 2011
    Assignee: Agere Systems Inc.
    Inventor: Ratnakar Aravind Nayak
  • Patent number: 7991359
    Abstract: A receiver has an offset application circuit for applying a known offset to an input signal, and a decision circuit for comparing the offset-applied input signal with a reference voltage. The level of the input signal is determined based on the known offset and on the result output from the decision circuit. With this configuration, a large common mode voltage can be eliminated in a circuit used for signal transmission.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: August 2, 2011
    Assignee: Fujitsu Limited
    Inventor: Hirotaka Tamura
  • Patent number: 7973685
    Abstract: Methods, and other embodiments associated with signal filtering are described. According to one embodiment, an apparatus includes an analog-to-digital converter that generates a first digital component and a second digital component from an analog signal. A filter filters the first digital component and the second digital component to substantially align the phase of the first digital component and the phase of the second digital component.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: July 5, 2011
    Assignee: Marvell International Ltd
    Inventor: Sergey Timofeev
  • Patent number: 7928872
    Abstract: An analog-to-digital converter includes a first preamplifier receiving a first reference voltage and an input signal, a second preamplifier receiving a second reference voltage and the input signal, a first preamplifier calibrator placed for the first preamplifier and adjusting an input offset of the first preamplifier, a second preamplifier calibrator placed for the second preamplifier and adjusting an input offset of the second preamplifier, an interpolator placed between output terminals of the first and second preamplifiers and generating an interpolation signal having a voltage value between a first output signal from the first preamplifier and a second output signal from the second preamplifier, comparators receiving the first output signal, the second output signal or the interpolation signal and outputting a digital value based on the received signal, and comparator calibrators placed for at least comparators receiving the interpolation signal among the comparators and adjusting input offsets of the c
    Type: Grant
    Filed: October 20, 2009
    Date of Patent: April 19, 2011
    Assignee: Renesas Electronics Corporation
    Inventor: Yuji Nakajima
  • Patent number: 7880649
    Abstract: An AD converting apparatus converts an analog input signal into a digital output signal. The apparatus includes a plurality of AD converters that are supplied with sampling clocks differing from each other by a prescribed phase and that each output an individual signal obtained by digitizing the input signal according to the sampling clock supplied thereto, a common compensating section that commonly compensates for prescribed common non-linear distortion in the individual signals, and a plurality of individual compensating sections that each individually compensate for individual non-linear distortion in a corresponding one of the individual signals. The individual non-linear distortion is obtained as a ratio between the non-linear distortion and the common non-linear distortion in each individual signal. The apparatus further includes a combining section that combines the individual signals to generate the output signal.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: February 1, 2011
    Assignee: Advantest Corporation
    Inventor: Koji Asami
  • Patent number: 7864089
    Abstract: The present invention discloses an FFT-based ADC calibration system able to solve the problems of capacitor mismatch and finite Op-Amp open loop gain, which result in that the radix of the gain of each stage is not exactly equal to 2. The present invention uses an FFT processor to calculate the real radix of each stage and uses a digital method to generate new digital outputs. As the present invention can compensate the finite gain of Op-Amp, the specification of Op-Amp is not so critical in designing ADC. Therefore, the low-gain Op-Amp can be used to reduce the power consumption of ADC. Further, the FFT-based calibration technology can considerably promote the performance of ADC.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: January 4, 2011
    Assignee: National Chung Cheng University
    Inventors: Shuenn-Yuh Lee, Ming-Chun Liang
  • Patent number: 7864090
    Abstract: In an A/D converting apparatus, a converting unit has an input terminal and an input-output characteristic. The input-output characteristic has temperature dependence, and the converting unit carries out a process of converting an input voltage signal to digital data. A temperature determining unit has information representing a relationship between a variable of an output of the converting unit and a variable of a temperature around the converting unit according to the temperature dependence of the input-output characteristic of the converting unit. When the specified voltage is applied to the input terminal of the converting unit, the temperature determining unit determines a value of the temperature around the converting unit based on the information and the specified voltage. A reducing unit reduces temperature dependence of the process of converting an input voltage signal to digital data based on the determined value of the temperature around the converting unit.
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: January 4, 2011
    Assignee: Denso Corporation
    Inventors: Hiroyoshi Yamamoto, Hiroshi Tamura
  • Patent number: 7821434
    Abstract: For digitizing analog measurement signals, an analog-to-digital converter is used, wherein the offset to be subtracted from an analog measurement value is taken to account within a locked loop by means of which an analog-to-digital converter operating according to the modulation principle is fed back.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: October 26, 2010
    Assignee: Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventor: Juergen Huppertz
  • Patent number: 7796068
    Abstract: A signal processing system for reducing calibration-related distortions in a complete-channel signal generated by a multi-channel subsystem, such as an interleaved ADC, includes a channel separator for separating the distorted digital signal into its various sub-channels and a single-channel corrector for independently processing each sub-channel to reduce distortion products present therein. The system additionally includes a subchannel re-combiner for combining the plurality of sub-channels processed by the single-channel corrector and a multi-channel corrector for calibrating each of plurality of sub-channels relative to one another to yield an equalized, complete-channel output signal. The multi-channel corrector includes a bank of optimized filters, each filter being assigned to a corresponding sub-channel of the complete-channel signal.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: September 14, 2010
    Assignee: GMR Research & Technology, Inc.
    Inventors: Gil M. Raz, Jeffrey H. Jackson
  • Patent number: 7773012
    Abstract: To prevent the value of a successive approximation register, which should be holding the value of the comparison result, from changing due to noise or the like during the A/D conversion by a successive approximation A/D converter, a detection circuit is arranged on an arbitrary bit of a successive approximation register 5 to detect the change in the value of the bit. The detection circuit detects the change in the value during the period in which the successive approximation register should be holding the data, such as during the period other than the comparison time, and outputs an abnormal conversion detection signal.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: August 10, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Chikashi Yoshinaga
  • Patent number: 7750830
    Abstract: A calibration device includes a comparison unit, a counting unit, a memory, and a compensation circuit. A residue of a sub analog-to-digital converter is compared with a first and a second voltage by the comparison unit for generating a comparison result. A number of times of the residue voltage, out of bounds defined by the first and the second voltage, is counted by the counting unit in an ith period according to the comparison result. The number of times of the residue voltage out of the bounds in an (i?1)th period is stored in the memory. A clock of the sub ADC is adjusted by the compensation circuit into a direction based on the number of times of the residue voltage out of the bounds in the ith period and the number of times of the residue voltage out of the bounds in the (i?1)th period.
    Type: Grant
    Filed: October 22, 2008
    Date of Patent: July 6, 2010
    Assignee: Industrial Technology Research Institute
    Inventors: Szu-Kang Hsien, Ta-Chun Pu
  • Patent number: 7724165
    Abstract: An audio codec and a BIST method adapted for the audio codec are provided. The BIST method includes the following steps. A first channel digital-to-analog converter (DAC) of the audio codec converts a test signal into an analog signal. A first channel analog-to-digital converter (ADC) of the audio codec converts the analog signal into a digital signal. Use a second channel DAC of the audio codec and a second channel ADC of the audio codec to calculate the magnitudes of a plurality of spectral components of the DFT of the digital signal. Determine whether the audio codec passes the test according to the magnitudes of the spectral components.
    Type: Grant
    Filed: July 17, 2008
    Date of Patent: May 25, 2010
    Assignee: Faraday Technology Corp.
    Inventors: Che-Min Lin, Chiao-Min Chen, Kuo-Hsiung Wu
  • Patent number: 7663520
    Abstract: An A/D conversion apparatus performs motor current detection in an A/D conversion period corresponding to two phases out of three phases of a sinusoidal drive motor, using reduced register resources while minimizing the number of A/D converters. The A/D conversion apparatus includes: a selection unit selecting one of a plurality of input channels; an A/D converter converting an analog signal from the selected input channel to a digital signal; a start register holding a start channel number of sequential conversion; an end register holding an end channel number of the sequential conversion; a prohibition information holding unit holding prohibition information indicating an input channel to be excluded from the sequential conversion; and a control unit causing the selection unit to select, in channel number order, input channels corresponding to channel numbers from the start channel number to the end channel number except the input channel indicated by the prohibition information.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: February 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Yuji Sugihara, Hisashi Kikue, Masaru Kohara
  • Patent number: 7652602
    Abstract: Interface unit for voltage input signals comprising two or more input channels. The input signals of these two or more input channels are connected alternately by an analog multiplexer to an analog-to-digital converter. The A/D converter comprises an integrated sigma-delta modulator circuit which generates a digitized 1-bit signal representing the input signal voltage level for a control unit irrespective of whether the input channel signal is digital or analog. By means of the invention all input voltage channels are made similar such that the input channels of the interface unit can receive an analog or digital signal irrespective of each other.
    Type: Grant
    Filed: February 8, 2008
    Date of Patent: January 26, 2010
    Assignee: ABB Oy
    Inventor: Erkki Miettinen
  • Patent number: 7620131
    Abstract: A digital clock generator includes a base clock generator for generating a base clock signal at a variable base clock frequency in response to a control signal. A digital clock controller generates a digital clock signal having a substantially constant number of digital clock cycles over a predetermined period.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: November 17, 2009
    Assignee: Sigmatel, Inc.
    Inventors: Michael R. May, Erich Lowe
  • Patent number: 7557743
    Abstract: A D/A converter has a reference comparison current generator configured to generate a reference comparison current, a first reference current generator configured to generate a first reference current capable of correcting a current level, a first D/A converting part capable of outputting a first full-scale current having a predetermined proportional relationship with the first reference current and capable of generating a first D/A converting voltage in accordance with first input digital data, and a current comparator configured to generate a difference current between the first full-scale current and the reference comparison current to determine a magnitude of the difference current. The first reference current generator corrects the first reference current based on a result determined by the current comparator.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: July 7, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shigeo Imai
  • Patent number: 7551108
    Abstract: An Inverter system includes a comparator unit compares an analog input voltage with at least one voltage threshold to judge a voltage range for the input voltage. A DC-offset unit determines a DC-offset value to limit the input voltage within a predetermined bound. The input voltage is level-shifted and amplified by a non-inverting adder unit according to the DC-offset value and a fixed gain, and then processed by an analog to digital converter (ADC) to obtain a digital count value. A microcontroller unit calculates an original value for the input analog voltage according to the voltage range and the digital count value. When the analog input voltage could be negative value, a full-wave rectifier unit and a polarity judgment unit are used to find an absolute value and a polarity of the analog input voltage for further processing.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: June 23, 2009
    Assignee: Delta Electronics, Inc.
    Inventor: Min-Jon Lee
  • Patent number: 7541958
    Abstract: A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to frequency and multiplied by correction matrices to yield a corrected, reconstructed power spectrum for the PTIC. The technique is especially effective at removing gain and phase errors introduced by individual ADCs of the PTIC, including gain and phase errors that vary with frequency.
    Type: Grant
    Filed: December 30, 2006
    Date of Patent: June 2, 2009
    Assignee: Teradyne, Inc.
    Inventor: Fang Xu
  • Patent number: 7541952
    Abstract: A method for determining a gain compensation value for multiple ADCs sums an absolute value of a number of ADC output samples from each of the ADCs that may be collected while the ADCs are in normal operation. In one embodiment, the ratio of the sums of the absolute values of ADC output samples may reflect the difference in gains between the ADCs, and may be used to determine the ADC gain compensation value. A method for determining an offset compensation value between for multiple ADCs averages of a number of ADC output samples from each ADC collected while the ADCs are in normal operation. In one embodiment, a difference between the ADC sample averages may reflect the difference in magnitudes of the ADC offsets for each ADC, and may be used to determine the ADC offset compensation value.
    Type: Grant
    Filed: October 10, 2007
    Date of Patent: June 2, 2009
    Assignee: Atheros Communications, Inc.
    Inventors: Sundar Sankaran, Tuofu Lu
  • Patent number: 7538708
    Abstract: A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to bin number. If all elements corresponding to the same bin number exceed a predetermined threshold, the elements are multiplied by correction matrices to yield corrected, DFT terms for a reconstructed power spectrum. If they do not exceed the threshold, DFT elements are processed to produce uncorrected DFT terms for the reconstructed power spectrum.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: May 26, 2009
    Assignee: Teradyne, Inc.
    Inventor: Fang Xu
  • Patent number: 7535382
    Abstract: A high speed quadrature counter for use with a displacement measuring device is disclosed. The counter provides high speed counting by partitioning the tracking counter into a small fast tracking counter portion for the LSBs and a larger slow tracking counter portion for the MSBs. The fast tracking counter portion outputs a smaller number of bits according to a fast clock rate, while the slow tracking counter portion outputs a larger number of bits to update the remainder of the position at a slower clock rate. In various embodiments, the counter provides a corrected position value that has an effective timing within a few fast clock cycles of the time of the latch trigger signal. A corrected latched position circuit corrects an error that may otherwise be produced by the partitioning and the different clock rates of the fast and slow tracking counter portions.
    Type: Grant
    Filed: October 31, 2006
    Date of Patent: May 19, 2009
    Assignee: Mitutoyo Corporation
    Inventor: Bjorn E. B. Jansson
  • Patent number: 7432837
    Abstract: A system for correcting a DC offset includes a digital-to-analog (D/A) converter module (30), a summing circuit (40), an inphase-to-quadrature (I/Q) modulator (50), a spectrum analyzer module (60) and a DC offset correction module (70). The D/A converter module converts digital control signals to analog control signals, and outputs DC offset regulating signals. The summing circuit respectively sums up the DC offset regulating signals and corresponding vectors of a base band signal. The I/Q modulator receives the summed base band signal, and converts the summed base band signal to a radio frequency (RF) signal. The spectrum analyzer module analyzes an energy variation according to a DC offset contained in the RF signal. The DC offset correction module outputs the digital control signals to adjust the DC offset regulating signals, thereby obtaining the lowest energy variation.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: October 7, 2008
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Kwo-Jyr Wong, Jane-Yi Pieh
  • Patent number: 7417571
    Abstract: A method for providing a correlation between a periodic analog/digital conversion and an angle-synchronous signal, in which the periodic analog/digital conversion is provided with a timing mark, which correlates with the angle-synchronous signal, and is assigned to an angular position of a device via this timing mark.
    Type: Grant
    Filed: May 17, 2007
    Date of Patent: August 26, 2008
    Assignee: Robert Bosch GmbH
    Inventor: Manfred Dietrich
  • Patent number: 7391347
    Abstract: A system on a chip integrated circuit includes a first digital module a second digital module such that the first digital module and the second digital module are operably coupled to generate an output signal based on an input signal, based on the first digital clock signal and the second digital clock signal. A digital clock generator generates a base clock signal at a base clock frequency that varies based on a control signal and generates a first digital clock signal having a substantially constant number of first digital clock cycles over a predetermined period and for generating a second digital clock signal having a substantially constant number of second digital clock cycles over the predetermined period.
    Type: Grant
    Filed: November 22, 2005
    Date of Patent: June 24, 2008
    Assignee: Sigmatel, Inc.
    Inventors: Michael R. May, Erich Lowe
  • Patent number: 7388528
    Abstract: Method for coding at least one datum using three digital signals A, B, C delivered on respectively one channel, in which the third signal C is delivered by a combination of the first two signals A, B in order to form m binary triplets, where m<8. The method provides for modifying the third signal C according to the data to be coded in order to generate n binary triplets, where n>1, the n triplets being different from the m triplets. A device for determining the absolute angular position of a turning member is described.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: June 17, 2008
    Assignee: SNR Roulements
    Inventor: Pascal Desbiolles
  • Patent number: 7365661
    Abstract: A control system and method for simultaneously regulating the operation of a plurality of different types of switching power converters. The system utilizes in regulating the power converters sampled data and nonlinear feedback control loops.
    Type: Grant
    Filed: November 14, 2002
    Date of Patent: April 29, 2008
    Assignee: Fyre Storm, Inc.
    Inventor: John Carl Thomas
  • Patent number: 7348910
    Abstract: A Root Mean Square (RMS) detector circuit includes a first differential pair circuit arranged to operate in a common mode. The detector circuit also includes a compensation circuit unit having a second differential pair circuit to duplicate an unwanted base current drawn by the first differential pair circuit. The compensation circuit unit is arranged to generate an offset voltage using the duplicated base current. The compensation circuit unit also has an operational amplifier coupled to an NMOS transistor so as to generate a corrective current corresponding to the offset voltage, the corrective current being mirrored by a current mirror and provided as a compensatory current to an input of the first differential pair circuit.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: March 25, 2008
    Assignee: Avago Technologies General IP Pte Ltd
    Inventors: Fesseha Tessera Seifu, Marco Fornasari, Samir Aboulhouda
  • Patent number: 7289051
    Abstract: A digital-to-analog converter may include a clock signal generator and a charge pump. The clock signal generator may be configured to generate an information clock signal responsive to a digital input signal so that different duty cycles of the information clock signal are provided for different values of the digital input signal. The charge pump may be configured to generate an analog output signal responsive to the information clock signal so that different values of the analog output signal are provided for different duty cycles of the information clock signal. Related converters, methods, and power control devices are also discussed.
    Type: Grant
    Filed: January 5, 2006
    Date of Patent: October 30, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Sang-Seob Kim
  • Patent number: 7187309
    Abstract: In an angle computation method and apparatus for a variable reluctance resolver, the maximum values Vsin(max) and Vcos(max) of sine and cosine output voltages in respective positive value ranges and the minimum values Vsin(min) and Vcos(min) of the sine and cosine output voltages in respective negative value ranges are extracted, and on the basis of these values, offset values, amplitude values, sin-cos voltage ratio, and a zero-point correction value are obtained in accordance with the following equations: VSINOFFSET=(Vsin(max)+Vsin(min))/2 VSINAMP=(Vsin(max)?Vsin(min))/2 ?SINPHASE=sin?1(VSINOFFSET/VSINAMP)?VSINOFFSET/VSINAMP VCOSOFFSET=(Vcos(max)+Vcos(min))/2 VCOSAMP=(Vcos(max)?Vcos(min))/2 K=VSINAMP/VCOSAMP On the basis of the thus-obtained values, an angle ? is obtained in accordance with the following equation: F(Vsin?VSINOFFSET, K(Vcos?VCOSOFFSET), ?SINPHASE)=?.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: March 6, 2007
    Assignee: Minebea Co., Ltd.
    Inventor: Masahiro Kobayashi
  • Patent number: 7126514
    Abstract: An inverter control microcomputer 10 comprises AD converters 21–23, a selector control circuit 31, and a selector 32. The selector 32 selects three analog signals from among inputted seven analog signals in accordance with control from the selector control circuit 31. A control signal generation section, which comprises a CPU 11 and an inverter control signal generation circuit 17, generates a motor control signal Cntl based on three digital values obtained by the respective AD converters 21–23. By performing AD conversion concurrently for arbitrary three analog signals, it is possible to eliminate a phase shift between the detected analog signals and perform motor control with high precision. Thus, it is possible to detect an analog signal necessary for control of a motor, etc., at an appropriate timing without increasing the number of AD converters.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: October 24, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Masaru Kohara
  • Patent number: 7084790
    Abstract: A device for effectuating a digital estimate of a periodic electric signal is described. The device comprising a linear DAC having an output signal, a comparator that compares the output signal of the linear DAC with the periodic electric signal, and logic circuitry having in input the output signal of the comparator and a pulse clock signal. The logic circuitry provides a first digital signal in input to the linear DAC and a second digital signal representative of the estimate of the periodic electric signal.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: August 1, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonio Borrello, Stefano Saggini, Aldo Novelli, Ignazio Bellomo
  • Patent number: 7046177
    Abstract: A servo system comprising an analog sigma delta modulator for generating a normalized digital error correction signal from first and second analog control signals. The sigma delta modulator comprises an analog low-pass filter, a quantizer delivering the digital error correction signal and a multiplying DA-converter in feedback arrangement between the output of the quantizer and the input of the low-pass filter for multiplying the feedback signals with the sum of the analog control signals.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: May 16, 2006
    Assignee: Koninklijke Philips Electronics, N.V.
    Inventors: Albert Hendrik Jan Immink, Johannes Aldegonda Theodora Maria Van Den Homberg, Aalbert Stek