Phase Or Time Of Phase Change Patents (Class 341/111)
  • Patent number: 10270394
    Abstract: Embodiments described herein relate to an envelope tracking system that uses a single-bit digital signal to encode an analog envelope tracking control signal, or envelope tracking signal for brevity. In certain embodiments, the envelope tracking system can estimate or measure the amplitude of the baseband signal. The envelope tracking system can further estimate the amplitude of the envelope of the RF signal. The system can convert the amplitude of the envelope signal to a single-bit digital signal, typically at a higher, oversample rate. The single-bit digital signal can be transmitted in, for example, a low-voltage differential signaling (LVDS) format, from a transceiver to an envelope tracker. An analog-to-digital converter (ADC or A/D) can convert the single-bit digital signal back to an analog envelope signal. Moreover, a driver can increase the power of the A/D output envelope signal to produce an envelope-tracking supply voltage for a power amplifier.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: April 23, 2019
    Assignee: Skyworks Solutions, Inc.
    Inventors: Serge Francois Drogi, Florinel G. Balteanu, Luigi Panseri, Craig Joseph Christmas, Paul T. DiCarlo
  • Patent number: 10168183
    Abstract: A system and a method for determining a failure within a resolver are provided. The method includes detecting signals output from the resolver. In addition, an average value and a deviation value of the detected signals are calculated. Further, the controller is configured to determine a disconnection or a short circuit of the resolver using the calculated average value and deviation value.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 1, 2019
    Assignee: Hyundai Motor Company
    Inventors: Hyun Min Park, Tae Young Chung
  • Patent number: 9709830
    Abstract: A phase modulation device including a diode-type phase modulator having a pair of side terminals connected to two sides of an optical waveguide core along an optical axis of the optical waveguide core, and a control unit that controls electrical signals to be input to the phase modulator, the side terminal of the phase modulator being divided into a plurality of portions along the optical axis of the optical waveguide core, the phase modulator having electrodes 15 respectively provided on the divided side terminals and electrically separated from each other, the control unit having switches and constant-current sources connected to the electrodes of the side terminals and controls stepwise the amount of change in phase of propagating light in the optical waveguide core according to the number of the switches turned on.
    Type: Grant
    Filed: March 2, 2015
    Date of Patent: July 18, 2017
    Assignee: FUJITSU LIMITED
    Inventor: Suguru Akiyama
  • Patent number: 9514812
    Abstract: According to an example, a method for storage device reading may include receiving an input signal indicative of a period of oscillation of a ring oscillator coupled to a storage device of a plurality of storage devices, and measuring the period of oscillation of the ring oscillator by a time-to-digital circuit. The method for storage device reading may further include determining a value of data stored in the storage device based on the measurement.
    Type: Grant
    Filed: March 28, 2013
    Date of Patent: December 6, 2016
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Robert J. Brooks
  • Patent number: 9406282
    Abstract: A device includes a timing test circuit. The timing test circuit receives a timing signal related to the display of an image on a display. The timing test circuit also determines if the timing signals are invalid. Moreover, the timing test circuit transmits a fault indication when the timing signals are determined to be invalid.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: August 2, 2016
    Assignee: APPLE INC.
    Inventors: Jason N. Gomez, James C. Aamold, Sandro H. Pintz, Paolo Sacchetto
  • Patent number: 9329057
    Abstract: Presented herein is a magnetic field sensor architecture that uses outputs of a peak detector and threshold detector operating in parallel to detect magnetic anomalies that may be associated with the target being sensed, e.g., a rotational ferromagnetic object such as a toothed gear, and use such detection to prevent sensor malfunction. The sensor includes an edge detection circuit and an error detection circuit. In one embodiment, the edge detection circuit includes circuits to detect edges (or transitions) of the threshold and peak detector output signals and the error detection circuit includes circuits, responsive to the edge detection circuit, to indicate an error when a “missed transition” occurs or a peak-to-peak value of an input signal as detected by the peak detector for a current cycle differs from an expected peak-to-peak value by a predetermined amount.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 3, 2016
    Assignee: Allegro Microsystems, LLC
    Inventors: Andrea Foletto, Michael Morris, Mathew Drouin, Devon Fernandez, Andreas P. Friedrich, P. Karl Scheller
  • Patent number: 9288841
    Abstract: This application discusses, among other things, apparatus and methods for sharing a local oscillator between multiple wireless devices. In certain examples, an apparatus can include a central frequency synthesizer configured to provide a central oscillator signal having a first frequency, a first transmitter, the first transmitter including a first transmit digital-to-time converter (DTC) configured to receive the central oscillator signal and to provide a first transmitter signal having a second frequency, and a first receiver, the first receiver including a first receive DTC configured to receive the central oscillator signal and to provide a first receiver signal having a first receive frequency.
    Type: Grant
    Filed: December 23, 2013
    Date of Patent: March 15, 2016
    Assignee: Intel IP Corporation
    Inventors: Hasnain Lakdawala, Ashoke Ravi, Ofir Degani, Bernd-Ulrich Klepser, Zdravko Boos, Georgios Palaskas, Stefano Pellerano, Paolo Madoglio
  • Patent number: 9267814
    Abstract: A system (1) is described for determining offsets (?) of measuring instruments, in particular of measures with a null or constant mean value, composed of first processing means (3) adapted to compute, from at least one value of a measuring signal (S) deriving from an instantaneous measure performed by at least one measuring instrument or a sensor, at least one offset value (?) of such signal (S); and second processing means (5) adapted to subtract such offset value (?) from the value of the instantaneous measure signal (S) to obtain a corrected measure value (S??) of such signal S. A process is also described for determining offsets (?) of measuring instruments, in particular of measures with a null or constant mean value.
    Type: Grant
    Filed: September 13, 2011
    Date of Patent: February 23, 2016
    Assignee: PSC ENGINEERING S.R.L.
    Inventor: Santino Crupi
  • Patent number: 9093951
    Abstract: One embodiment of the present invention features a poly-phase local oscillator generator combining frequency dividers and direct-injection-locked phase correctors. The poly-phase local oscillator generator comprises a plurality of phase correctors configured to relax frequency and tuning range of a reference local oscillator (LO), and a plurality of frequency dividers, coupled to the phase correctors, configured to offer different frequency segments. The phase correctors are expandable, so that phase accuracy can be optimized by cascading more of themselves.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: July 28, 2015
    Assignee: UNIVERSITY OF MACAU
    Inventors: Ka-Fai Un, Pui-In Mak, Rui Paulo da Silva Martins
  • Patent number: 9081370
    Abstract: A time-to-digital converter includes first and second phase distribution circuits and N time-to-digital conversion circuits. The first and second phase distribution circuits each includes a plurality of frequency dividers connected in a tree structure. The first and second phase distribution circuits each divides a signal received by the frequency dividers of root nodes into N signals. The first and second phase distribution circuits each outputs the N signals each having a different phase. The N time-to-digital conversion circuits each converts a phase difference between an i-th signal (where i is an integer from 0 to N?1) that is output from the first phase distribution circuit and another i-th signal that is output from the second phase distribution circuit into a digital value.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: July 14, 2015
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Shiro Dosho
  • Patent number: 9063518
    Abstract: The solution according to the invention consisting in conversion of a time interval to a digital word of a number of bits equal to n by the use of the array (A) of binary-scaled capacitors (Cn-1, . . . , C0) is characterized in that the time interval whose both start and end are detected by the control module (CM) is first mapped to a portion of electric charge delivered by the current source (I) and successively accumulated in the capacitors ((Cn-1, . . . , C0)) in the order of decreasing capacitances starting from the capacitor (Cn-1) having the highest capacitance value in the array, and when the control module (CM) detects the end of the time interval, the charge accumulated in the capacitor (Cx) charged recently is successively transferred by the use of the current source (I) to the capacitors of lower capacitance values.
    Type: Grant
    Filed: June 5, 2011
    Date of Patent: June 23, 2015
    Assignee: AKADEMIA GORNICZO-HUTNICZA IM. STANISLAWA STASZICA, AL.
    Inventors: Dariusz Koscielnik, Marek Miskowicz
  • Patent number: 9024793
    Abstract: An oversampling time-to-digital converter includes an input pulse generation circuit generating two pulse signals, a reference pulse generation circuit generating two pulse signals, a swap circuit swapping two pulse signals, a multiplexer selecting an output of the input pulse generation circuit or the swap circuit, a time-to-current conversion circuit outputting two pulse currents in accordance with an output of the multiplexer, a current mirror circuit whose input and output terminals receive the two pulse currents, an integration circuit integrating a differential current between the pulse current connected to the output terminal of the current mirror circuit and an output current of the current mirror circuit, and a comparison circuit comparing an output signal of the integration circuit to a threshold voltage. An output signal of the comparison circuit is given to the swap circuit as a control signal.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: May 5, 2015
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Shiro Dosho, Masao Takayama
  • Patent number: 9020088
    Abstract: The present invention proposes a digital system and method of measuring (estimating) non-energy parameters of the signal (phase, frequency and frequency rate) received in additive mixture with Gaussian noise. The first embodiment of the measuring system consists of a PLL system tracking variable signal frequency, a block of NCO full phase computation (OFPC), a block of signal phase primary estimation (SPPE) and a first type adaptive filter filtering the signal from the output of SPPE. The second embodiment of the invention has no block SPPE, and NCO full phase is fed to the input of a second type adaptive filter. The present invention can be used in receivers of various navigation systems, such as GPS, GLONASS and GALILEO, which provide precise measurements of signal phase at different rates of frequency change, as well as systems using digital PLLs for speed measurements.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: April 28, 2015
    Assignee: Topcon Positioning Systems, Inc.
    Inventors: Mark I. Zhodzishsky, Victor A. Prasolov, Alexey S. Lebedinsky, Daniel S. Milyutin
  • Patent number: 8957793
    Abstract: Aspects of the disclosure provide a method. The method includes boosting a portion of frequency components of a digital signal that is converted from an analog signal based on a clock signal, generating a decision signal based on the boosted digital signal, generating a timing error signal based on the boosted digital signal and the decision signal, and filtering the timing error signal to generate a voltage signal to control a voltage controlled oscillator to generate the clock signal.
    Type: Grant
    Filed: September 10, 2012
    Date of Patent: February 17, 2015
    Assignee: Marvell International Ltd.
    Inventors: Jingfeng Liu, Mats Oberg, Zachary Keirn, Bin Ni
  • Patent number: 8797194
    Abstract: One embodiment includes a phase-based analog-to-digital converter (ADC) system. The system includes a voltage-to-phase converter configured to convert an input voltage to a phase difference corresponding to a phase-delay with respect to an input clock signal that is based on a magnitude of the input voltage. The system also includes a phase-to-digital converter configured to convert the phase difference into a digital output signal having a digital value corresponding to a magnitude of the phase difference.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: August 5, 2014
    Assignee: The Ohio State University
    Inventors: Yiqiao Lin, Mohammed Ismail El-nagger
  • Patent number: 8779951
    Abstract: According to one embodiment, a multi-bit delta-sigma time digitizer circuit includes a delay array including delay selection circuits respectively including a delay element and a multiplexer, a phase comparator calculating a time difference, an integrator integrating the time difference output, a flash A/D converter executing digital conversion, a ring oscillation circuit including the delay array, a counter measuring a number of clock signal pulses, a memory storing a delay value of the delay element, and a processor correcting an output result of the A/D converter based on the delay value when the rising timing interval is measured.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: July 15, 2014
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Satoshi Uemori, Masamichi Ishii, Haruo Kobayashi
  • Patent number: 8742960
    Abstract: A phase digitizing system includes an analog-to-digital converter (ADC), multiple phase accumulators and a processing device. The ADC generates sample segments of digital signal waveform samples based on an analog composite input signal received in a measurement channel, the composite input signal includes a first signal having a first frequency F1 and a second signal imported from a reference channel having a second frequency F2. The processing device is coupled to the phase accumulators, and digitally processes each sample segment with outputs of the phase accumulators, and continually generates digital phase data The processing device further provides increment values to each of the phase accumulators based on the digital phase data, causing an output of a first phase accumulator to represent an instantaneous phase of the first signal, and an output of a second phase accumulator to represent an instantaneous phase of the second signal.
    Type: Grant
    Filed: September 26, 2012
    Date of Patent: June 3, 2014
    Assignee: Agilent Technologies, Inc.
    Inventors: Daniel White, Nhan T. Nguyen, Janet L. Yun
  • Publication number: 20140085116
    Abstract: A phase digitizing system includes an analog-to-digital converter (ADC), multiple phase accumulators and a processing device. The ADC generates sample segments of digital signal waveform samples based on an analog composite input signal received in a measurement channel, the composite input signal includes a first signal having a first frequency F1 and a second signal imported from a reference channel having a second frequency F2. The processing device is coupled to the phase accumulators, and digitally processes each sample segment with outputs of the phase accumulators, and continually generates digital phase data The processing device further provides increment values to each of the phase accumulators based on the digital phase data, causing an output of a first phase accumulator to represent an instantaneous phase of the first signal, and an output of a second phase accumulator to represent an instantaneous phase of the second signal.
    Type: Application
    Filed: September 26, 2012
    Publication date: March 27, 2014
    Applicant: AGILENT TECHNOLOGIES, INC.
    Inventors: Daniel White, Nhan T. Nguyen, Janet L. Yun
  • Patent number: 8659360
    Abstract: The charge-to-digital timer apparatus and method disclosed herein estimates the elapsed time between two signals, e.g., a start signal and a stop signal. To that end, at least a capacitive load is charged with a known current to generate a load voltage. Subsequently, a first voltage is ramped in a plurality of discrete voltage steps associated with a plurality of known capacitances until the ramped voltage satisfies a predetermined criterion relative to a second voltage. The elapsed time is determined from the discrete voltage steps, one of the first and second voltages, the known current, and the known capacitive load.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: February 25, 2014
    Assignee: St-Ericsson SA
    Inventors: Petri Heliö, Petri Korpi, Niko Mikkola, Paavo Väänänen, Sami Vilhonen
  • Patent number: 8655176
    Abstract: A system and methods are provided for converting a first temporally short and spectrally broad optical pulse into a train of spectrally narrow and distinct optical pulses. This involves receiving, on a first I/O channel, the first optical pulse associated with a plurality of wavelengths and performing wavelength division demultiplexing on the first optical pulse at an optical unit housed on an optical chip to output a plurality of second optical pulses on different ones of a plurality of second I/O channels, each of the second optical pulses associated with a unique wavelength range from the first optical pulse. This also involves receiving the second optical pulses at loop mirrors in the second I/O channels, wherein the second I/O channels are patterned as waveguides in the optical chip and reflecting, at the loop mirrors, the second optical pulses back to the optical unit.
    Type: Grant
    Filed: January 27, 2010
    Date of Patent: February 18, 2014
    Assignee: Telcordia Technologies, Inc.
    Inventor: Janet Jackel
  • Patent number: 8581759
    Abstract: A phase to digital conversion circuit with improved resolution for a rotary traveling wave oscillator. The phase to digital conversion circuit connects with a closed loop transmission line via a plurality of signal lines or nodes distributed along the transmission line. As an oscillating signal propagates around the transmission line, a time waveform of the signal at each of the plurality of signal lines is transmitted to a corresponding plurality of latches. Upon a triggering condition, the plurality of latches simultaneously samples the signals from the plurality of signal lines. At least two reference clock signals are switchably coupled with the plurality of latches latch for triggering the plurality of latches based on an edge transition in each of the reference clock signals compared with an edge transition in each of the signals from the plurality of taps.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: November 12, 2013
    Assignee: Panasonic Corporation
    Inventors: Richard W. D. Booth, Koji Takinami
  • Patent number: 8531322
    Abstract: Embodiments of a time-to-digital converter are provided, comprising a delay stage matrix and a measurement circuit. The delay stage matrix comprises a first and a second delay lines coupled thereto, and is arranged to propagate a transition signal from a starting delay stage in the first and a second delay lines, wherein each of the first and second delay lines comprises a same number of delay stages coupled in series, each delay stage in one of the first and second delay lines is coupled to a corresponding delay stage in the other delay line and operative to generate a delayed signal. The measurement circuit is arranged to determine a time of the transition signal propagating along the delay stages by sampling the delayed signals using a measurement signal to generate and hold a digital representation of the time.
    Type: Grant
    Filed: April 18, 2012
    Date of Patent: September 10, 2013
    Assignee: Mediatek Singapore Pte. Ltd.
    Inventors: Changhua Cao, Xiaochuan Guo, Yen-Horng Chen, Caiyi Wang
  • Patent number: 8519880
    Abstract: An AD converter includes a VT converter circuit part which inputs an analog input voltage and a sampling clock, converts the analog input voltage to a corresponding delay time, and outputs time domain data. A ring oscillator circuit part of N stages inputs the time domain data, and an error propagation circuit part takes out delay information containing a quantization error from phase information of the ring oscillator circuit part of the previous stage, and propagate the delay information to the ring oscillator circuit part of a subsequent stage. A counter circuit part measures a number of waves of an output oscillation waveform of the ring oscillator circuit part of each stage, and an output signal generator part generates an output signal from an output counted value of each counter circuit part. A reset part resets each error propagation circuit part and each counter circuit part with a sampling clock.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 27, 2013
    Assignee: Semiconductor Technology Academic Research Center
    Inventors: Hiroshi Kawaguchi, Masahiko Yoshimoto, Toshihiro Konishi, Shintaro Izumi
  • Patent number: 8514111
    Abstract: A digital-to-synchro converter (“DSC”) is a device that converts digital signals to analog signals suitable for use by a synchro device. A conventional DSC implements complex circuitry to take digital input and generate [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Cos(?)] analog signals, and a Scott-T transformer to transform these analog signals into [V Sin({acute over (?)}t) Sin(?)], [V Sin({acute over (?)}t) Sin(?+120)], and [V Sin({acute over (?)}t) Sin(?+240)] analog signals. An inventive DSC, as typically embodied, implements a microcontroller to take digital input and generate [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Sin(?+120)] digital signals, a digital-to-analog converter to convert these digital signals to [V Sin({acute over (?)}t) Sin(?)] and [V Sin({acute over (?)}t) Sin(?+120)] analog signals, and a regular transformer (i.e.
    Type: Grant
    Filed: June 4, 2012
    Date of Patent: August 20, 2013
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Bhavesh V. Patel
  • Patent number: 8481915
    Abstract: An linear encoder includes: a scale; a light-emitting element that emits light onto the scale; a detecting head that has a light-receiving element that receives the light emitted by the light-emitting element to be reflected or transmitted by the scale; and a connector connected to the detecting head via a cable. The connector comprises a display that displays a status of the light received by the light-receiving element and a connector controller that controls the display. The connector controller includes a display controller that controls the display in accordance with the intensity of the light received by the light-receiving element.
    Type: Grant
    Filed: March 23, 2011
    Date of Patent: July 9, 2013
    Assignee: Mitutoyo Corporation
    Inventors: Takanori Otsuka, Michio Nakamura, Mikiya Teraguchi
  • Patent number: 8466644
    Abstract: First and second A/D converters perform analog/digital conversion of first and second signals of a Hall signal so as to generate third and fourth signals as digital signals. A differential conversion circuit generates a fifth signal as a single-ended signal that corresponds to the difference between the third and fourth signals. An offset correction circuit corrects offset of the fifth signal so as to generate a sixth signal. An amplitude control circuit stabilizes the amplitude of the sixth signal to a predetermined target value, and generates its absolute value, thus generating a seventh signal. A control signal generating unit generates a control signal based upon the seventh signal. A driver circuit drives a motor according to the control signal.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: June 18, 2013
    Assignee: Rohm Co., Ltd.
    Inventors: Tatsuro Shimizu, Hiroyuki Ishii, Nobuo Komura, Toshiya Suzuki
  • Patent number: 8446302
    Abstract: According to one embodiment, a multiphase circuit, a flip-flop, and a decoder are provided. The multiphase circuit generates multiphase signals of which phases are different from each other by 180/M degrees by dividing a differential oscillation signal by M (M is an integral number not smaller than 2). The flip-flop captures the multiphase signal in synchronization with an input of a reference signal. The decoder decodes an output signal of the flip-flop.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: May 21, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Daisuke Miyashita
  • Patent number: 8416902
    Abstract: A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.
    Type: Grant
    Filed: January 14, 2010
    Date of Patent: April 9, 2013
    Inventors: Ian Kyles, Eugene Pahomsky
  • Patent number: 8362932
    Abstract: Calibration data for calibrating time to digital conversion is obtained by switching a feed circuit of a time to digital converter between a normal operating mode or a calibration mode. A delay circuit with a delay circuit input and a plurality of taps outputs. A sampling register samples data from the data inputs. The feed circuit provides for selection of transitions of the oscillator signal that control timing of a first active transition at the clock circuit after a transition at the delay circuit input. A control circuit switches the feed circuit between normal operating mode and calibration mode, and controls the feed circuit successively to select a plurality of different transitions to control timing of the first active transition in the calibration mode. The control circuit reads out resulting data from the sampling register for each selection and determines calibration data for the oscillator signal from said data.
    Type: Grant
    Filed: June 30, 2009
    Date of Patent: January 29, 2013
    Assignee: ST-Ericsson SA
    Inventors: Nenad Pavlovic, Manel Collados Asensio, Xin He, Jan Van Sinderen
  • Patent number: 8362933
    Abstract: Provided are a TDC having a pipeline or cyclic structure and an operating method thereof. The TDC includes a first stage block and a second stage block. The first stage block detects a first bit of a digital code for a time difference between first and second input signals. The second stage block detects a second bit of the digital code for a time difference between first and second output signals of the first stage block. The first stage block amplifies a time difference between first and second delay signals for the first and second input signals to generate the first and second output signals, and transfers the first and second output signals to the second stage block.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: January 29, 2013
    Assignee: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: Yeomyung Kim, Tae Wook Kim
  • Patent number: 8339295
    Abstract: A method and system for managing Digital to Time Conversion (DTC) is provided. The method comprises receiving a first Radio Frequency (RF) signal and a second RF signal. The second RF signal is a phase-shifted first RF signal. The method further comprises converting the first RF signal to a first Intermediate Frequency (IF) signal and the second RF signal to a second IF signal. Further, a time delay between the first IF signal and the second IF signal is estimated based on a time difference measurement technique. The second RF signal is processed based on the estimated time delay to compensate for a delay error associated with the second RF signal.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: December 25, 2012
    Assignee: Motorola Solutions, Inc.
    Inventors: Geetha B. Nagaraj, Nicholas G. Cafaro, Ralf Hekmann, Robert E. Stengel, Scott Miller
  • Patent number: 8330630
    Abstract: A circuit arrangement is described comprising a first receiver configured to receive a first input signal, a second receiver configured to receive a second input signal, a first signal generator configured to generate a first pulse signal, a second signal generator configured to generate a second pulse signal, wherein a delay between a rising edge of the first pulse signal and a rising edge of the second pulse signal is proportional to a difference between the first input signal and the second input signal, a first converter configured to convert the first pulse signal to a first digital number proportional to a width of the first pulse signal, a second converter configured to convert the second pulse signal to a second digital number proportional to a width of the second pulse signal, wherein at least one of the first converter and the second converter comprises a cascade of at least two converter stages, wherein each converter stage of the at least two converter stages is configured to propagate and shrink
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: December 11, 2012
    Assignee: NXP, N.V.
    Inventor: Herve Marie
  • Patent number: 8310384
    Abstract: A phase digitizing apparatus for generating a corresponding digital value in response to a phase of an input signal is provided. The phase digitizing apparatus includes a coarse phase generator, for generating a coarse phase code according to the phase of the input signal and a first time unit; a fine phase code generator, for generating a fine phase code according to the phase of the input signal and a second time unit; and a calculating unit, for generating the digital value according to the coarse phase code and the fine phase code; wherein the first time unit is greater than the second time unit.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: November 13, 2012
    Assignee: MStar Semiconductor, Inc.
    Inventors: Po Lin Yeh, Chien-Hsing Lin, Shao Ping Hung, Chih-Tien Chang, Chun-Chia Chen, Jui-Hua Yeh
  • Patent number: 8274413
    Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.
    Type: Grant
    Filed: September 8, 2010
    Date of Patent: September 25, 2012
    Assignee: Marvell International Ltd.
    Inventors: Jingfeng Liu, Mats Oberg, Zachary Keirn, Bin Ni
  • Patent number: 8264388
    Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: September 11, 2012
    Assignee: Applied Micro Circuits Corporation
    Inventors: Hanan Cohen, Simon Pang
  • Patent number: 8238017
    Abstract: An optical path is configured to propagate an input optical signal. A plurality of electrodes are configured to produce a plurality of discrete phase shifts on the optical signal. An output optical signal is phase-shifted with respect to the input optical signal by a sum of the plurality of discrete phase shifts.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: August 7, 2012
    Assignee: Alcatel Lucent
    Inventors: Kun-Yii Tu, Ting-Chen Hu, Young-Kai Chen
  • Patent number: 8193955
    Abstract: The inventive data conversion device is typically embodied as a modular unit including a PCBA and a frame that houses it. The PCBA includes a PCB and electronic components mounted thereon including a computer and one or more conventional conversion devices, viz., at least one conventional synchro-to-digital converter and/or at least one conventional digital-to-synchro converter. According to typical inventive synchro-to-digital conversion, analog synchro data (received from a synchro) is converted by the synchro-to-digital converter(s) to lower-level-format parallel-binary-angle digital synchro data, which in turn is converted by the computer to higher-level-format digital synchro data.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: June 5, 2012
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventor: Charles J. Hermann
  • Patent number: 8159173
    Abstract: A control device for a travel motor mounted to a vehicle has a resolver which works as a rotation-angle sensor. The control device has a RDC which calculates a rotation-angle output value ? based on rotation detection signals Sa, Sb transferred from the resolver. The control device supplies electric power to the travel motor based on the rotation angle output value ?. The RDC calculates “sin(???)” as an error deviation ? based on the signals Sa and Sb and the rotation-angle output value ?. The RDC calculates an angular acceleration by multiplying the error deviation ? with a gain (=Ka·Kb), and integrates the angular acceleration two times in order to obtain a next rotation-angle output value. A gain control part of the RDC decreases the gain when the judgment means judges that the travel motor rotates at a constant rotation speed.
    Type: Grant
    Filed: August 6, 2010
    Date of Patent: April 17, 2012
    Assignee: Denso Corporation
    Inventors: Shigenori Mori, Eiichiro Kawakami
  • Patent number: 7880657
    Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with motion encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. Problems with noise spikes common to zero-hysteresis comparators typically employed in interpolation circuits are eliminated, as are problems with time delays differing between comparators that do feature hysteresis. The disclosed interpolation circuits may be implemented using CMOS processes without undue effort.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: February 1, 2011
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Mei Yee Ng, Gim Eng Chew
  • Patent number: 7880658
    Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with optical encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. The disclosed interpolation circuits may be implemented using CMOS or BiCMOS processes without undue effort.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: February 1, 2011
    Assignee: Avago Technologies ECBU IP (Singapore) Pte. Ltd.
    Inventors: Kheng Hin Toh, Gim Eng Chew
  • Publication number: 20110018748
    Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes an analog to digital converter, a digital interpolation circuit, a phase error circuit, and a phase adjustment control circuit. The analog to digital converter samples an analog data input at a sampling phase governed at least in part by a coarse control, and provides a series of digital samples. The digital interpolation circuit interpolates between a subset of the series of digital samples based at least in part on a fine control. The phase error circuit calculates a phase error value. The phase adjustment control circuit is operable to determine the coarse control and the fine control based at least in part on the phase error value.
    Type: Application
    Filed: July 27, 2009
    Publication date: January 27, 2011
    Inventors: Nayak Ratnakar Aravind, James A. Bailey, Robert H. Leonowich
  • Patent number: 7831358
    Abstract: Land-based vehicle including an arrangement for monitoring objects in or about a vehicle includes a source from which modulated illumination is emitted into an area in or about the vehicle, a receiver arranged to receive illumination reflected from an object in the path of the modulated illumination, and circuitry coupled to the receiver and the source and arranged to compare a phase of the modulated illumination with a phase of the reflected radiation at a common frequency to determine whether there is a phase difference between the modulated illumination and the reflected illumination. The phase difference is a measure of a property of the object, such as the distance between the object and the source/receiver, which can be co-located. Otherwise, if the source and receiver and not co-located or substantially co-located, the distance is a measure of the distance of travel of the illumination.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: November 9, 2010
    Assignee: Automotive Technologies International, Inc.
    Inventors: David S. Breed, Wendell C. Johnson, Wilbur E. DuVall
  • Patent number: 7825836
    Abstract: A timing loop for generating a channel clock signal for driving an analog to digital converter (ADC) includes a slicer bias loop configured to generate an asymmetry compensation signal for a digital output signal from the ADC, the first adder configured to asymmetrically compensate the digital output signal based on the asymmetry compensation signal from the slicer bias loop, a limit equalizer configured to limit a boost range of the asymmetrically compensated digital output signal from the adder, a slicer configured to generate a temporary decision signal based on the asymmetrically compensated digital output signal from the limit equalizer, a phase detector configured to generate a timing error signal based on the asymmetrically compensated digital output signal from the limit equalizer and the temporary decision signal from the slicer; and the first filter configured to generate a clock signal for driving the ADC based on the time error signal from the phase detector.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: November 2, 2010
    Assignee: Marvell International, Ltd
    Inventors: Jingfeng Liu, Mats Oberg, Zachary Keirn, Bin Ni
  • Patent number: 7817070
    Abstract: A signal conditioning circuit time share multiplexes anti-aliasing filters and an A/D converter. A plurality of first tier multiplexers each time share multiplex one of a plurality of antialiasing filters between a plurality of AC or baseband input signals from a plurality of sensors. A second tier multiplexer selects its inputs from the outputs of the first tier multiplexers. The output of the second tier multiplexer feeds a high speed A/D converter. Thus, the A/D converter is time share multiplexed by the second tier multiplexer. In this manner, a plurality of sensors can share a single A/D converter. After allowing a settling time for the multiplexers and antialiasing filters, a plurality of samples of the input signals are taken, such as for one period. The samples of each AC input signal are multiplied by a sine vector and a cosine vector. The product vectors are then each averaged and the root mean square of the two averages yields the magnitude of the input signal.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: October 19, 2010
    Assignee: Hamilton Sundstrand Corporation
    Inventor: John E. Games
  • Publication number: 20100214139
    Abstract: Disclosed are various embodiments of interpolation circuits for use in conjunction with optical encoders. The analog output signals provided by incremental or absolute motion encoders are provided to an interpolation circuit, which is capable of providing high interpolation factor output signals having high timing accuracy. The disclosed interpolation circuits may be implemented using CMOS or BiCMOS processes without undue effort.
    Type: Application
    Filed: July 31, 2009
    Publication date: August 26, 2010
    Applicant: Avago Technologies ECBU (Singapore) Pte. Ltd.
    Inventors: Kheng Hin Toh, Gim Eng Chew
  • Patent number: 7773008
    Abstract: A signal conditioning circuit time share multiplexes anti-aliasing filters and an A/D converter. A plurality of first tier multiplexers each time share multiplex one of a plurality of antialiasing filters between a plurality of AC or baseband input signals from a plurality of sensors. A second tier multiplexer selects its inputs from the outputs of the first tier multiplexers. The output of the second tier multiplexer feeds a high speed A/D converter. Thus, the A/D converter is time share multiplexed by the second tier multiplexer. In this manner, a plurality of sensors can share a single A/D converter. After allowing a settling time for the multiplexers and antialiasing filters, a plurality of samples of the input signals are taken, such as for one period. The samples of each AC input signal are multiplied by a sine vector and a cosine vector. The product vectors are then each averaged and the root mean square of the two averages yields the magnitude of the input signal.
    Type: Grant
    Filed: August 28, 2008
    Date of Patent: August 10, 2010
    Assignee: Hamilton Sundstrand Corporation
    Inventor: John E. Games
  • Publication number: 20100097251
    Abstract: A method, system, and apparatus of a balanced rotator conversion of serialized data are disclosed. In one embodiment, a method to convert serialized data includes acquiring a rotator module output, and generating a balancing signal with a reference module, which operates with a reference frequency. The method further includes processing the rotator module output and the balancing signal in an interpolation module to generate a balanced rotator output. The method may include a rotator module output that is generated by an analog phase rotator when a control voltage is received by the analog phase rotator. The reference module may include an other analog phase rotator to generate a balancing signal. The interpolation module may interpolate the balancing signal and the rotator module output to modulate a phase of the balanced rotator output. The balanced rotator output may include an orthogonal output.
    Type: Application
    Filed: October 20, 2008
    Publication date: April 22, 2010
    Inventors: Yin LIU, Guangyong ZHAO, Huaming CHONG
  • Patent number: 7701374
    Abstract: A system for determining an optimal sampling phase is provided. The system includes a plurality of analog to digital converters, each receiving an analog signal and a clock phase signal and generating an output. A clock generator receives a reference clock and generates a plurality of clock phase signals. A sampling phase system receives the plurality of outputs of the analog to digital converters and generates an optimal sampling phase.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: April 20, 2010
    Assignee: Conexant Systems, Inc.
    Inventor: Costantino Pala
  • Publication number: 20090256601
    Abstract: A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.
    Type: Application
    Filed: April 14, 2008
    Publication date: October 15, 2009
    Applicant: QUALCOMM INCORPORATED
    Inventors: Gang Zhang, Abhishek Jajoo, Yiping Han
  • Publication number: 20090179674
    Abstract: A phase-combining circuit for combining cyclic timing waveforms that have been phase-controlled by control signals based on three or more input signals of different phases, has a weight signal generating circuit and a weighting circuit. The weight signal generating circuit generates weights according to the control signals, and the weighting circuit gives the weights to the respective input signals, with a positive or negative polarity for each one signal.
    Type: Application
    Filed: February 2, 2009
    Publication date: July 16, 2009
    Applicant: FUJITSU LIMITED
    Inventors: Hirotaka Tamura, Masaya Kibune