Abstract: Technical solutions are described for a motor control system, such as one used in a steering system, the motor control system including multiple controllers. In an example, the motor control system includes a first arbitration module associated with a first controller, and a second arbitration module associated with a second controller. The first arbitration module generates a first arbitrated input signal based on a first input signal directed to the first controller, and a second input signal directed to the second controller. The second arbitration module generates a second arbitrated input signal based on the first input signal and the second input signal. The first controller generates a first control output using the first arbitrated input signal, and the second controller generates a second control output using the second arbitrated input signal.

Abstract: An analog-to-digital converter includes a digital-to-analog (DA) converting part having a predetermined number of gradation converting stages and configured to cause each of the predetermined number of gradation converting stages to convert a digital signal to an analog signal and output the converted analog signal, a main-comparator configured to output a binary signal on the basis of a first comparison result between the analog signal output from the DA converting part and a predetermined reference level, and a second sub-comparator having an offset less than a quantization unit with respect to the main-comparator and being configured to output a binary signal on the basis of a second comparison result between the analog signal output from the DA converting part and the predetermined reference level.

Abstract: A single slope AD converter circuit includes a comparator that compares a ramp voltage varying with a predetermined slope as time elapses with an analog input voltage, a counter that counts a predetermined clock in parallel with the comparing process of the comparator, and a controller that outputs a clock count value corresponding to elapsed time when the ramp voltage is smaller than the analog input voltage, as an AD converted first digital value. The comparator compares the ramp voltage with a predetermined first reference voltage, the counter counts the clock in parallel with the comparing process, and the controller outputs the clock count value corresponding to the elapsed time as an AD converted second digital value.

Abstract: The discrete time analog circuit (100) is provided with: a rotate capacitor circuit (150); an amplifier (141) that is connected to the input line or the output line of the rotate capacitor (150), and amplifies the input potential or input charge; a coefficient circuit (140) that is positioned in series with the amplifier (141), and has two history capacitors (143-1, 143-2) positioned parallel to each other; a first active capacitor among the two history capacitors (143-1, 143-2) that is connected to and charges the amplifier (141); and a clock generation circuit (110) that is connected to the input line or the output line without the involvement of the amplifier (141), and that sequentially changes the pairing of the rotate capacitor circuit (150) a second active capacitor, which shares a charge with the rotate capacitor circuit (150).

Abstract: Circuits and methods that improve the performance of electronic sampling systems are provided. Impedances associated with sampling semiconductor switches are maintained substantially constant during sample states, at least in part, by compensating for encountered input signal variations in order to reduce or minimize signal distortion associated with sampled signals that pass through the sampling switch.

Abstract: The invention provides an apparatus and a method for performing a calculation operation with at least one input signal consisting of signal sections, wherein each signal section of said input signal has a constant amplitude. The apparatus comprises a signal transformation unit for transforming at least one input signal into a first intermediary signal having a virtual amplitude with respect to at least one carrier signal. The calculation unit is provided for performing the calculation operation on said first intermediary signal to generate a second intermediary signal. A signal re-transformation unit re-transforms the second intermediary signal into an output signal consisting of signal sections, wherein each signal section of said output signal has a constant amplitude.

Abstract: System and method for converting an analog voltage to a digital signal. The system includes an input voltage sampler, a ramp generator, a comparator, a time-to-digital converter (TDC), and a multiphase oscillator, preferably a rotary traveling wave oscillator, that provides the critical system timing. The phases of the multiphase oscillator define a sampling interval during which the input voltage is sampled and held and a conversion interval during which the ramp generator, comparator, and TDC operate to convert the sampled voltage to the digital signal. The TDC samples at times provided by the phases of the multiphase oscillator to form the bits of the digital signal. The sampler, ramp generator, and comparator can be constructed from multiple fragments, one of which is selectable for calibration while the rest of the fragments are joined for normal operation. Multiple converters can be interleaved to increase the sampling rate.

Abstract: Provided is an apparatus and method to convert an analog signal into a digital signal, more particularly, an apparatus and method for converting an analog signal into a digital signal, the apparatus and method to perform a sampling operation by taking an average value of an analog signal for a predetermined sample period as a sample value and converting the analog signal into a digital signal using the sample value. The apparatus includes a signal input unit to which an analog signal is input; a sampling unit to perform a sampling operation by taking an average value of the analog signal for a predetermined sample period as a sample value; and a signal conversion unit to convert the analog signal into a digital signal using the sample value.

Abstract: A sample rate conversion is accomplished by presenting to a numerically controlled oscillator (NCO) register a clock input at the desired output rate; first-modifying the NCO register contents responsive to a first factor; determining when the first modified NCO register contents are in a predetermined range and in response to the first modified NCO register contents not being in the predetermined range, presenting the first modified NCO register contents to the input of the NCO register; second-modifying, responsive to a second factor, the first modified NCO register contents when the first modified NCO register contents are within the predetermined range and presenting it to the input of the NCO register; and fetching samples, in response to the first-modified NCO register contents being in the predetermined range and interpolating them to produce a resultant sample value at the output rate, and in response to the contents not being in the predetermined range to interpolate the previous sample to produce a

Abstract: A system and method (400) for producing a reference signal is provided. The method includes supplying (405) a first current to a diode, sampling (410) a first voltage across the diode, supplying (405) a second current to the diode, sampling (410) a second voltage across the diode, converting (415) the first voltage and the second voltage to a first digital value and a second digital value, and determining (420) a digital reference value from the first digital value and the second digital value. The first voltage is based on the first current, and the second voltage is based on the second current.

Abstract: A switched-capacitor sample/hold circuit includes a switched-capacitor input sampling stage and a sample/hold amplifier circuit including an operational amplifier having first and second inputs coupled to first and second input sampling capacitors, respectively, and first and second feedback capacitors coupled between the first and second inputs and first and second outputs of the operational amplifier. A continuous-time offset DAC receives a digital input signal representative of an offset voltage produces first and second offset correction voltages. The first and second offset correction voltages are coupled to the switched-capacitor sample/hold circuit to adjust the amount of pre-charging of the first and second feedback capacitors, respectively, in accordance with the value of the digital input signal to compensate an offset component associated with the and second input voltages. The output of the switched-capacitor sample/hold circuit can be connected to an ADC.

Abstract: A system and method for processing sample data employing hardware, such as a Field Programmable Gate Array (FPGA), to process the sample data in small pipelined steps. The processing includes a circular buffer where the read and write of data is synchronous, preventing buffer overrun or data loss. This pipeline processing approach allows increasing data acquisition channels or additional processing steps without limiting processing speed.

Abstract: An input stage includes a plurality of arrays of autozero amplifiers arranged in series in each array, wherein each autozero amplifier receives an output of a preceding autozero amplifier, wherein a first autozero amplifier in each array amplifiers receives an input signal and a corresponding reference voltage at its inputs, and wherein at least one of the autozero amplifiers includes a circuit that receives the signal corresponding to the output signal, the circuit substantially passing the signal corresponding to the output signal and the reference voltages to the amplifiers during the clock phase ?2 and substantially rejecting the signal corresponding to the output signal during the clock phase ?1.

Abstract: An analog signal input circuit having sample-hold circuit that is constituted by a switched capacitor amplifier for which the gain is controlled according to the capacitance ratio of the plurality of capacitors connected with a switch group, for which the opening and closing is controlled according to the amplification rate setting command. The clamping voltage of a clamping circuit included in the analog signal input circuit is established in compliance with an amplification rate setting command.

Abstract: The demand on very high resolution A/D converter can be eliminated by using the invented floating-point A/D converter when the resolution is merely used for covering the signal dynamic range rather than the quantization accuracy. This can be achieved by producing m amplified analog signals with amplifications 2(i−1)k where k=constant and i=1, 2, . . . m. The largest linearly amplified signal will be selected by a logic circuit (after sampling) and converted into an n-bit digital data code by an A/D converter. In the same time, the logic circuit produces an m-bit logic flag code. The n-bit data code (u), the m-bit logic flag code (v) and the constant k are combined to form a final digital output uvk with n+(m−1)k bits. In this way, the resolution and dynamic range can be designed independently. Unlike the know logarithmic amplifier solution, the floating-point A/D converter give a linear digital code output directly without using any look-up table.

Abstract: A data line driver circuit having application in active matrix displays, such as thin-film transistor liquid crystal displays, uses charge metering techniques to achieve high precision and analog pipelining. Pipelining permits both the digital-analog conversion function and the presentation of the analog output to the display data line each to occupy most of the display's line time. The requirement of liquid crystals for periodic inversion of the net applied voltage is accommodated either by the circuits alone or with the display common electrode driven by a square wave.

Abstract: One of analog input voltages applied to a plurality of analog input terminals is selected by means of analog switches connected to the respective analog input terminals and supplied to a common terminal. In this case, each of the analog switches permits selective supply of the potential of a corresponding one of the plurality of analog input terminals in response to a control signal supplied from a controller. The common terminal is connected to the positive input terminal of a comparator. The comparator compares the voltage with a digital output value from the controller which is converted into an analog voltage by means of a D/A converter. Further, the controller generates a preset control signal in an inhibition period during which supply of a voltage from the plurality of analog input terminals to the common terminal is inhibited.

Abstract: A power steering control unit for use with an electric motor assisted vehicle power steering system. The control unit includes two microprocessor controllers that monitor vehicle speed and a torque applied through a vehicle steering column in calculating a duty cycle for the assist motor. The response to the speeed and torque inputs can be adjusted by setting a group of four control switches on the vehicle dashboard. Each microprocessor not only calculates an optimum motor energization but also monitors motor performance. In the event this performance deviates from an expected range the assist is removed and in some cases corrective steps taken to correct the unit's performance. An electrically erasable read only memory coupled to the microprocessors stores constants needed in calculating an energization sequence. The EEROM also stores indicators of the control unit performance to aid in diagnosing difficulties.

Abstract: A microwave signal receiving apparatus comprises a delay line for distributing a microwave signal, samplers for sampling the signal spatially along the delay line and producing analog samples, analog-to-digital converters for converting the analog samples to digital samples, and digital memories associated with each converter for storing the digital samples.

Abstract: A method and apparatus of converting analog voltage signals to digital frequency signals comprises a voltage to frequency converter having an output which produces pulse trains that are proportional to the voltage level of an analog voltage signal applied to the converter. A microprocessor is connected to the converter for sampling the pulse trains during a fixed sampling period. The microprocessor detects the leading edges of the first and last pulse in the pulse train, stores the occurrence time for the two leading edges and then subtracts the occurrence times to calculate the duration time for all the pulses in the sample period between the leading edges of the first and last pulses. A counter counts the number of pulses between the first and last pulse, and a calculation is made dividing the number of pulses by the time duration to yield an accurate measurement of the frequency for the pulse train.

Abstract: An image sensor system using offset analog to digital converters. The analog to digital converters require a plurality of clock cycles to carry out the actual conversion. These conversions are offset in time from one another, so that at each clock cycle, new data is available. Systems are disclosed in which an image sensor converts an analog signal into a digital signal using a pipelined analog to digital converter.