Abstract: A bio-field effect transistor (bioFET) system includes a bioFET configured to receive to a first voltage signal and output a current signal, where the current signal varies exponentially with respect to the first voltage signal. A logarithmic current-to-time converter is connected to the bioFET and is configured to receive the current signal and convert the current signal to a time domain signal. The time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.

Abstract: A device for generating training data sets for signal type recognition has at least one radio frequency signal generator for generating at least one artificial radio frequency signal, a radio frequency receiver connected to the at least one radio frequency signal generator for receiving the at least one artificial radio frequency signal generated by the at least one radio frequency signal generator, and a signal data recorder connected to the radio frequency receiver for storing the radio frequency signal received by the radio frequency receiver as a training data set. Further, a method for generating training data sets as well as a training data set are provided.

Abstract: A measurement apparatus comprising a first terminal to receive an input signal of a circuit under test; a second terminal to receive an output signal of the circuit under test. A first and second phase splitter configured to generate a first and second phase signal, I1 and I2, and a first and second quadrature signal, Q1 and Q2. A first and second multiplexer, each coupled to the first terminal and the second terminal and configured to alternately pass the input and output signals of the circuit under test to the inputs of the first and second phase splitters. A double-quadrature mixer having four inputs configured to receive I1, Q1, I2, and Q2, and an output. A calculation unit to determine one or both of a phase shift of the circuit under test and/or a gain of the circuit under test based on the output of the double-quadrature mixer.

Abstract: A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into a plurality of first digital codes, in which a first converter circuitry in the converter circuitries is configured to perform a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate control signals, and determines whether to set the second digital code to be a second corresponding digital code in predetermined digital codes according to the control signals.

Abstract: Provided are a gate driver circuit used in a display device and a method for driving the same. Charge sharing is adaptively achieved according to the phase of a clock signal outputted by the output ends of buffers in the gate driver circuit, so that power consumed when a gate line is driven can be reduced.

Abstract: The present disclosure relates to a display device, a touch panel and a manufacturing method thereof. The touch panel includes a substrate and a touch layer. The touch layer is disposed on a side of the substrate, and includes a first touch area and a border area surrounding the first touch area. The border area includes at least one second touch area, the second touch area includes a plurality of button portions. The button portions include at least one mutual-capacitance button portion, and the mutual-capacitance button portion includes a first touch electrode, a second touch electrode, and a dummy electrode disposed in a same layer, and there is a gap between the first touch electrode and the second touch electrode. The dummy electrode is disposed in the gap between the first touch electrode and the second touch electrode, and separated from the first touch electrode and the second touch electrode.

Abstract: The flicker performance manager disclosed herein implements a method including measuring a liquid crystal (LC) common voltage (VCOM) over a predetermined period of operation an LCD panel having a plurality of LCs, determining a shift in the VCOM (VCOM shift) over the predetermined period based at least in part on the measured VCO, storing the VCOM shift as a function of time in a table of an embedded controller, receiving a power-on signal for the LCD panel and adjusting a VCOM reference level applied to the LCs based at least in part on the stored values of the VCOM shift.

Abstract: The disclosure relates to accurately determining a DC energy signal, such as a DC current or DC voltage, which may be particularly useful when controlling a formation/testing current of a battery cell during formation and/or testing. In the battery formation/testing context, a current sensor is used to measure the current of the battery cell, which is used as a feedback signal for controlling the current to achieve a target current. The transfer function of the current sensor is used to improve the accuracy of the current measurement. Because the transfer function can be regularly determined during formation/testing, a lower-cost current sensor with relatively poor temperature coefficient may be used. Any change in the gain of the current sensor may be detected by the transfer function determination and corrected for. Therefore, high current control accuracy may be achieved at lower cost.

Abstract: According to the one embodiment, a semiconductor circuit includes: an analog-to-digital conversion circuit including a first analog-to-digital converter configured to sample at least one first sampling signal regarding an input signal based on a first clock, and a second analog-to-digital converter configured to sample at least one second sampling signal regarding the input signal based on a second clock shifted from the first clock by a first time; and a first calibration circuit configured to calibrate at least one timing of the first clock and the second clock based on a calculation result of a moving average of the first sampling signal and the second sampling signal.

Abstract: A conversion circuit that performs analog-to-digital conversion is described. During operation, the conversion circuit receives an input signal. Then, the conversion circuit performs analog-to-digital conversion and provides a quantized output corresponding to the input signal based at least in part on a first power-supply voltage and a second power-supply voltage of the conversion circuit. For example, the quantized output may be based at least in part on a comparison of the input signal to the first power-supply voltage and the second power-supply voltage. Moreover, the first power-supply voltage and the second power-supply voltage may specify a full-scale range of the conversion circuit. When the full-scale range exceeds a second full-scale range associated with reference voltages that are other than the first power-supply voltage and the second power-supply voltage, the quantized output may correspond to a larger number of bits than when the full-scale range equals the second full-scale range.

Abstract: Example implementations include a method of obtaining an input voltage of a power converter circuit and a system voltage of the power converter circuit, obtaining a voltage rate gain based on an aggregate inductance of the power converter circuit, and in accordance with a determination that the input voltage and the system voltage are not equal, generating a rate offset voltage based on the voltage rate gain and the system voltage difference.

Abstract: A bio-field effect transistor (bioFET) system includes a bioFET configured to receive a first voltage signal and output a current signal. A logarithmic current-to-time converter is connected to the bioFET and is configured to receive the current signal and convert the current signal to a time domain signal. The time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.

Abstract: A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.

Abstract: A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

Abstract: Aspects of the technology described herein relate to apparatuses and methods for performing elevational beamforming of ultrasound data. Elevational beamforming may be implemented by different types of control circuitry. Certain control circuitry may be configured to control memory such that ultrasound data from different elevational channels is summed with stored ultrasound data in the memory that was collected at different times. Certain control circuitry may be configured to control a decimator to decimate ultrasound data from different elevational channels with different phases. Certain control circuitry may be configured to control direct digital synthesis circuitry to add a different phase offset to complex signals generated by the DDS circuitry for multiplying with ultrasound data from different elevational channels.

Abstract: Analog-to-digital converters (ADCs) with a high sampling rate and larger spurious-free dynamic range (SFDR) in the spectral domain are used in many applications, including, but not limited to, range finders, meteorology, spectroscopy, and/or coherent medical imaging. Circuit techniques for time-interleaving a set of low-sampling-rate sub-ADCs into a higher sampling-rate ADC with a larger SFDR than existing approaches are described. In one embodiment, the circuit techniques add a small number of additional units or sub-ADCs. This change in architecture enables a dynamic-selection procedure to time-interleave the set of sub-ADCs in such a way that mismatch-related non-idealities of the constituent sub-ADCs are spread in the frequency domain into a noise-like spectral shape in order to prevent the creation of spurious tones, which would otherwise deleteriously impact the SFDR.

Abstract: An analog-to-digital conversion (ADC) system is operated with a duty cycle. During the ON period, the ADC circuits perform analog-to-digital conversions of an analog input signal. During the Standby period, the ADC system is in either a standby state or a foreground calibration state. The ADC system operates in a reduced-power mode in the standby state. In the foreground calibration state, the ADC system performs a portion of a foreground calibration cycle during a calibration time slot. The foreground calibration cycle is performed over multiple calibration time slots. The foreground calibration cycle and the calibration time slots are configurable by changing the values of control registers that represent calibration parameters.

Abstract: The present description relates to a comparator (2) comprising a ring of gates (110A, 110B, 110A?, 110B?, 106, 108) in series, wherein: each gate implements an inverting function between a first input (100) and an output (102) of the gate; at least one (110A?, 110B?) gate is controllable and is associated with another gate; each controllable gate (110A?, 110B?) comprises a control input (116) coupled with the output (102) of said associated gate, and prevents switching of its output (102) to a high state if its control input (116) is in the high state, and to a low state otherwise; and the control input (116) of each controllable gate (110A?, 110B?) receives the output (102) of said associated gate if an even number of gates separates these two gates, and receives the complement of said output if not.

Abstract: A signal control device includes a charge/discharge circuit, a sampling capacitor, and an AC conversion circuit. The charge/discharge circuit is capable of charging or discharging the sampling capacitor. The AC conversion circuit performs an AD conversion by converting an analog voltage value charged in the sampling capacitor into an AD conversion value that is a digital value. After a charge operation or a discharge operation to the sampling capacitor with the charge/discharge circuit, the AD conversion circuit performs the AD conversion, and a malfunction of the charge/discharge circuit is determined based on a diagnosis result of the AD conversion value.

Abstract: A multipath sampling circuit includes an input line electrically having an input voltage, a plurality of voltage amplifiers in parallel electrically with one another, each voltage amplifier having a respective input electrically coupled in series with the input line, each voltage amplifier having a different gain and a different saturation voltage; and a plurality of track-and-hold circuits. The track-and-hold circuits have a first state in which a respective input of each track-and-hold circuit is electrically coupled to an output of a respective amplifier. The track-and-hold circuits have a second state in which the respective input of each track-and-hold circuit is electrically decoupled from the output of the respective amplifier. The track-and-hold circuits can be electrically coupled to a summing circuit, a buffer amplifier, or an operational amplifier.

Abstract: An apparatus is disclosed for measuring the resistance of a shape memory alloy, SMA, wire. The apparatus comprises: an SMA wire; a sense resistor connected in series with the SMA wire; a measurement circuit configured to perform a measurement indicative of the potential difference across at least the SMA wire; and a measurement switch between the SMA wire and the sense resistor. The measurement switch is configured to connect either to the measurement circuit such that the measurement circuit can perform the measurement or to a circuit that bypasses the sense resistor.

Abstract: Input circuitry for an analog-to-digital converter (ADC) is provided. The input circuitry includes a calibration signal source configured to output a calibration signal for the ADC and an analog circuitry configured to receive and process an analog input signal for the ADC. The analog circuitry is further configured to generate a combined signal by combining the analog input signal and the calibration signal. The input circuitry further includes a buffer amplifier coupled to the analog circuitry and configured to supply a buffered signal to the ADC based on the combined signal. Further, the input circuitry includes neutralization circuitry configured to generate, based on the calibration signal, a neutralization signal for mitigating an unwanted signal component related to a limited reverse isolation of the analog circuitry. The neutralization circuitry is further configured to supply the neutralization signal to at least one of an input node and an intermediate node of the analog circuitry.

Abstract: A nontransitory computer-readable program storage medium storing program instructions. The program, when executed by a processor, has the processor capable of receiving a set of input data, the input data relating to devices on a test board for testing a device under test. The program, when executed by a processor, also is capable of transforming the set of input data into test board mapping data. The test board mapping data comprises an ordered listing of potential test points along a path that couples to a conductive surface, wherein the potential test points are derived from at least one of the test board attributes. Further, the program, when executed by a processor, is capable of identifying a selected test point from among the one or more potential test points, the selected test point for spike check probing of the device under test.

Abstract: A method of beamforming is provided. A single non-linear equalization (NLEQ) coefficient set is generated in beamspace, the single NLEQ coefficient set configured to characterize non-linear behavior of a system having an array of N elements. M parallel digital signals are received, for transmission by N channels, respectively, the N channels corresponding to the N elements. Each of the M respective parallel digital signals are equalized, using an NLEQ filter based on the single NLEQ coefficient set, wherein the single NLEQ coefficient set is used for each of the N elements and wherein the equalizing is configured to generate a set of M linearized parallel digital signals. Using a single summer, the M linearized parallel digital signals are summed, to produce one or more beamspace channelized output signals.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input voltage signal. A first ADC stage is coupled to the input terminal and is configured to output a first digital value corresponding to the analog input voltage signal and a first analog residue signal corresponding to a difference between the first digital value and the analog input signal. An inverter based residue amplifier is configured to receive the first analog residue signal, amplify the first analog residue signal, and output an amplified residue signal. The amplified residue signal is converted to a second digital value, and the first and second digital values are combined to create a digital output signal corresponding to the analog input voltage signal.

Abstract: A digital-to-analog converter includes an array of capacitors, an array of capacitor switches, positive and negative high-bandwidth reference buffers, positive and negative low-bandwidth reference buffers, and a reference-voltage-selection switch. Each capacitor switch electrically couples a respective capacitor to either a positive or a negative reference voltage line. The reference-voltage-selection switch electrically couples the positive and negative reference voltage lines to either positive and negative high-bandwidth voltages or to positive and negative low-bandwidth voltages. The positive and negative high-bandwidth voltages are produced by the positive and negative high-bandwidth reference buffers. The positive and negative low-bandwidth voltages are produced by the positive and negative low-bandwidth reference buffers.

Abstract: A current cancellation circuit, a heart rate detection device and a wearable device. The current cancellation circuit includes: a current-voltage conversion circuit and a SAR ADC, where the SAR ADC includes a DAC, an SAR logic circuit and a comparator; the current-voltage conversion circuit is configured to receive an analog current output by the DAC and an interference current output by a photoelectric sensor, calculate a difference between the analog current and the interference current, and output an analog voltage; the comparator is configured to receive the analog voltage output by the current-voltage conversion circuit, and output a comparison result according to the analog voltage; and the DAC is configured to output the analog current according to a digital signal corresponding to the comparison result that is output by the SAR logic circuit, and the analog current is used to cancel the interference current output by the photoelectric sensor.

Abstract: The present disclosure relates to an electronic device. An analog-digital converter includes an input voltage provider configured to output the input voltage during a plurality of stages, a comparator configured to output a comparison result between the input voltage and one of a plurality of comparison reference voltages, a successive approximation register configured to output at least one bit among the plurality of bits of digital data based on the comparison result, and a digital-analog converter configured to provide the comparator with one comparison reference voltage among the plurality of the comparison reference voltages based on the at least one bit, wherein the digital-analog converter includes a plurality of transistors that are coupled in parallel with each other, the digital-analog converter configured to selectively receive a plurality of reference voltages to generate the one comparison reference voltage.

Abstract: A photoelectric conversion device includes pixels forming columns, an amplifier, signal holding capacitors, switches, and a control unit. The pixels forming columns are configured to amplify, at multiple gains, a signal based on charge generated by a photoelectric converter of the pixel. The signal holding capacitors are provided in association with the columns. The switches control sample-and-hold operations to the signal holding capacitors on corresponding columns. The control unit supplies a control signal that controls the switches. The control unit supplies the control signal whose settling time when the switches transition from an on-state to an off-state is a first length and a second length when the signal amplified at a first gain and a second gain, respectively, is held in the signal holding capacitor. The second gain is higher than the first gain.

Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

Abstract: A system of providing power including: a preceding-stage power supply module, a post-stage power supply module and a load, connected in sequence; a projection on the mainboard of a smallest envelope area formed by contour lines of the preceding-stage power supply module and the load at least partially overlaps with a projection of the post-stage power supply module; the preceding-stage power supply module includes a plurality of sets of preceding-stage output pins and preceding-stage ground pins alternately arranged to form a first rectangular envelope area, and the load is disposed on a side of a long side of the first rectangular envelope area; and the load comprises a load input pin and a load ground pin forming a second rectangular envelope area, and a center line of the first rectangular envelope area and the second rectangular envelope area is perpendicular to the long side of the first rectangular envelope area.

Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.

Abstract: A first successive approximation register analog-to-digital converter according an embodiment of the present disclosure includes an N-bit (N represents an integer greater than or equal to 5) capacitive digital-to-analog converter including a plurality of capacitive elements. A plurality of first capacitive elements of the plurality of capacitive elements is capacitive elements that have total capacity corresponding to total capacity of a plurality of the capacitive elements corresponding to a whole or a portion of first to (N?1)-th bits, and do not correspond to the first to (N?1)-th bits.

Abstract: Devices, systems, and methods that can facilitate in situ probing of a discrete time circuit components are provided. According to an embodiment, a device can comprise a hold circuit that can generate a sampled signal at a holding stage. The device can further comprise an in situ probe device that can be coupled to the hold circuit that can measure one or more operating voltage values at the holding stage based on the sampled signal.

Abstract: An example residue generation arrangement for a continuous time or hybrid ADC includes a delay circuit having a cascade of analog delay sections, each section to provide a respective delay to an analog input signal, thus providing a delayed analog input signal at the output of the delay circuit. The delay circuit further includes a selector, configured to select an input or an output of one of the delay sections to provide as an input signal to a quantizer of a feedforward path. The quantizer may generate a digital input to a DAC of the feedforward path based on the output of the selector, and the DAC may generate a feedforward path analog output based on the digital signal generated by the quantizer. The arrangement further includes a summation node, configured to generate a residue signal based on the delayed analog input and the feedforward path analog output.

Abstract: A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.

Abstract: A signal processing circuit including a plurality of analog-to-digital conversion circuits, an in-memory computing device, and a control method thereof are provided. Each analog-to-digital conversion circuit includes a reset switch, a capacitor array circuit, a voltage comparator, and a successive approximation circuit. A first terminal of the reset switch receives a first reference voltage, and a second terminal of the reset switch receives an input voltage signal. The capacitor array circuit adjusts the input voltage signal according to a successive approximation control signal to generate an adjusted voltage. The voltage comparator compares the voltage levels of the adjusted voltage and a second reference voltage to generate a comparison signal. The successive approximation circuit generates a successive approximation control signal according to the comparison signal and generates an output digital signal corresponding to the input voltage signal.

Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM; and a second input port for receiving a control signal, wherein the control signal dynamically adjusts an output frequency band of the DSM.

Abstract: A sensor device includes an oscillator element that is suppliable with a trigger signal, an activation and deactivation of at least one sensor element of the sensor device being initiatable with the aid of the trigger signal and an activation element, and at least one piece of sensor data of the at least one sensor element being storable in a register after the at least one sensor element is activated; and an interface connected to the register and via which the piece of sensor data is transmittable to the control device.

Abstract: A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.

Abstract: A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed.

Abstract: Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.

Abstract: An integrator circuit (10) for use in a sigma-delta modulator (1) comprises a differential operational amplifier (130) with a first input node (E130a) and a second input node (E130b). The first input node (E130a) of the differential operational amplifier (130) is connected to a first current path (101) and the second input node (E130b) of the differential operational amplifier (130) is connected to a second current path (102). A first controllable switch (111) is arranged between the second input node (E130b) of the differential operational amplifier (130) and the first current path (101). A second controllable switch (112) is arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102). A third controllable switch (113) is arranged between a reference potential (RP) and the first current path (101). A fourth controllable switch (114) is arranged between the reference potential (RP) and the second current path (102).

Abstract: A circuit includes a voltage-to-time conversion element configured to receive an input voltage at an input and to generate a time domain representation of the input voltage. The voltage-to-time conversion element includes an amplifier having an amplifier input coupled to the input, a zero crossing detector coupled to an output of the amplifier, and a current source selectively coupled to the amplifier input by way of a switching element.

Abstract: A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADCs, an open-loop clocking circuit, and a time-multiplexing circuit. The plurality of ADCs receive an analog input signal. Each ADC is configured to sample the analog input signal upon receipt of a respective clock signal. The open-loop clocking circuit receives a main clock signal having a reference frequency, and then divides the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal starting from the main clock signal. The open-loop clocking circuit then distributes the plurality of respective clock signals to the plurality of ADCs. The time-multiplexing circuit is coupled to the plurality of ADCs and is configured to combine respective digital output signals from the plurality of ADCs into a time series.

Abstract: A dynamic differential amplifier includes: gain transistors to drive with differential input voltage levels; sample capacitors having first terminals to ramp from an initial voltage level to differential amplified voltage levels of the input voltage levels in response to the driven gain transistors; and adjustment circuits to adjust the amplified voltage levels in the direction of the initial voltage level by an offset voltage level. In some cases, second terminals of the sample capacitors are a common-mode node to maintain a common-mode voltage level midway between the ramping voltage levels of the first terminals. In some cases, the dynamic differential amplifier further includes a comparison circuit to compare the maintained common-mode voltage level to a threshold voltage level, wherein the first terminals of the sample capacitors stop ramping and the adjustment circuits adjust the amplified voltage levels in response to the compared common-mode voltage level reaching the threshold voltage level.

Abstract: A voltage-mode digital-to-analog converter (DAC) includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).

Abstract: An analog-to-digital converter includes a sampling capacitor connected to a multiplexer output, discharge circuitry discharging the sampling capacitor during a first period beginning at a start of a sampling cycle, and level shifting circuitry charging the sampling capacitor to a voltage at a first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period beginning at expiration of the first period. A first switch connects the first analog input node to the output node to charge the sampling capacitor to the voltage at the first analog input node, at expiration of the second period, and disconnects the first analog input node from the output node at an end of the sampling cycle of the analog-to-digital converter.

Abstract: A system includes analog-to-digital converter (ADC) logic, wherein the ADC logic includes a stage with a dynamic comparator circuit. The ADC logic also includes a residue stage. The dynamic comparator circuit includes a preamplifier and a common mode clamp circuit for the preamplifier.

Abstract: An apparatus for determining one or more calibration values of an ADC is configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal including the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal including the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal. The apparatus is configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.