Sample And Hold Patents (Class 341/122)
  • Patent number: 11310456
    Abstract: A photoelectric conversion device includes pixels forming columns, an amplifier, signal holding capacitors, switches, and a control unit. The pixels forming columns are configured to amplify, at multiple gains, a signal based on charge generated by a photoelectric converter of the pixel. The signal holding capacitors are provided in association with the columns. The switches control sample-and-hold operations to the signal holding capacitors on corresponding columns. The control unit supplies a control signal that controls the switches. The control unit supplies the control signal whose settling time when the switches transition from an on-state to an off-state is a first length and a second length when the signal amplified at a first gain and a second gain, respectively, is held in the signal holding capacitor. The second gain is higher than the first gain.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: April 19, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Yasuhiro Oguro, Takanori Yamashita, Tomoya Kumagai
  • Patent number: 11303292
    Abstract: An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current steering DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 12, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Martin Kinyua, Eric Soenen
  • Patent number: 11277912
    Abstract: A system of providing power including: a preceding-stage power supply module, a post-stage power supply module and a load, connected in sequence; a projection on the mainboard of a smallest envelope area formed by contour lines of the preceding-stage power supply module and the load at least partially overlaps with a projection of the post-stage power supply module; the preceding-stage power supply module includes a plurality of sets of preceding-stage output pins and preceding-stage ground pins alternately arranged to form a first rectangular envelope area, and the load is disposed on a side of a long side of the first rectangular envelope area; and the load comprises a load input pin and a load ground pin forming a second rectangular envelope area, and a center line of the first rectangular envelope area and the second rectangular envelope area is perpendicular to the long side of the first rectangular envelope area.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: March 15, 2022
    Assignee: Delta Electronics (Shanghai) CO., LTD
    Inventors: Shouyu Hong, Zhiheng Fu, Haoyi Ye, Qingdong Chen, Yiqing Ye, Jinping Zhou, Xiaoni Xin, Pengkai Ji, Min Zhou
  • Patent number: 11239855
    Abstract: A capacitor-based digital-to-analog-converter produces a level-shifted analog outputs by precharging respective sets of output-generating capacitors to different applied potentials and then floating a common output of the sets of capacitors such that charge is redistributed among the capacitors through the common output to yield, across all the capacitors, a uniform precharge voltage that falls between the different applied potentials.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: February 1, 2022
    Assignee: Rambus Inc.
    Inventor: Shankar Tangirala
  • Patent number: 11206038
    Abstract: A first successive approximation register analog-to-digital converter according an embodiment of the present disclosure includes an N-bit (N represents an integer greater than or equal to 5) capacitive digital-to-analog converter including a plurality of capacitive elements. A plurality of first capacitive elements of the plurality of capacitive elements is capacitive elements that have total capacity corresponding to total capacity of a plurality of the capacitive elements corresponding to a whole or a portion of first to (N?1)-th bits, and do not correspond to the first to (N?1)-th bits.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 21, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Shinichirou Etou
  • Patent number: 11156644
    Abstract: Devices, systems, and methods that can facilitate in situ probing of a discrete time circuit components are provided. According to an embodiment, a device can comprise a hold circuit that can generate a sampled signal at a holding stage. The device can further comprise an in situ probe device that can be coupled to the hold circuit that can measure one or more operating voltage values at the holding stage based on the sampled signal.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: October 26, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Martin Cochet, Troy James Beukema
  • Patent number: 11133814
    Abstract: An example residue generation arrangement for a continuous time or hybrid ADC includes a delay circuit having a cascade of analog delay sections, each section to provide a respective delay to an analog input signal, thus providing a delayed analog input signal at the output of the delay circuit. The delay circuit further includes a selector, configured to select an input or an output of one of the delay sections to provide as an input signal to a quantizer of a feedforward path. The quantizer may generate a digital input to a DAC of the feedforward path based on the output of the selector, and the DAC may generate a feedforward path analog output based on the digital signal generated by the quantizer. The arrangement further includes a summation node, configured to generate a residue signal based on the delayed analog input and the feedforward path analog output.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: September 28, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Sharvil Pradeep Patil, Kimo Tam, Hajime Shibata
  • Patent number: 11018682
    Abstract: A sub-ranging analog-to-digital converter (ADC) includes a coarse ADC and a fine ADC that receives a set of coarse signals from the coarse ADC. The fine ADC includes multiple digital-to-analog converters (DACs) and multiple converters such that a number of converters is less than a number of DACs. The DACs and the converters function in a partial time-interleaved manner where each DAC receives an analog input signal in different non-overlapping durations of a clock signal and generates a corresponding analog output signal. At least one of the converters is coupled with at least two DACs, and each converter is configured to receive the corresponding analog output signals and perform conversion operation to generate digital signals in non-overlapping durations of the clock signal, respectively. The durations for performing conversion operation of at least two of the converters overlap partially.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: May 25, 2021
    Assignee: NXP B.V.
    Inventors: Sushil Kumar Gupta, Pankaj Agrawal, Ashish Panpalia
  • Patent number: 10979065
    Abstract: A signal processing circuit including a plurality of analog-to-digital conversion circuits, an in-memory computing device, and a control method thereof are provided. Each analog-to-digital conversion circuit includes a reset switch, a capacitor array circuit, a voltage comparator, and a successive approximation circuit. A first terminal of the reset switch receives a first reference voltage, and a second terminal of the reset switch receives an input voltage signal. The capacitor array circuit adjusts the input voltage signal according to a successive approximation control signal to generate an adjusted voltage. The voltage comparator compares the voltage levels of the adjusted voltage and a second reference voltage to generate a comparison signal. The successive approximation circuit generates a successive approximation control signal according to the comparison signal and generates an output digital signal corresponding to the input voltage signal.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: April 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Ho Chang, Jaw-Juinn Horng, Yung-Chow Peng
  • Patent number: 10965309
    Abstract: A delta-sigma modulator (DSM) with non-recursive computation of delta-sigma residues comprising: an input port for receiving a digital input signal; a residue calculation circuit coupled to the input port for calculating delta-sigma residues non-recursively; a DSM output calculation circuit coupled to the output of the residue calculation circuit for generating an output of the DSM; and a second input port for receiving a control signal, wherein the control signal dynamically adjusts an output frequency band of the DSM.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 30, 2021
    Assignee: Raytheon Company
    Inventor: Brian A. Gunn
  • Patent number: 10955267
    Abstract: A sensor device includes an oscillator element that is suppliable with a trigger signal, an activation and deactivation of at least one sensor element of the sensor device being initiatable with the aid of the trigger signal and an activation element, and at least one piece of sensor data of the at least one sensor element being storable in a register after the at least one sensor element is activated; and an interface connected to the register and via which the piece of sensor data is transmittable to the control device.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: March 23, 2021
    Assignee: Robert Bosch GmbH
    Inventors: Jan Hayek, Dorde Cvejanovic
  • Patent number: 10931122
    Abstract: A pre-charge circuit is provided for pre-charging the input node of a capacitive component to which the multiplexer output is fed to a charge level that is close to or approximates the signal output level of the multiplexer when its output is next switched. In order to reduce the level shifting burden on the amplifier in the pre-charge circuit, each pre-charge circuit input channel has a respective capacitor that is able to be switched in and out of series with the respective multiplexer channels, such that the respective capacitors track the signal levels on the multiplexer channels. The provision of the corresponding capacitors for each MUX channel reduces the input current to the pre-charge amplifier, and allows for the level shifting burden to be taken by the capacitors, leading to more stable and lower power operation.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: February 23, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Christopher Peter Hurrell, Sanjay Rajasekhar
  • Patent number: 10903847
    Abstract: A conventional analog-to-digital conversion circuit has a problem that conversion errors cannot be suppressed.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: January 26, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tetsuo Matsui, Keisaku Sento, Tomohiko Ebata
  • Patent number: 10868564
    Abstract: Various embodiments of the present technology may provide methods and apparatus for a delta-sigma analog-to-digital converter. The delta-sigma ADC may provide a sample-and-hold circuit defined by a first switch, a second switch, a capacitor, and an amplifier, and an integrator defined by the first capacitor, a second capacitor, and the amplifier, wherein the sample-and-hold circuit and the integrator share the first capacitor and the amplifier.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: December 15, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Masayuki Kanematsu
  • Patent number: 10826522
    Abstract: An integrator circuit (10) for use in a sigma-delta modulator (1) comprises a differential operational amplifier (130) with a first input node (E130a) and a second input node (E130b). The first input node (E130a) of the differential operational amplifier (130) is connected to a first current path (101) and the second input node (E130b) of the differential operational amplifier (130) is connected to a second current path (102). A first controllable switch (111) is arranged between the second input node (E130b) of the differential operational amplifier (130) and the first current path (101). A second controllable switch (112) is arranged between the first input node (E130a) of the differential operational amplifier (130) and the second current path (102). A third controllable switch (113) is arranged between a reference potential (RP) and the first current path (101). A fourth controllable switch (114) is arranged between the reference potential (RP) and the second current path (102).
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: November 3, 2020
    Assignee: ams AG
    Inventor: Daisuke Horii
  • Patent number: 10797714
    Abstract: A circuit includes a voltage-to-time conversion element configured to receive an input voltage at an input and to generate a time domain representation of the input voltage. The voltage-to-time conversion element includes an amplifier having an amplifier input coupled to the input, a zero crossing detector coupled to an output of the amplifier, and a current source selectively coupled to the amplifier input by way of a switching element.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Martin Kinyua
  • Patent number: 10790845
    Abstract: A time-interleaved analog-to-digital converter (ADC) includes a plurality of ADCs, an open-loop clocking circuit, and a time-multiplexing circuit. The plurality of ADCs receive an analog input signal. Each ADC is configured to sample the analog input signal upon receipt of a respective clock signal. The open-loop clocking circuit receives a main clock signal having a reference frequency, and then divides the main clock signal into a sequential plurality of respective clock signals, each having a frequency lower than the reference frequency, and each triggered by one other respective clock signal starting from the main clock signal. The open-loop clocking circuit then distributes the plurality of respective clock signals to the plurality of ADCs. The time-multiplexing circuit is coupled to the plurality of ADCs and is configured to combine respective digital output signals from the plurality of ADCs into a time series.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 29, 2020
    Assignee: THE BOEING COMPANY
    Inventors: Alfio Zanchi, Rodney Kevin Bonebright
  • Patent number: 10778155
    Abstract: A dynamic differential amplifier includes: gain transistors to drive with differential input voltage levels; sample capacitors having first terminals to ramp from an initial voltage level to differential amplified voltage levels of the input voltage levels in response to the driven gain transistors; and adjustment circuits to adjust the amplified voltage levels in the direction of the initial voltage level by an offset voltage level. In some cases, second terminals of the sample capacitors are a common-mode node to maintain a common-mode voltage level midway between the ramping voltage levels of the first terminals. In some cases, the dynamic differential amplifier further includes a comparison circuit to compare the maintained common-mode voltage level to a threshold voltage level, wherein the first terminals of the sample capacitors stop ramping and the adjustment circuits adjust the amplified voltage levels in response to the compared common-mode voltage level reaching the threshold voltage level.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: September 15, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Randall M. White
  • Patent number: 10771083
    Abstract: A system includes analog-to-digital converter (ADC) logic, wherein the ADC logic includes a stage with a dynamic comparator circuit. The ADC logic also includes a residue stage. The dynamic comparator circuit includes a preamplifier and a common mode clamp circuit for the preamplifier.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Joseph Palackal Mathew
  • Patent number: 10771077
    Abstract: A voltage-mode digital-to-analog converter (DAC) includes multiple bit processing circuits to generate an output voltage responsive to a binary input. Each of the multiple bit processing circuits includes a first switch circuit and a second switch circuit. The first switch circuit is to selectively couple one of multiple reference voltages to a first output load in response to receiving a first input bit during a first bit time. The first output load has a value proportional to d. The second switch circuit is to selectively couple one of the multiple reference voltages to a second output load in response to receiving a second input bit during a second bit time. The second output load has a value corresponding to the first output load. The first and second output loads are disposed in parallel, and serially couple to a third output load having a value proportional to (1-d).
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: September 8, 2020
    Assignee: Marvell Asia Pte., LTD
    Inventor: Joseph Briaire
  • Patent number: 10771082
    Abstract: An analog-to-digital converter includes a sampling capacitor connected to a multiplexer output, discharge circuitry discharging the sampling capacitor during a first period beginning at a start of a sampling cycle, and level shifting circuitry charging the sampling capacitor to a voltage at a first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period beginning at expiration of the first period. A first switch connects the first analog input node to the output node to charge the sampling capacitor to the voltage at the first analog input node, at expiration of the second period, and disconnects the first analog input node from the output node at an end of the sampling cycle of the analog-to-digital converter.
    Type: Grant
    Filed: September 4, 2019
    Date of Patent: September 8, 2020
    Assignee: STMicroelectronics International N.V.
    Inventors: Rajesh Narwal, Kavindu Shekhar Benjwal
  • Patent number: 10763877
    Abstract: An apparatus for determining one or more calibration values of an ADC is configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal including the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal including the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal. The apparatus is configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 1, 2020
    Assignee: NXP B.V.
    Inventor: Frederic Darthenay
  • Patent number: 10686406
    Abstract: A circuit comprising: a first passive mixer (21) having mixer inputs configured to receive in-phase (I) and quadrature-phase (Q) differential signals; and a first differential sub-circuit (31). The first passive mixer is configured to switch the in-phase (I) and quadrature-phase (Q) differential signals to the first differential sub-circuit at a mixing frequency. The first differential sub-circuit (31) has a pair of differential inputs configured to receive the switched in-phase (I) and quadrature-phase (Q) differential signals from the first passive mixer (21), each input having a capacitance capable of storing a charge that depends on the switched in-phase or quadrature-phase signals. The circuit further comprises a charge canceller configured to supply, to at least one of: the mixer inputs; and the pair of differential inputs, an opposite charge compared with a charge that has been stored on the pair of differential inputs by the operation of the first passive mixer.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: June 16, 2020
    Assignee: u-blox AG
    Inventor: Niall Duncan
  • Patent number: 10686459
    Abstract: A method of incorporating Programmable Gain Amplifier (PGA) function into pipelined ADC for wide input range. The power consumption is saved without adding extra stage to reduce input range. The ADC input range can be adjusted on the fly using resistor bank and capacitor bank to achieve optimal system performance.
    Type: Grant
    Filed: July 8, 2018
    Date of Patent: June 16, 2020
    Assignee: IPGREAT INCORPORATED
    Inventor: Yuan-Ju Chao
  • Patent number: 10665265
    Abstract: Methods and systems are provided for generating an event reel based on spectator reaction data, the event reel is temporally synchronized to a music track. A method includes receiving a video file for video content and receiving spectator reaction data related to reactions generated by spectators while viewing the video content. The method includes processing the spectator reaction data to identify video time slices from the video content that correspond to segments of interest of the video content. The method includes processing a music track to identify markers for the music track that correspond to beats of the music track and generating an event reel having a video component defined by a sequence of the video time slices that is temporally synchronized to the markers of the music track.
    Type: Grant
    Filed: February 2, 2018
    Date of Patent: May 26, 2020
    Assignee: Sony Interactive Entertainment America LLC
    Inventor: Warren Benedetto
  • Patent number: 10615818
    Abstract: A two-step, hybrid analog-to-digital converter (ADC) includes a Delta-Sigma ADC that employs chopping to resolve MSBs, a Nyquist ADC that employs correlated double sampling (CDS) to resolve LSBs, and a combiner that combines the MSBs and the LSBs to generate a digital output signal. The Delta-Sigma ADC has first and second integrators where, after resolving the MSBs, the first integrator is re-configured to function as a reference buffer for the Nyquist ADC and the second integrator is re-configured to function as the Nyquist ADC.
    Type: Grant
    Filed: June 2, 2019
    Date of Patent: April 7, 2020
    Assignee: NXP USA, Inc.
    Inventors: Kamlesh Singh, Vikram Varma
  • Patent number: 10613753
    Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device, which have an improved processing speed for a suspend operation. The semiconductor memory device includes a memory cell array, a peripheral circuit configured to perform a data operation corresponding to an externally provided command on the memory cell array and a control circuit configured to control the peripheral circuit to perform the data operation by sequentially executing instructions corresponding to a plurality of instruction lines of an operation algorithm for the data operation and, when a suspend command is provided during the data operation, to perform a preset suspend operation in any one of a checker mode and an instant mode.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: April 7, 2020
    Assignee: SK hynix Inc.
    Inventor: Tai Kyu Kang
  • Patent number: 10594315
    Abstract: An apparatus to monitor and control a switching rate in a switch includes a differentiator circuit including a capacitor and a configurable resistor. The differentiator circuit further includes an input terminal of the capacitors configured to receive a first voltage from a switch and a differentiator node configured to receive a differentiated voltage based on the first voltage. The apparatus includes a peak detector circuit coupled to the differentiator node and configured to detect a peak value of the differentiated voltage. The apparatus further includes a driver circuit coupled to the peak detector circuit and configured to adjust a control signal to the switch responsive to the detected peak value of the differentiated voltage.
    Type: Grant
    Filed: July 17, 2017
    Date of Patent: March 17, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rajdeep Bondade, Nathan Schemm, Rajarshi Mukhopadhyay
  • Patent number: 10581450
    Abstract: Apparatus and associated methods relating to a digital-to-analog converter (DAC) include a programmable resistance network coupled between a voltage supply node VDD and a switch cell circuit to provide a predetermined resistance in response to the VDD and current IS of the switch cell circuit. In an illustrative example, the DAC may include a switch cell circuit comprising one or more switch cells connected in parallel. Each switch cell may include a differential gain circuit having a first branch coupled to a second branch at an input of a current source. The programmable resistance may include a variable resistance configured to adjust a voltage (Vbias) supplied to the switch cell circuit in response to a control signal. By introducing the programmable resistance network, predetermined bias and/or gain values may be dynamically adjusted with a constant board-level power supply VDD.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 3, 2020
    Assignee: XILINX, INC.
    Inventors: Brendan Farley, Bob W. Verbruggen, Christophe Erdmann, Roberto Pelliconi
  • Patent number: 10529285
    Abstract: An electronic device includes a display panel. The display panel includes a number of pixels, each of which includes a driving thin-film-transistor (TFT) and a light-emitting diode. Compensation circuitry external to the display panel applies offset data to pixel data for each pixel of the plurality of pixels before the pixel data is provided to the plurality of pixels.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: January 7, 2020
    Assignee: Apple Inc.
    Inventors: Mohammad B. Vahid Far, Jesse A. Richmond, Yafei Bi
  • Patent number: 10516411
    Abstract: A differential digital-to-analog (DAC) circuit that can include a reservoir capacitor and various switches to couple the bottom plates of the input capacitors, e.g., bit-trial capacitors, to reference voltages, e.g., REF+ or REF?. In this manner, the reservoir capacitor can be used to provide any differential charge to the input capacitors, e.g., bit-trial capacitors, and the reference voltages, e.g., REF+ and REF?, can be used to provide any common mode charge to the input capacitors.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: December 24, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventor: Sandeep Monangi
  • Patent number: 10459477
    Abstract: A computing system can be arranged to generate a range of different frequencies with at least one oscillator of a clock module prior to providing a first clock frequency to a controller with a channel selector of the clock module in response to a dither control circuit. A system operation may be executed with the controller before the first clock frequency is changed to a second clock frequency during the execution of the system operation as directed by the dither control circuit. The second clock frequency can be chosen from the range of different frequencies. The computing system may return to the first clock frequency at the conclusion of the execution of the system operation.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: October 29, 2019
    Assignee: Seagate Technology LLC
    Inventors: Bruce D. Buch, Nicholas P. Mati, Matthew D. Rench
  • Patent number: 10454490
    Abstract: A dielectric resonator oscillator includes a dielectric resonator; a transmission line disposed adjacent the dielectric resonator; an active device having an input electrically connected to the transmission line; a matching network having an input electrically connected to an output of the active device and an output configured to be connected to a load; wherein both the transmission line and the active device are positioned sufficiently close to the dielectric resonator to form part of a resonant circuit with the dielectric resonator.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: October 22, 2019
    Assignee: Entropic Communications LLC
    Inventors: Branislav Petrovic, Tommy Yu, Troy Brandon, Ralph Duncan
  • Patent number: 10454492
    Abstract: A conversion time and an acquisition time of an ADC can be estimated so that a speed of the ADC can be calibrated. An ADC circuit can perform M bit-trials in its conversion phase and continue performing additional bit-trials in a calibration mode. The ADC can count the number of additional bit-trials performed, e.g., X bit-trials, that occur before the next conversion phase, where additional bit-trials can be considered to be the number of available bit-trials during an acquisition time if the ADC continues performing bit-trials instead of sampling an input signal. The ADC can estimate the conversion time and the acquisition time using M and X. Then, the conversion time of the ADC can be calibrated by adjusting one or more of the comparison time, DAC settling delay, and logic propagation delay.
    Type: Grant
    Filed: June 19, 2018
    Date of Patent: October 22, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Akira Shikata, Junhua Shen, Anping Liu
  • Patent number: 10447291
    Abstract: Techniques to provide automatic-gain ranging for high dynamic range by including a separate S/H capacitor, segmenting the S/H capacitor into a plurality of capacitors, and determining the number of segments to use for a sample. In this manner, the size of the S/H capacitor can be changed (by adjusting the number of capacitors), which can change the amount of input voltage that produces an amount of charge. Using these techniques, the full-scale input range for a sample of the analog input signal can be adjusted automatically based on the magnitude of the sample, which can provide better resolution and/or better noise performance for that particular sample then would otherwise be possible.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: October 15, 2019
    Assignee: Linear Technology Holding, LLC
    Inventor: Andrew Joseph Thomas
  • Patent number: 10367516
    Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 30, 2019
    Assignee: Analog Devices Global
    Inventors: Frederick Carnegie Thompson, Varun Agrawal, Jose Barreiro Silva, Declan M. Dalton
  • Patent number: 10360855
    Abstract: A semiconductor device having a novel structure is provided. Fluctuation in the grayscale voltage due to an offset voltage is suppressed. When a current corresponding to a lower-bit grayscale voltage is generated in a transconductance amplifier, voltages VHI and VLO supplied to the transconductance amplifier are alternately input to two input terminals in accordance with a digital signal of the most significant bit of lower bits. Since a change corresponding to the offset voltage is added to both the maximum and minimum values of the current output from the transconductance amplifier, fluctuation in the grayscale voltage due to the offset voltage can be suppressed.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: July 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Kei Takahashi
  • Patent number: 10354741
    Abstract: A sample and hold (S/H) circuit includes a capacitor coupling a sample node to a first voltage and an input line carrying a signal from an input. The S/H circuit also can include one or more transistors coupling the input line to the sample node. The S/H circuit also can include a switch coupled to one or more sources or drains of the one or more transistors and to a second voltage. The S/H circuit also can include a hold circuit coupled to the switch and to one or more gates of the one or more transistors, the hold circuit configured to open, during a sample period, the input line between the input and the sample node.
    Type: Grant
    Filed: September 19, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Mei-Chen Chuang, Alan Roth
  • Patent number: 10333541
    Abstract: A novel non-uniform sampling technique for a burst type signal. The analog signal is digitized with high sampling rate to maintain harmonics at higher frequencies and consequently the integrity of the analog signal. Then by using non-uniform sampling technique the most significant samples are selected for further processing which results in overall cost and power consumption reduction.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: June 25, 2019
    Assignee: Kiomars Anvari
    Inventors: Ehsan Hadizadeh Hafshejani, Ali Fotowat-Ahmady, Kiomars Anvari
  • Patent number: 10314503
    Abstract: Systems and methods for tracking dynamic structure in physiological data are provided. In some aspects, the method includes providing physiological data, including electroencephalogram (“EEG”) data, acquired from a subject and assembling a time-frequency representation of signals from the physiological data. The method also includes generating a dynamic model of at least one non-stationary spectral feature, such as at least one non-stationary spectral peak, using the time-frequency representation and a user indication, and applying a dynamic model of at least one non-stationary spectral feature in a parameter estimation algorithm to compute concurrent estimates of spectral parameters describing the at least one non-stationary spectral feature. The method also includes tracking the spectral parameters of the at least one spectral feature over time.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: June 11, 2019
    Assignee: The General Hospital Corporation
    Inventors: Michael J. Prerau, Patrick L. Purdon, Uri Eden
  • Patent number: 10295572
    Abstract: A voltage sampling circuit and method are provided. The voltage sampling circuit includes a capacitor having a first terminal and a second terminal. A first pre-charge circuit is coupled to a first voltage supply terminal and to the first terminal of the capacitor. The first pre-charge circuit is configured to receive a first control signal and pre-charge the capacitor to a first voltage. A switch circuit includes a first transistor having a first current electrode coupled to an input terminal of the voltage sampling circuit, a control electrode coupled to the first terminal of the capacitor, and a body electrode coupled to the second terminal of the capacitor. A second transistor having a first current electrode coupled to a second current electrode of the first transistor, a body electrode coupled to the second terminal of the capacitor, and a second current electrode coupled to an output terminal of the voltage sampling circuit.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: May 21, 2019
    Assignee: NXP USA, INC.
    Inventors: Khoi Mai, Michael Todd Berens, Jon Scott Choy
  • Patent number: 10277240
    Abstract: Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the bandpass signal with a bandpass filter, generating the real and imaginary parts of the complex analytic signal with a quadrature hybrid, determining the amplitude of the complex analytic signal by adding an even power-law transform of the real and imaginary parts of the complex analytic signal, and determining the phase of the complex analytic signal by comparing the real and imaginary parts of the complex analytic signal to zero and comparing an even power-law transform of the real and imaginary parts of the complex analytic signal to each other. Analog to digital converters and methods of converting complex analytic signals to digital signals are also disclosed.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: April 30, 2019
    Assignee: Associated Universities, Inc.
    Inventor: Omar Artemi Yeste Ojeda
  • Patent number: 10270461
    Abstract: This application discloses an implementation of a novel non-uniform sampling technique for a burst type signal. A simple circuit is developed that implements an analog computation of a complex digital calculation to skip the unnecessary samples and choose the optimum next sample. Then the optimum samples are selected for further processing which results in overall cost and power consumption reduction.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 23, 2019
    Assignee: Kiomars Anvari
    Inventors: Ehsan Hadizadeh Hafshejani, Ali Fotowat-Ahmady, Kiomars Anvari
  • Patent number: 10249279
    Abstract: A digital-to-analog converter performs a ?? computation process to start the ?? computation based upon the second clock signal with respect to the digital data of music sound if the ?? computation is not under execution when the control signal is outputted by the signal output process, a control process to inhibit the ?? computation based upon the second clock signal from being started with respect to the digital data of music sound until the ?? computation is not under execution when the ?? computation is under execution, and an output process to convert a computation result of the ?? computation process into an analog signal and output the analog signal.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 2, 2019
    Assignee: CASIO COMPUTER CO., LTD.
    Inventor: Goro Sakata
  • Patent number: 10224113
    Abstract: A sampling device samples a differential measuring voltage. The sampling device comprises a first holding device, a second holding device and a multiplexing circuit, which is configured to provide a differential sample of a sampled differential signal, derived from the differential measuring voltage by sampling with a first clock signal of a first clock rate, to the first holding device, at the occurrence of each HIGH-value of a second clock signal of a second clock rate being half of the first clock rate and provide a differential sample of the sample differential signal to the second holding device, at each LOW-value of the second clock signal. The sampling device comprises a reset device configured to reset the second holding device at or after each HIGH-value of the second clock signal and reset the first holding device at or after each LOW-value of the second clock signal.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: March 5, 2019
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Ols Hidri
  • Patent number: 10192491
    Abstract: A data driver capable of displaying images with a substantially uniform brightness, an organic light emitting display device using the same, and a method of driving the organic light emitting display device. The data driver includes a plurality of current sink units for controlling predetermined currents to flow through data lines, a plurality of voltage generators for resetting values of gray scale voltages using compensation voltages generated when the predetermined currents flow, a plurality of digital-to-analog converters for selecting one gray scale voltage among the gray scale voltages as a data signal in response to bit values of the data supplied from the outside, and a plurality of switching units for supplying the data signal to the data lines. The predetermined currents may be set equal to pixel currents that correspond to a maximum brightness.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: January 29, 2019
    Assignees: Samsung Display Co., Ltd., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)
    Inventors: Do Hyung Ryu, Bo Yong Chung, Hong Kwon Kim, Oh Kyong Kwon
  • Patent number: 10187673
    Abstract: Ingress noise from subscriber equipment is mitigated or prevented from reaching a cable television (CATV) network. All upstream signals including ingress noise are initially transmitted to the CATV network whenever their instantaneous power exceeds a threshold which typically distinguishes ingress noise from a valid upstream signal. Whenever the instantaneous power is below the threshold, ingress noise is blocked from reaching the CATV network. A gas tube surge protection device is included to resist component destruction and malfunction arising from lightning strikes and other high voltage, high current surges.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: January 22, 2019
    Assignee: PPC BROADBAND, INC.
    Inventors: Charles F. Newby, Gregory F. Halik, Matthew Kellogg
  • Patent number: 10158370
    Abstract: Methods and systems for generating a digital representation of the amplitude and phase of a bandpass signal are disclosed. The methods comprise filtering the bandpass signal with a bandpass filter, generating the real and imaginary parts of the complex analytic signal with a quadrature hybrid, determining the amplitude of the complex analytic signal by adding an even power-law transform of the real and imaginary parts of the complex analytic signal, and determining the phase of the complex analytic signal by comparing the real and imaginary parts of the complex analytic signal to zero and comparing an even power-law transform of the real and imaginary parts of the complex analytic signal to each other. Analog to digital converters and methods of converting complex analytic signals to digital signals are also disclosed.
    Type: Grant
    Filed: March 13, 2018
    Date of Patent: December 18, 2018
    Assignee: Assocciated Universities, Inc.
    Inventor: Omar Artemi Yeste Ojeda
  • Patent number: 10119822
    Abstract: Vibration gyroscope circuitry, connectable to a vibrating MEMS gyroscope, includes drive circuitry for driving the gyroscope and a measurement circuit for providing a drive measurement signal indicating displacement of a mass along a drive axis. Sense circuitry processes a sense measurement signal of the gyroscope indicating displacement of the mass along a sense axis. A digital sample clock generator includes an oscillator for generating a master clock, a counter for counting master clock periods during one period of an input signal derived from the drive measurement signal, and a number count monitor for determining during how many input signal periods the number count stays constant and for comparing a number of constant periods with a critical number of constant periods. A frequency shifter triggers the oscillator to shift the master clock frequency whenever the monitor determines that the number of constant periods exceeds the critical number of constant periods.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: November 6, 2018
    Assignee: NXP USA, Inc.
    Inventors: Thierry Cassagnes, Hugues Beaulaton, Laurent Cornibert, Yean Ling Teo
  • Patent number: 10116275
    Abstract: A physical quantity detection device includes a switched capacitor filter circuit having a first sample-and-hold circuit adapted to sample and hold a first signal, which is based on an output signal of a physical quantity detection element, an amplifier circuit to which an output signal of the first sample-and-hold circuit is input, and a first switched capacitor circuit to which a first output signal of the amplifier circuit is input, wherein an output signal of the first switched capacitor circuit is input to the amplifier circuit, and an A/D conversion circuit adapted to perform an A/D conversion on an output signal of the switched capacitor filter circuit.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: October 30, 2018
    Assignee: Seiko Epson Corporation
    Inventor: Noriyuki Murashima