Current Mirror Patents (Class 341/135)
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Patent number: 12289117Abstract: An input circuitry for receiving an analog input signal comprises: an input transistor configured to receive the analog input signal on a gate terminal of the input transistor wherein the input transistor is connected to a digital component providing a digital signal, and wherein the input transistor is configured to receive the digital signal on a bulk terminal of the input transistor; wherein the input transistor is configured to provide an output current based on the analog input signal and the digital signal, such that the input transistor provides digital-to-analog conversion of the digital signal received on the bulk terminal.Type: GrantFiled: December 19, 2022Date of Patent: April 29, 2025Assignees: IMEC VZW, KATHOLIEKE UNIVERSITEIT LEUVENInventors: Xiaohua Huang, Marco Ballini
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Patent number: 12119839Abstract: A digital-to-analog converter includes an amplifier, a voltage relaxation circuit, a base current source, a first weighting current source, and at least one second weighting current source. The amplifier receives a reference voltage and a feedback voltage, and generates an output voltage according to the reference voltage and the feedback voltage. The base current source is coupled to an output end of the amplifier through the voltage relaxation circuit, and is configured to generate an adjustable base current. The first weighting current source generates an adjustable first weighting current between a reference ground end and one of a current load and the voltage relaxation circuit according to a first bit of input data. The second weighting current source generates at least one second weighting current according to at least one second bit of the input data.Type: GrantFiled: December 6, 2022Date of Patent: October 15, 2024Assignee: Winbond Electronics Corp.Inventor: Ju-An Chiang
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Patent number: 12111340Abstract: An apparatus including a first comparator device. The first comparator device includes a first reference current providing device for providing a first reference current and a first comparison current providing device for providing a first comparison current. The first comparator device is configured to compare the first reference current with the first comparison current to obtain a first comparison result and output a first output signal characterizing the first comparison result based on the first comparison result.Type: GrantFiled: March 6, 2023Date of Patent: October 8, 2024Assignee: ROBERT BOSCH GMBHInventors: Taha Ibrahim Ibrahim Soliman, Tobias Kirchner
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Patent number: 12074609Abstract: A digital-to-analog converter device including a set of components, each component included in the set of components including a number of unit cells, each unit cell being associated with a unit cell size indicating manufacturing specifications of the unit cell is provided by the present disclosure. The digital-to-analog converter device further includes a plurality of switches, each switch included in the plurality of switches being coupled to a component included in the set of components, and an output electrode coupled to the plurality of switches. The digital-to-analog converter device is configured to output an output signal at the output electrode. A first unit cell size associated with a first unit cell included in the set of components is different than a second unit cell size associated with a second unit cell included in the set of components.Type: GrantFiled: March 7, 2022Date of Patent: August 27, 2024Assignee: REGENTS OF THE UNIVERSITY OF MINNESOTAInventors: Zhi Yang, Anh Tuan Nguyen, Diu Khue Luu, Jian Xu
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Patent number: 12059707Abstract: An ultrasound diagnostic apparatus and an ultrasonic probe are provided which are capable of reducing a leak current even in combined use of a low voltage transmission circuit and a high voltage transmission circuit including a buffer. The ultrasonic probe includes: a high voltage transmission circuit for transmitting a relatively high voltage; a low voltage transmission circuit for transmitting a relatively low voltage; and a transducer for selectively receiving a voltage transmitted from the high voltage transmission circuit and the low voltage transmission circuit. The high voltage transmission circuit includes: a current source for varying a current generated thereby and a current drawn thereby based on a set signal; a buffer for driving the transducer in accordance with the currents generated and drawn by the current source; and an impedance controller connected to an input terminal and an output terminal of the buffer.Type: GrantFiled: April 25, 2022Date of Patent: August 13, 2024Assignee: FUJIFILM Healthcare CorporationInventor: Toru Yazaki
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Patent number: 11925942Abstract: A roller crusher having two generally parallel rollers arranged to rotate in opposite directions, towards each other, and separated by a gap, where each roller having two ends. The roller crusher includes a flange attached to at least one of the ends of one of the rollers. The roller crusher further includes at least one mechanical scraper and a remote material removal device configured to output a material removing beam towards a target area. The at least one mechanical scraper and the remote material removal device are arranged consecutive to each other at an end of the roller with a flange for at least partially removing material accumulated on the flange and/or on the outer surface at the end of the roller. A method for operating a roller crusher is also provided.Type: GrantFiled: October 22, 2021Date of Patent: March 12, 2024Assignee: Metso Outotec USA Inc.Inventors: Vadim Reznitchenko, Keith Harbold, Brian Eric Behm
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Patent number: 11804848Abstract: An analog-to-digital converter of successive approximation register (SAR) type includes a comparator, a SAR logic circuit, and a capacitor digital-to-analog converter. The capacitor digital-to-analog converter includes a plurality of drivers. Each driver includes a capacitor and a split inverter. A first capacitor node of the capacitor is connected to one of comparison input terminals. The split inverter includes a pull-up unit connected to a first reference voltage and a pull-down unit connected to a second reference voltage. The split inverter drives a second capacitor node of the capacitor by selectively turning on one of the pull-up unit and the pull-down unit. A first one of the pull-up unit and the pull-down unit includes a full transistor, and a second one of the pull-up unit and the pull-down unit includes a first split transistor and a second split transistor. A short current is reduced using the split inverter.Type: GrantFiled: March 28, 2022Date of Patent: October 31, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Jaehoon Lee, Yong Lim, Seunghyun Oh
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Patent number: 11723122Abstract: Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.Type: GrantFiled: March 12, 2021Date of Patent: August 8, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Jiana Lou
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Patent number: 11626886Abstract: Methods, systems, and devices for thermometer coding for driving non-binary signals are described. A set of drivers may be used to drive a signal line, with each of the drivers calibrated to have different individual drive strengths. To drive a signal line to successive voltages in accordance with a non-binary modulation scheme, additional individual drivers of the set may be used. The different drive strengths of the individual drivers of the set may scale in non-linear fashion, which may offset non-linearities associated with the individual drivers as additional individual drivers of the set are activated.Type: GrantFiled: July 21, 2021Date of Patent: April 11, 2023Assignee: Micron Technology, Inc.Inventor: Dragos Dimitriu
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Patent number: 11508435Abstract: A charge pump apparatus including a first charge pump system, a second charge pump system, a switch transistor, and a voltage regulation circuit is provided. The first charge pump system converts a first supply voltage into a first boost voltage. The second charge pump system converts a second supply voltage into a second boost voltage. The switch transistor is coupled to the first charge pump system and the second charge pump system, and outputs an output voltage according to the second boost voltage. The switch transistor includes a control terminal receiving the second boost voltage, a first terminal receiving the first boost voltage, and a second terminal outputting the output voltage. The voltage regulation circuit controls the second charge pump system according to the output voltage to adjust the second boost voltage so that the output voltage approaches to a target output value.Type: GrantFiled: July 19, 2021Date of Patent: November 22, 2022Assignee: eMemory Technology Inc.Inventors: Chia-Fu Chang, Sung-Ling Hsieh
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Patent number: 11482281Abstract: Circuits and methods are disclosed for voltage-mode bit line precharge for random-access memory cells. A circuit includes an array of random access memory cells; a low-impedance voltage source configured to provide a precharge voltage; and a control circuit configured to precharge a bit line of one of the random access memory cells to the precharge voltage using the low-impedance voltage source prior to reading the one of the random access memory cells.Type: GrantFiled: April 29, 2021Date of Patent: October 25, 2022Assignee: Hefei Reliance Memory LimitedInventor: Danut Manea
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Patent number: 11476859Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has a first terminal and a second terminal. The compensation circuit has a third terminal and a fourth terminal. The third terminal is coupled to the first terminal, and the fourth terminal is coupled to the second terminal. The compensation circuit is configured to source current into the first terminal responsive to an increase in voltage on the second terminal, and to sink current from the first terminal responsive to a decrease in voltage on the second terminal.Type: GrantFiled: June 1, 2021Date of Patent: October 18, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Meghna Agrawal, Debapriya Sahu
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Patent number: 11445154Abstract: A laser drive apparatus is provided with a digital to analog converter including current sources of a number corresponding to a bit number of a digital input code and switches of a number corresponding to the number of bits. The digital input code is converted from input video data, and provided to a DA converter, that generates RGB drive currents for a laser scanning type image display apparatus driven by the laser drive apparatus, and output currents from current sources are weighted in accordance with bits of the digital input code. A ratio of each of the output currents from each of the current sources to a load capacity of a driver having each of current mirror circuits is identical for all bits corresponding to each of the current sources, and the current mirror circuits is configured to distribute load capacity of the driver circuit.Type: GrantFiled: December 21, 2018Date of Patent: September 13, 2022Assignee: Nisshinbo Micro Devices Inc.Inventor: Masaki Kiyokawa
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Patent number: 10986708Abstract: Aspects of the disclosure provide for a circuit including a binary-weighted DAC, a first transistor, a second transistor, a switch, a first current mirror, a second current mirror. The binary-weighted DAC is coupled between a first node and a second node and configured to receive a plurality of bits of a digital control signal. The first transistor has a source coupled to the first node, a drain coupled to a third node, and a gate coupled to a fourth node. The second transistor has a source coupled to the first node, a drain coupled to the third node, and a gate. The switch is coupled between the gate of the second transistor and the fourth node and configured to receive a partition control signal. The first current mirror is coupled to the third node and the second node. The second current mirror is coupled to the first current mirror.Type: GrantFiled: November 21, 2019Date of Patent: April 20, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Jiana Lou
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Patent number: 10692433Abstract: The present invention is to improve on an emissive display by providing a backplane and modulation system that enables fabrication of multi-color or monochrome LED display systems that operate efficiently and without objectionable image artifacts. One aspect of the present invention is to implement the backplane of an emissive display that offers high precision across an array of pixels and extremely low variation. The present invention uses a large L FET to generate a reference current and then uses the same large L FET to act as a current source mirroring the reference current, thereby ensuring a substantially perfect match between reference current FET and current source FET.Type: GrantFiled: July 2, 2019Date of Patent: June 23, 2020Assignee: JASPER DISPLAY CORP.Inventor: Bo Li
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Patent number: 10608661Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a first plurality of digital-to-analog converter cells configured to generate a first analog signal. Further, digital-to-analog converter includes a second plurality of digital-to-analog converter cells configured to generate a second analog signal. The first analog signal and the second analog signal form a differential signal pair. Further, the digital-to-analog converter includes a transmission line transformer comprising a first input node coupled to the first plurality of digital-to-analog converter cells, a second input node coupled to the second plurality of digital-to-analog converter cells, and a first output node. The transmission line transformer is configured to present a first impedance at the first and second input nodes and to present a second impedance at the first output node.Type: GrantFiled: March 29, 2019Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Daniel Gruber, Ramon Sanchez, Kameran Azadet, Martin Clara
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Patent number: 10110263Abstract: In a system, known digitizer signals (known analog signals or digital representations of known analog signals) are generated. The known digitizer signals are input into digitizers (analog-to-digital converter (ADCs) or digital-to-analog converter (DACs)) to output generated digitizer signals (generated digital representations or generated analog signals). The generated digitizer signals are analyzed in relation to the known digitizer signals to generate coupling coefficients, which can be either scalar quantities or finite-impulse-response (FIR) filter functions. Subsequent digitizer signals are generated. The subsequent digitizer signals are modified using the coupling coefficients to generate modified digitizer signals according to formulae. The modified digitizer signals are used directly as digital representations, or are input to the DACs to output modified analog signals that substantially match subsequent analog signals.Type: GrantFiled: January 30, 2018Date of Patent: October 23, 2018Assignee: Roshmere, Inc.Inventors: Eduardo Temprana Giraldo, Nikola Alic
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Patent number: 9779697Abstract: A display apparatus for displaying a display information includes a display panel, and a plurality of gate drivers and a plurality of source drivers coupled to the display panel. When one abnormal driver exists among the plurality of gate drivers and the plurality of source drivers, the other functionally operating gate drivers and source drivers transform the display information into a transformed display information to transmit the transformed display information to the display panel for a display operation.Type: GrantFiled: July 27, 2015Date of Patent: October 3, 2017Assignee: Sitronix Technology Corp.Inventors: Chih-Hsiung Lin, Yung-Sheng Tseng
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Patent number: 9583631Abstract: A transistor with uniform density of poly silicon includes a gate terminal, a drain terminal, and a source terminal. The gate terminal is constructed by a plurality of separated poly silicon, such that the density of the poly silicon is uniform.Type: GrantFiled: March 17, 2016Date of Patent: February 28, 2017Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.Inventors: Jade Deng, Keith Ma
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Patent number: 9490794Abstract: Systems, circuits, and methods for operating an Insulated-Gate Bipolar Transistor (IGBT) are provided. A switching circuit is described that includes a first current path and a second current path. The first current path carries current away from the gate of the IGBT during a first phase of switching and the second current path carries current away from the gate of the IGBT during a second phase of switching.Type: GrantFiled: April 21, 2015Date of Patent: November 8, 2016Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Bin Zhang, Mei Zhen Choo
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Patent number: 9438267Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.Type: GrantFiled: December 1, 2015Date of Patent: September 6, 2016Assignee: Innophase, Inc.Inventors: Xuejun Zhang, Yang Xu
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Patent number: 9203424Abstract: A digital-to-analog converter circuit includes an input to receive a digital input signal having multiple bits. A modulation circuit is coupled to respond to less significant bits of the digital input signal by outputting a modulation signal that alternates between a logic low level and a logic high level. A digital-to-analog circuit is configured to convert more significant bits of the digital input signal to a first analog level. The digital-to-analog circuit is configured to alternate an analog output between the first analog level corresponding to a value of the more significant bits and a second analog level corresponding to one of adjacent values of the more significant bits in response to the modulation signal.Type: GrantFiled: May 13, 2014Date of Patent: December 1, 2015Assignee: Power Integrations, Inc.Inventors: Tiziano Pastore, Ricardo Luis Janezic Pregitzer, Mingming Mao, Peter Vaughan
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Patent number: 9203420Abstract: A DAC using current mirrors suitable for use in a modulator. Embodiments include a current-generating circuit to provide an information signal; a bias current source; a current mirror having a mirror input transistor connected to the current generating circuit and the bias current source, and being driven by the bias current and the varying current signal and having a corresponding varying voltage signal at a control terminal; a signal shaping filter interposed between the mirror input transistor and an output mirror transistor configured to limit a bandwidth of the varying voltage signal; the output mirror transistor configured to generate a band-limited varying current signal and a mirrored bias current; and, a mirrored bias current reduction circuit connected to the output mirror transistor configured to reduce the mirrored bias current.Type: GrantFiled: February 5, 2014Date of Patent: December 1, 2015Assignee: INNOPHASE INC.Inventors: Xuejun Zhang, Yang Xu
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Patent number: 9097742Abstract: There is provided a Multi-functional measuring and waveform-generating equipment with a probe. The equipment is capable of measuring element values of electric or electronic devices and electrical quantities such as a voltage, and generating electrical signals with various waveforms. Also, a user can conveniently manipulate and handily carry it. The equipment provides functions of measuring a voltage, a resistance, an inductance, capacitance, a frequency, the number of pulses, and the voltage level of a logic signal; verifying diode polarities, measuring the voltage level of a pulse signal, and modes generating a rectangular pulse train and a PWM signal by the simple combinations of two switches. Additionally, it also offers a much cheaper equipment than other existing expensive apparatuses, and provide better usability at experimental environments because it is small-sized, light, and conveniently portable, compared to conventional equipments that are large-sized, heavy, and not easy to carry.Type: GrantFiled: December 12, 2013Date of Patent: August 4, 2015Assignee: INDE UNIVERSITY INDUSTRY-ACADEMIC COOPERATION FOUNDATIONInventors: Nam Tae Kim, Tae Kyoung Hwang, Jeong Ho Lee, Sung Jin Kim
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Patent number: 9030342Abstract: An integrated circuit includes a component calculator configured to compute at least one component value of a highly programmable analog-to-digital converter (ADC) from at least one application parameter, and a mapping module configured to map the component value to a corresponding register setting of the ADC based on at least one process parameter, wherein the integrated circuit produces digital control signals capable of programming the ADC. In a specific embodiment, the component calculator uses an algebraic function of a normalized representation of the application parameter to approximately evaluate at least one normalized ADC coefficient. The component value is further calculated by denormalizing the normalized ADC coefficient. In another specific embodiment, the component calculator uses an algebraic function of the application parameter to calculate the component value.Type: GrantFiled: July 18, 2013Date of Patent: May 12, 2015Assignee: Analog Devices GlobalInventors: Kevin Cao-Van Lam, Richard E. Schreier, Donald W. Paterson
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Patent number: 9007252Abstract: An analog to digital conversion method includes charging a capacitor through an analog signal to sample a voltage of the analog signal; coupling the capacitor and a plurality of reference voltages to a comparator when a voltage of the capacitor is equal to the voltage of the analog signal, to compare the voltage of the capacitor with the reference voltages and generate a first comparison result; coupling the capacitor to a ramp generator when a status of the first comparison result changes, to compare a ramp signal of the ramp generator with a voltage difference of a first reference voltage and the voltage of the capacitor and generate a second comparison result; obtaining a voltage of the ramp signal when a status of the second comparison result changes; and obtaining a digital code of the analog signal according to the first reference voltage and the voltage of the ramp signal.Type: GrantFiled: April 29, 2014Date of Patent: April 14, 2015Assignee: NOVATEK Microelectronics Corp.Inventor: Jer-Hao Hsu
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Patent number: 9007246Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding, reference source without any substantial affect upon its full scale output.Type: GrantFiled: April 22, 2013Date of Patent: April 14, 2015Assignee: Broadcom CorporationInventors: Ovidiu Bajdechi, Tom W. Kwan
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Patent number: 9000969Abstract: A received plurality of signals may be filtered to select an in-band signal and/or an out-of-band. A signal strength of the selected signal(s) may be measured. A resolution of an analog-to-digital converter may be controlled based on the measured signal strength(s). The selected in-band signal may be converted to a digital representation via the analog-to-digital converter. The resolution may be decreased when the strength of the in-band signal is higher, and increased when the strength of the in-band signal is lower. The resolution may be increased when the strength of the out-of-band signal is higher, and decreased when the strength of the out-of-band signal is lower. A signal-to-noise ratio and/or dynamic range of the selected signal(s) may be determined based on the measured signal strength(s), and may be utilized to adjust the resolution of the analog-to-digital converter.Type: GrantFiled: October 25, 2012Date of Patent: April 7, 2015Assignee: Broadcom CorporationInventor: Ahmadreza Rofougaran
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Patent number: 8963761Abstract: A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to ½ of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.Type: GrantFiled: July 30, 2013Date of Patent: February 24, 2015Assignee: Realtek Semiconductor Corp.Inventors: Jen-Huan Tsai, Po-Chiun Huang, Shih-Hsiun Huang
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Patent number: 8941519Abstract: A light intensity subtractor according to one aspect of the present invention includes a light subtraction unit, a feedback circuit, a light input port, a first light output port, and a second light output port. The light subtraction unit receives input light through the light input port, outputs first output light to the first light output port, and outputs second output light to the second light output port. The light subtraction unit generates the first output light by reducing the light intensity of the second output light from the light intensity of the input light in accordance with a control voltage. The feedback circuit is connected to the light subtraction unit through the second light output port, and outputs the control voltage in accordance with the light intensity of the received second output light.Type: GrantFiled: November 18, 2011Date of Patent: January 27, 2015Assignee: NEC CorporationInventor: Kenji Sato
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Patent number: 8928506Abstract: Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.Type: GrantFiled: April 9, 2014Date of Patent: January 6, 2015Assignee: MaxLinear, Inc.Inventors: Raja Pullela, Curtis Ling
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Patent number: 8922409Abstract: A switch-driving circuit and a Digital-to-Analog Converter (DAC) using the switch-driving circuit are provided. The switch-driving circuit includes a main cell and a reference cell. The main cell includes a current source and a resistance-control component electronically connected to the current source. The reference cell is coupled to the current source and the resistance-control component, and includes a first loop, the first loop is configured to track a target reference voltage so as to provide at least one first control voltage to control a resistance change of the resistance-control component. The reference cell and the main cell are implemented by MOS transistors in place of capacitors which occupy an increased circuit area, rendering reduced circuit area for the switch-driving circuit, and decreasing manufacturing costs. Further, the switch-driving circuit outputs a voltage signal with reduced noise, increasing the performance of the Digital-to-Analog Converter.Type: GrantFiled: March 15, 2013Date of Patent: December 30, 2014Assignee: MediaTek Singapore Pte. Ltd.Inventors: Cheng Tao, Yue Feng, Kun Lan, Yu-Kai Chou
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Patent number: 8872685Abstract: A digital-to-analog converter (DAC) includes, in part, a multitude of input stages that supply currents to a pair of current summing nodes in response to a digital signal, and an impedance attenuator coupled between the current summing nodes and the output of the DAC. The impedance attenuator is adapted, among other function, to increase the range of impedances of the output load, to account for changes in the output load impedance due to variations in the process, voltage and temperature, and to decouple the impedances seen by the summing nodes from the load impedance. The impedance attenuator further includes a differential-input, differential-output amplifier with programmable common-mode gain bandwidth to control the harmonic distortion of the amplifier. The impedance attenuator optionally includes a pair of cross-coupled capacitors to control the harmonic distortion of the amplifier.Type: GrantFiled: March 15, 2013Date of Patent: October 28, 2014Assignee: QUALCOMM IncorporatedInventors: Tongyu Song, Sang Min Lee, Derui Kong, Dongwon Seo
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Patent number: 8847808Abstract: A biasing circuit facilitates process, temperature, and voltage insensitive operation of a circuit block. The biasing circuit may include a replicate circuit corresponding to the circuit block. The replicate circuit may be a low complexity version of the circuit block that includes selected process, temperature, or voltage sensitive components of the circuit block. The biasing circuit enforces bias conditions on the circuit block that are informed by the response of the replicate circuit to variations in process, temperature, and voltage.Type: GrantFiled: June 10, 2013Date of Patent: September 30, 2014Assignee: Broadcom CorporationInventors: Hongwu Chi, Michael Ming Lee
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Patent number: 8836560Abstract: A digital to analog converter (DAC) includes: first and second nodes; a first switching device; a second switching device; and a switch control module. The switch control module selectively configures the first and second switching devices such that: in a first configuration, the first switching device connects a first current to the first node and the second switching device connects a second current to the second node; in a second configuration, the first switching device connects the first current to the second node and the second switching device connects the second current to the first node; and in a third configuration, the first and second switching devices disconnect the first current and the second current from the first and second nodes.Type: GrantFiled: December 5, 2012Date of Patent: September 16, 2014Assignee: Maxim Integrated Products, Inc.Inventor: Matthew Felder
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Patent number: 8760332Abstract: An apparatus and a method for digital-analog conversion are provided. The apparatus includes a first cell matrix for outputting a current of a signal corresponding to a number of Most Significant Bits (MSBs) of an input digital signal, a second cell matrix for outputting a current of a signal corresponding to a number of Least Significant Bits (LSBs) of the input digital signal, an amplifier for amplifying the output current of the second cell matrix at a preset amplification, and an adder for adding the output current of the first cell matrix and the output current of the amplifier.Type: GrantFiled: December 5, 2012Date of Patent: June 24, 2014Assignee: Samsung Electronics Co., Ltd.Inventor: Jong-Woo Lee
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Patent number: 8665125Abstract: The device comprises a successive approximation register, a capacitive digital-to-analog converter comprising a plurality of capacitors, the plurality of capacitors being coupled with a first side to a common node; a comparator coupled to the common node and being adapted to make bit decisions by comparing a voltage at the common node with another voltage level, and a SAR control stage for providing a digital code representing a conversion result. The device is configured to operate in a calibration mode, where the device is configured to sample a reference voltage on a first capacitor of the plurality of capacitors by coupling one side of the first capacitor to the reference voltage, to perform a regular conversion cycle with at least those capacitors of the plurality of capacitors having lower significance than the first capacitor and to provide the conversion result of the regular conversion cycle for calibrating the first capacitor.Type: GrantFiled: August 8, 2012Date of Patent: March 4, 2014Assignee: Texas Instruments Deutschland GmbHInventors: Michael Reinhold, Martin Allinger, Frank Ohnhaeuser
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Patent number: 8624766Abstract: Embodiments of the present disclosure provide a method and system for an auto-ranging analog-to-digital converter (ADC) for dynamically scaling inputs to an ADC. The auto-ranging ADC includes a dynamically configurable transistor arrangement for delivering a load current and a replica device for replicating the load current. A current sense resistor generates a replicated load voltage based on the replicated current. The ADC generates a digital value based on the replicated load voltage. The auto-ranging ADC also includes an auto-ranging controller for dynamically configuring the transistor arrangement based on the digital value to scale the inputs to the ADC.Type: GrantFiled: November 30, 2011Date of Patent: January 7, 2014Assignee: Standard Microsystems CorporationInventor: Srinivas K. Pulijala
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Patent number: 8576214Abstract: A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.Type: GrantFiled: February 19, 2010Date of Patent: November 5, 2013Assignees: Hitachi Displays, Ltd., Panasonic Liquid Crystal Display Co., Ltd.Inventors: Hiroko Sehata, Kouichi Kotera, Yoshihiro Kotani, Shuuichirou Matsumoto
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Patent number: 8564465Abstract: An analog to digital conversion includes a multiplexor circuit for receiving analog input signals and, responsive to a select input, an analog to digital converter circuit to convert a selected analog signal into a digital signal, a conversion starting device to send a conversion start signal on the basis of a trigger event, the conversion starting device being responsive to a select input, a sequencer to control the analog to digital converter circuitry to execute one sequence conversion on the basis of one conversion sequence instruction, and a FIFO register block to receive conversion sequence instructions and being able to queue each new received conversion sequence instruction if an actual conversion sequence is in progress and to control the sequencer to execute a new sequence conversion instruction after the conversion sequence is executed.Type: GrantFiled: April 5, 2012Date of Patent: October 22, 2013Assignee: STMicroelectronics, Srl.Inventors: Gianluigi Forte, Dino Costanzo, StelloMatteo Billeā²
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Patent number: 8537040Abstract: Systems and methods are disclosed for performing data conversion by matching current sources using a thin oxide device; and minimizing voltage stress on the thin oxide device during operation or power down.Type: GrantFiled: November 15, 2011Date of Patent: September 17, 2013Assignee: Integrated Device Technology, Inc.Inventors: Mansour Keramat, Yuan-Ju Chao
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Patent number: 8525719Abstract: The invention includes a successive approximation register, a digital-to-analog converter, a comparator and a control stage. The control stage initially sets the successive approximation register to a first digital value. The digital-to-analog converter converts the digital value stored in the successive approximation register to an analog value. The comparator compares the converted digital value with an analog input value. The control stage restricts subsequent analog-to-digital conversion for the analog input value to a search interval above or below the first digital value depending on whether the analog input value is greater or lower than the converted analog value of the first digital value.Type: GrantFiled: March 17, 2011Date of Patent: September 3, 2013Assignee: Texas Instruments Incorporated Deutschland, GmbHInventors: Joerg Schreiner, Bernhard Ruck, Harinath Renukamurthy
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Patent number: 8525716Abstract: An electronic circuit comprises a digital-to-analog converter (DAC) core circuit having a current source device and a digital input bit. An isolation circuit is also provided and is connected to the DAC core circuit. The isolation circuit is configured to selectively provide a source bias signal to the current source device. The isolation circuit also is configured to isolate the source bias signal from the current source device based on a state of the digital input bit.Type: GrantFiled: December 29, 2011Date of Patent: September 3, 2013Assignee: Texas Instruments IncorporatedInventors: Karan S. Bhatia, Neeraj P. Nayak
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Patent number: 8451155Abstract: A transmission circuit for use with an ultrasonic probe including an ultrasonic transducer is provided. The transmission circuit includes a high voltage current DAC configured to output a drive current of an ultrasonic transducer to transmit and receive ultrasound, and a waveform generator configured to output a control signal from the high voltage current DAC to the high voltage current DAC with a predetermined timing. The control signal configured to output the drive current with a desired magnitude.Type: GrantFiled: February 25, 2011Date of Patent: May 28, 2013Assignee: General Electric CompanyInventors: Shinichi Amemiya, Bruno Haider, Naresh Kesavan Rao, Krishnakumar Sundaresan, Thomas Halvorsrod
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Patent number: 8441381Abstract: A method and apparatus is disclosed to compensate for gate leakage currents of thin oxide devices that have very thin oxide layers in a current mirror of a digital-to-analog converter (DAC). The DAC converts a digital input signal from a digital representation in a digital signaling domain to an analog representation in an analog signaling domain to provide an analog output signal. The DAC uses one or more transistors to convert the digital input signal from the digital representation to the analog representation. These transistors are typically implemented using thin oxide devices that have very thin oxide layers and corresponding gate leakage currents that are associated with these very thin oxide layers. The current-steering DAC provides these gate leakage currents independent of its corresponding reference source without any substantial affect upon its full scale output.Type: GrantFiled: September 27, 2011Date of Patent: May 14, 2013Assignee: Broadcom CorporationInventors: Ovidiu Bajdechi, Tom W. Kwan
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Patent number: 8390491Abstract: Embodiments of the present invention may provide an integrated circuit that may comprise a first transistor to receive an input voltage signal at its gate and generate an output voltage signal at its drain. Further, the integrated circuit may comprise a second transistor to form an active load of the first transistor, the second transistor may have its drain and gate coupled to the drain of the first transistor. In addition, the integrated circuit may comprise a third transistor to form a current mirror with the second transistor, a fourth transistor to form an active load of the third transistor, and a fifth transistor to form a current mirror with the fourth transistor. The fifth transistor may be connected to the drain of the second transistor. The integrated circuit may form an amplifier and Gm stage of a reference buffer.Type: GrantFiled: January 14, 2011Date of Patent: March 5, 2013Assignee: Analog Devices, Inc.Inventor: Tsutomu Wakimoto
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Patent number: 8199042Abstract: Physical layouts of integrated circuits are provided, which may include an analog-to-digital converter including a plurality of comparators. Individual transistors of each comparator of the plurality are arranged in a one-dimensional row in a first direction. Neighboring comparators of the plurality of comparators are positioned relative to each other in an abutting configuration in a second direction orthogonal to the first direction. The plurality of comparators may include multiple, inter-coupled outputs. Such an ADC may be called a Benorion Analog-to-Digital Converter. A method for fabricating an integrated circuit is also provided.Type: GrantFiled: April 23, 2010Date of Patent: June 12, 2012Assignee: Integrated Device Technology, Inc.Inventors: Jeffrey G. Barrow, Benjamin O. Barrow
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Patent number: 8164499Abstract: In an exemplary decision-feedback equalizer (DFE) of a serializer/deserializer (SerDes) receiver, a single current mirror array is shared by multiple current digital-to-analog converter (IDAC) functions. The DFE has an initial amplifier stage that applies an initial coefficient COEFF0 to an input data signal and a number of (e.g., five) additional amplifier stages that apply additional coefficients (e.g., COEFF1-COEFF5) to different delayed versions of the recovered output data stream. The outputs of the initial and multiple additional amplifier stages are summed to generate an equalized data signal that is applied to a clock-and-data recovery (CDR) circuit. Due to certain characteristics of the equalizer function, the multiple additional amplifier stages can be implemented using a single shared current mirror array, which save significant amounts of chip area compared to conventional implementations in which each additional amplifier stage has its own dedicated current mirror array.Type: GrantFiled: June 11, 2010Date of Patent: April 24, 2012Assignee: Lattice Semiconductor CorporationInventors: Richard Booth, Paulius Mosinskis, Phillip Johnson, David Onimus
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Patent number: 8078122Abstract: Circuitry that generates an interface signal between a first and a second integrated circuit (IC). The circuitry includes a reference circuit that provides a reference signal, an interface circuit, and a circuit element. The interface circuit is implemented on the first IC, operatively couples to the reference circuit, receives the reference signal and a data input, and generates the interface signal. The circuit element is implemented on the second IC, operatively couples to the control circuit, receives the interface signal, and provides an output signal. The reference signal can be a voltage or a current signal, and can be generated in the first or second IC. The interface circuit can be implemented with a current mirror coupled to a switch array, and can be oversampled to ease the filtering requirement. The interface signal can be a differential current signal having multiple (e.g., four, eight, or more) bits of resolution. The circuit element can be, for example, a VGA, a modulator, or other circuits.Type: GrantFiled: July 21, 2003Date of Patent: December 13, 2011Assignee: QUALCOMM IncorporatedInventors: Gurkanwal Sahota, Mehdi H. Sani, Sassan Shahrokhinia
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Publication number: 20110210878Abstract: An analog-to-digital converter with comparators with multiple, inter-coupled, outputs is provided, which may be also called a Benorion Analog-to-Digital Converter (ADC) or a Benorion Converter. The analog-to-digital converter includes a plurality of comparators operably coupled for receiving an analog input signal and configured for comparing the analog input signal with a plurality of voltage reference signals. Each comparator of the plurality is configured for generating a plurality of comparator outputs comprising a primary comparator output, and at least one additional comparator output selected from the group consisting of positive comparator outputs and negative comparator.Type: ApplicationFiled: February 26, 2010Publication date: September 1, 2011Applicant: INTEGRATED DEVICE TECHNOLOGY, INC.Inventor: Jeffrey G. Barrow