With Particular Solid State Devices (e.g., Gunn Effect Device, Josephson Device, Drift Transistor, Using Solid State Active Devices As Impedances) With Other At Longer Intervals) Patents (Class 341/133)
  • Patent number: 11659302
    Abstract: A differential subrange analog-to-digital converter (ADC) converts differential analog image signals received from sample and hold circuits to a digital signal through an ADC comparator. The comparator of the differential subrange ADC is shared by a successive approximation register (SAR) ADC coupled to provide both M upper output bits (UOB) and a ramp ADC coupled to provide N lower output bits (LOB). Digital-to-analog converters (DACs) of the differential subrange SAR ADC comprises 2M buffered bit capacitor fingers connected to the comparator. Each buffered bit capacitor finger comprises a bit capacitor, a bit buffer, and a bit switch controlled by the UOB. Both DACs are initialized to preset values and finalized based on the values of the least significant bit of the UOB. The subsequent ramp ADC operation will be ensured to have its first ramp signal ramps in a monotonic direction and its second ramp signal ramp in an opposite direction.
    Type: Grant
    Filed: December 2, 2021
    Date of Patent: May 23, 2023
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chao-Fang Tsai, Zheng Yang, Chun-Hsiang Chang
  • Patent number: 11435416
    Abstract: A magnetic field measuring apparatus includes a digital FLL circuit. The digital FLL circuit includes a first amplifier configured to amplify voltage output by a superconducting quantum interference device in accordance with strength of a magnetic field strength, an AD converter configured to, convert analog signals to first digital values, an integrator configured to integrate the first digital values output by the AD converter, a DA converter configured to receive an integral value output by the integrator as a second digital value, convert the second digital value to voltage, and output the converted voltage, a signal switcher configured to connect an output of the first amplifier or an output of the DA converter to an input of the AD converter, and a storage unit configured to store a correction value that corrects the integral value received by the DA converter.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: September 6, 2022
    Assignee: Ricoh Company, Ltd.
    Inventor: Takashi Yasui
  • Patent number: 11133820
    Abstract: A delta sigma modulator includes two adders, an integrator stage, a reconfigurable local resonator, an analog-to-digital converter (ADC), and a digital-to-analog converter (DAC). A first adder receives an analog input signal at an additive input, and the integrator stage receives an output from the first adder and generates an integrated signal. The reconfigurable local resonator receives the integrated signal and generates a resonator output signal. A second adder receives the resonator output signal, the integrated signal, and the input signal. The ADC receives an output from the second adder and generates a digital output signal which can be provided to other circuits. The DAC receives the digital output signal, and generates and provides a feedback signal to a subtractive input of the first adder. The reconfigurable local resonator acts as a resonator, but reconfigures to act as a low pass filter in response to overload conditions.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: September 28, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Binan Wang
  • Patent number: 11120869
    Abstract: One example includes a memory cell system. The memory cell system includes a quantizing loop configured to conduct a quantizing current in a first direction corresponding to storage of a first state of a stored memory state of the memory cell system and to conduct the quantizing current in a second direction opposite the first direction corresponding to storage of a second state of the stored memory state of the memory cell system. The memory cell system also includes a bias element arranged in the quantizing loop and which is configured to provide a substantially constant flux bias of the quantizing loop in each of the first and second states of the stored memory state.
    Type: Grant
    Filed: September 15, 2020
    Date of Patent: September 14, 2021
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Ofer Naaman, Donald L. Miller, Henry Y Luo
  • Patent number: 11018686
    Abstract: A device for monitoring voltage in a battery-operated system, the device including: a ladder selector configured to select between a first resistive ladder and a second resistive ladder; the first resistive ladder includes: a first string of resistors coupled between a sensing input node and a first node of the ladder selector; and a first set of transistors configured to tap intermediate nodes of a set of resistors in the first string of resistors; the second resistive ladder includes: a second string of resistors coupled between the sensing input node and a second node of the ladder selector; and a second set of transistors configured to tap intermediate nodes of a set of resistors in the second string of resistors; and wherein a selected transistor in one of the first set of transistors or the second set of transistors is turned on, and non-selected transistors of the first set of transistors and the second set of transistors are turned off to set a threshold voltage for a sensing output node.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: May 25, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Santhosh Kumar Gowdhaman, Divya Kaur
  • Patent number: 10797684
    Abstract: A superconducting waveform synthesizer produces an arbitrary waveform and includes an encoder that produces a bitstream; a pattern generator that produces a current bias pulse from the bitstream; a Josephson junction that produces a quantized output pulse from the current bias pulse; and a converter that produces an arbitrary waveform from the quantized output pulse. A process for producing an arbitrary waveform includes producing a bitstream; producing a current bias pulse from the bitstream; communicating the current bias pulse to a Josephson junction; producing, by the Josephson junction, a quantized output pulse from the current bias pulse; producing a quantized output pulse from the current bias pulse; and producing an arbitrary waveform from the quantized output pulse.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: October 6, 2020
    Assignee: GOVERNMENT OF THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventors: Samuel Paul Benz, Justus Albert Brevik, Manuel Angel Castellanos Beltran, Paul David Dresselhaus, Peter Farrell Hopkins, Christine Annette Donnelly
  • Patent number: 10651808
    Abstract: Output amplifier comprising a stack of compound superconducting quantum interference device (SQUID) output amplifier stages and related methods are provided. A method includes receiving a first pulse train comprising a first plurality of single flux quantum (SFQ) pulses. The method may further include receiving a second pulse train comprising a second plurality of SFQ pulses, where the second pulse train is delayed by a predetermined fraction of a clock cycle relative to the first pulse train. The method may further include using the stack of the plurality of compound SQUID output amplifier stages converting the first plurality of SFQ pulses and the second plurality of SFQ pulses into a voltage waveform, where each of the plurality of compound SQUID output amplifier stages comprises a pair of superconducting quantum interference devices (SQUIDs).
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: May 12, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Jonathan D. Egan, Quentin P. Herr
  • Patent number: 10615826
    Abstract: Disclosed is a transceiver that includes a three-dimensional array of Josephson junctions. When transmitting, the junctions drive an array of micro-antennas. When receiving, the micro-antennas drive the array of Josephson junctions. By extending the junction array into the third dimension, this transceiver packages a large number of Josephson junctions into a small volume, thus increasing the power of a transmitted beam. Multiple different micro-antenna arrays can be included, thus allowing the transceiver to work efficiently at multiple frequency ranges.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: April 7, 2020
    Assignee: United States of America as represented by the Secretary of the Navy
    Inventors: Lee Lemay, Marcio Calixto de Andrade
  • Patent number: 10608044
    Abstract: Capacitively coupled superconducting integrated circuits powered using alternating current clock signals are described. An example superconducting integrated circuit includes a first clock line coupled via a first capacitor to a first superconducting circuit including a first Josephson junction, where the first capacitor is configured to receive a first clock signal having a first phase and couple a first bias current to the first superconducting circuit. The superconducting integrated circuit further includes a second clock line coupled via a second capacitor to a second superconducting circuit including a second Josephson junction, where the second capacitor is configured to receive a second clock signal having a second phase and couple a second bias current to the second superconducting circuit, and where the second phase is different from the first phase.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 31, 2020
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Anna Y. Herr, Quentin P. Herr, Joshua A. Strong
  • Patent number: 10585400
    Abstract: The method comprises providing a time-to-digital converter with a measurement period (3) for registration of events (1), and selecting time intervals of independent durations (4), each of the durations being independent of the registration of events. At each registration of an event, the time-to-digital converter is blocked from further registration for one of the time intervals of independent duration. Thus the recorded lengths of the time intervals (11, 13, 14, 16) corresponding to the occurrence of the events within each measurement period are uniformly distributed and a time-domain bias is avoided. The time-to-digital converter circuit includes a controlled gate for blocking the time-to-digital converter.
    Type: Grant
    Filed: April 24, 2017
    Date of Patent: March 10, 2020
    Assignee: ams AG
    Inventor: Marc Drader
  • Patent number: 10574251
    Abstract: One example includes a Josephson analog-to-digital converter (ADC) system. The system includes a control line inductively coupled to an input signal line on which an input analog signal is provided. The input signal line can be inductively coupled to the control line to propagate an induced input current that is based on the input analog signal on the control line. The system also includes at least one Josephson transmission line (JTL) stage that is biased via a DC bias current and is configured to generate an output pulse in response to the induced input current and the DC bias current exceeding a predetermined threshold current associated with the at least one JTL stage.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: February 25, 2020
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Micah John Atman Stoutimore, Timothy A. Manning, Mark E. Nowakowski, Alexander Marakov
  • Patent number: 10505097
    Abstract: A superconducting circuit is disclosed for fast digital readout of on-chip diagnostics in an array of devices in an integrated circuit. The digital readout comprises a digital RSFQ multiplexer to select the readout channel. This permits a large number of devices to be tested with a minimum of input and output lines. The devices may comprise digital devices (such as elementary RSFQ cells), or analog devices (such as inductors, resistors, or Josephson junctions) with a SQUID quantizer to generate a digital signal. The diagnostic array and the digital multiplexer are preferably configured to operate as part of the same integrated circuit at cryogenic temperatures.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: December 10, 2019
    Assignee: Hypres, Inc.
    Inventors: Amol Inamdar, Jie Ren, Denis Amparo
  • Patent number: 10490622
    Abstract: A semiconductor capacitor includes a semiconductor substrate, an electrode group formed on the semiconductor substrate, and a plurality of insulators sandwiched between the electrode groups to form a plurality of capacitors. At least one of the plurality of capacitors is set to be different from at least one of a tolerance, which is a capability of the capacitors to withstand a prescribed voltage, and a conductance, which is an ease with which a leakage current flows in the capacitors.
    Type: Grant
    Filed: August 5, 2016
    Date of Patent: November 26, 2019
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Yasuaki Hayami, Tetsuya Hayashi, Yusuke Zushi, Wei Ni, Akinori Okubo
  • Patent number: 10333507
    Abstract: A serializer device (1) includes a first latch unit (11), a second latch unit (12), a conversion unit (13), a frequency division unit (14), a load signal generation unit (15), a phase difference detection unit (16), and a reset instruction unit (17), and has a simple configuration and can reduce a bit error rate at an early stage. The phase difference detection unit (16) detects a phase difference between a first clock (CLK1) applied to the first latch unit (11) and a third clock (CLK3) applied to the second latch unit (12). The reset instruction unit (17) outputs a reset instruction signal (RSTn) to the frequency division unit (14) when the phase difference is not within a target range.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: June 25, 2019
    Assignee: THINE ELECTRONICS, INC.
    Inventors: Yusuke Fujita, Shunichi Kubo, Yoshinobu Oshima
  • Patent number: 10333049
    Abstract: A superconducting quantum interference devices (SQUID) comprises a superconducting inductive loop with at least two Josephson junction, whereby a magnetic flux coupled into the inductive loop produces a modulated response up through radio frequencies. Series and parallel arrays of SQUIDs can increase the dynamic range, output, and linearity, while maintaining bandwidth. Several approaches to achieving a linear triangle-wave transfer function are presented, including harmonic superposition of SQUID cells, differential serial arrays with magnetic frustration, and a novel bi-SQUID cell comprised of a nonlinear Josephson inductance shunting the linear coupling inductance. Total harmonic distortion of less than ?120 dB can be achieved in optimum cases.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: June 25, 2019
    Assignee: Hypres, Inc.
    Inventors: Victor K. Kornev, Igor I. Soloviev, Nikolai V. Klenov, Oleg A. Mukhanov
  • Patent number: 10320383
    Abstract: A technique relates to a lossless multiport device. The lossless multiport device includes a first port. A plurality of ports are operable to communicatively couple one at a time to the first port according to a pump drive.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 10298254
    Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 21, 2019
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY CHINA
    Inventors: Hua Fan, Jingxuan Yang, Quanyuan Feng, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari, Franco Maloberti, Jingtao Li, Huaying Su
  • Patent number: 10057527
    Abstract: An analog-digital converter may include a comparator suitable for comparing an input signal to a ramp signal to repetitively output a comparison signal a number of times corresponding to an analog gain for an analog-digital conversion; a counter receiving the repetitively outputted comparison signal from the comparator, the counter being suitable for performing a counting operation based on the repetitively outputted comparison signal; and a counting limiter suitable for limiting the counted number of bits by a maximum counted bit number of the counter.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 21, 2018
    Assignee: SK Hynix Inc.
    Inventors: Gun-Hee Yun, Hyun-Mook Park
  • Patent number: 9905295
    Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 27, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vikas Chandra, Brian Tracy Cline
  • Patent number: 9887700
    Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: February 6, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas Carmean, Alexander Braun, Anna Y. Herr, Quentin P. Herr
  • Patent number: 9799661
    Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Manfred Eller, Min-hwa Chi
  • Patent number: 9774338
    Abstract: The present invention relates to a digital-analog conversion method and device for adjusting a reference current to be used in a digital-analog conversion, by using a common mode feedback device, and the digital-analog conversion method of the present invention comprises the steps of: generating a reference current by receiving a reference voltage; converting a digital signal into an analog signal by receiving the generated reference current; detecting a common mode voltage, which is the average value of a both-end voltage of the converted analog signal; comparing the detected common mode voltage with the reference voltage; generating a feedback signal on the basis of the comparison result; and adjusting the reference current according to the generated feedback signal.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongwoo Lee, Thomas Byunghak Cho
  • Patent number: 9712182
    Abstract: A digital to analog conversion circuit, DAC, comprises a number of serializing lanes, each serializing lane comprising at least two bit inputs, and each serializing lane being configured to output the two bit inputs serially via a serialized output port at a predetermined first clock rate. The DAC further comprises a number of non-serializing lanes, each non-serializing lane comprising at least two bit inputs and each non-serializing lane being configured to output the two bit inputs in parallel each via a separate parallel output port, at a second clock rate, which is half the clock rate of the first clock rate, and a current switching network comprising a bit input port for every one of the serialized output ports and for every one of the parallel output ports and being configured to produce a output current, based on the signals received via the bit input ports.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: July 18, 2017
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Rich Huard
  • Patent number: 9618591
    Abstract: A magnetic resonance system, comprising at least one SQUID, configured to receive a radio frequency electromagnetic signal, in a circuit configured to produce a pulsatile output having a minimum pulse frequency of at least 1 GHz which is analyzed in a processor with respect to a timebase, to generate a digital signal representing magnetic resonance information. The processor may comprise at least one rapid single flux quantum circuit. The magnetic resonance information may be image information. A plurality of SQUIDs may be provided, fed by a plurality of antennas in a spatial array, to provide parallel data acquisition. A broadband excitation may be provided to address a range of voxels per excitation cycle. The processor may digitally compensate for magnetic field inhomogeneities.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 11, 2017
    Assignee: Hypres, Inc.
    Inventors: Masoud Radparvar, Alan M. Kadin, Elie K. Track, Richard E. Hitt
  • Patent number: 9614510
    Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 4, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Venkatesh Srinivasan, Kun Shi, Victoria Wang, Nikolaus Klemmer
  • Patent number: 9543959
    Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 10, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas Carmean, Alexander Braun, Anna Y. Herr, Quentin P. Herr
  • Patent number: 9350376
    Abstract: A digital to analog converter (DAC) includes a thermometer coder that generates a plurality of micro-current source analog controls on a frame-by-frame or symbol-by-symbol basis and to process digital inputs from symbols or frames of data based on a thermometer coding to generate a plurality of micro-current source inputs. A plurality of micro-current sources generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls for a first symbol or frame of the plurality of symbols or frames of data. A summing circuit generates an analog output based a sum of the corresponding plurality of micro-current source outputs.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 24, 2016
    Assignee: BROADCOM CORPORATION
    Inventors: Ramon Alejandro Gomez, Thomas Joseph Kolze, Bruce Joseph Currivan
  • Patent number: 9311559
    Abstract: A device and method for the hardware detection of local edges in an image, comprised of a plurality of elemental cells for mixed signal processing, locally interconnected with each other, comprising in each cell a first switch configured to enable the pre-charging of a condenser at the supply voltage; and where once said condenser is pre-charged, it discharges via a second switch connected to a power source which varies in a monotonically increasing manner with the analog voltage representing the value of the pixel concerned; and where the value of the pixel is compared asynchronously with the neighboring pixels of the neighboring cells via two inverters, a digital NOR gate, a digital NAND gate, a third and fourth switch and a memory feature to store the result.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 12, 2016
    Assignees: Universidad de Sevilla, Consejo Superior de Investigaciones Cientificas (CSIC)
    Inventors: Jorge FernƔndez Berni, Ɓngel Rodrƭguez VƔzquez, Ricardo Carmona GalƔn
  • Patent number: 9174840
    Abstract: One embodiment describes an AC/DC converter system. The system includes a flux-shuttle loop that is inductively coupled with an AC input signal. The system also includes a plurality of Josephson junctions spaced about the flux shuttle loop that are configured to sequentially trigger in response to the AC input signal and to provide a single-flux quantum (SFQ) pulse that moves sequentially around the flux-shuttle loop that results in a DC output signal being provided through an output inductor.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: November 3, 2015
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Quentin P. Herr, Anna Y. Herr
  • Patent number: 8872690
    Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: October 28, 2014
    Assignee: Hypres, Inc.
    Inventors: Amol Inamdar, Deepnarayan Gupta
  • Patent number: 8810440
    Abstract: A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Southeast University
    Inventors: Jianhui Wu, Zixuan Wang, Xiao Shi, Meng Zhang, Cheng Huang, Chao Chen, Fuqing Huang, Xincun Ji, Ping Jiang
  • Patent number: 8786476
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 22, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Patent number: 8611974
    Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: December 17, 2013
    Assignee: D-Wave Systems Inc.
    Inventors: Felix Maibaum, Paul I. Bunyk, Thomas Mahon
  • Patent number: 8547262
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 1, 2013
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette Elisabeth Jackson
  • Patent number: 8547264
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 1, 2013
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette Elisabeth Jackson
  • Patent number: 8547263
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 1, 2013
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette Elisabeth Jackson
  • Patent number: 8416109
    Abstract: A superconducting bandpass sigma-delta modulator and a method for analog-to-digital signal conversion is disclosed. The superconducting bandpass sigma-delta modulator includes coupled resonators having a desired impedance ratio. A first resonator connects to a comparator, which comparator generates single-flux-quantum pulses. A feedback loop links from the comparator to a second resonator and includes a current amplifier. A digital RF receiver system is also disclosed. This system includes a second order bandpass sigma-delta modulator, which has a desired impedance ratio between resonators and a feedback loop with current amplification. The system further has an antenna configured to receive a GHz frequency radio transmission and to yield an analog signal which is accepted by the sigma-delta modulator.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: April 9, 2013
    Assignee: HYPRES, Inc.
    Inventor: Dmitri Kirichenko
  • Patent number: 8330633
    Abstract: A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the ā€œsteeredā€ output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 11, 2012
    Assignee: Linear Technology Corporation
    Inventors: James L. Brubaker, Florin A. Oprescu
  • Publication number: 20120274494
    Abstract: A superconducting bandpass sigma-delta modulator and a method for analog-to-digital signal conversion is disclosed. The superconducting bandpass sigma-delta modulator includes coupled resonators having a desired impedance ratio. A first resonator connects to a comparator, which comparator generates single-flux-quantum pulses. A feedback loop links from the comparator to a second resonator and includes a current amplifier. A digital RF receiver system is also disclosed. This system includes a second order bandpass sigma-delta modulator, which has a desired impedance ratio between resonators and a feedback loop with current amplification. The system further has an antenna configured to receive a GHz frequency radio transmission and to yield an analog signal which is accepted by the sigma-delta modulator.
    Type: Application
    Filed: December 16, 2010
    Publication date: November 1, 2012
    Applicant: HYPRES, INC.
    Inventor: Dmitri Kirichenko
  • Patent number: 8188901
    Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: May 29, 2012
    Assignee: Hypres, Inc.
    Inventors: Amol Inamdar, Deepnarayan Gupta
  • Patent number: 8188897
    Abstract: An analog to digital converter includes a dielectric substrate, an analog input wire, and digital output wires, with a metal insulator extending over the digital output wires. The analog input wire can be in proximity to the dielectric substrate and can generate heat when an electric current flows through the analog input wire. The digital output wires can also be in proximity to the dielectric substrate. The metal insulator can have a phase transition temperature above which the metal insulator is electrically conductive to short circuit at least one of the digital output wires in contact with a metal insulator portion above the phase transition temperature. The digital output wires can be arranged at predetermined distances from the analog input wire such that output wires have varying short circuit thresholds.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: May 29, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John Paul Strachan, Philip J. Kuekes
  • Publication number: 20120092199
    Abstract: In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 19, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Marco Corsi, Robert F. Payne
  • Patent number: 8098179
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: January 17, 2012
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Patent number: 8050648
    Abstract: Digital mixers which permit mixing of asynchronous signals may be constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: November 1, 2011
    Assignee: Hypres, Inc.
    Inventors: Alexander F. Kirichenko, Deepnarayan Gupta, Saad Sarwana
  • Patent number: 8035540
    Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: October 11, 2011
    Assignee: D-Wave Systems Inc.
    Inventors: Andrew J. Berkley, Paul I. Bunyk, Geordie Rose
  • Patent number: 7994955
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: August 9, 2011
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette E. Jackson
  • Patent number: 7982646
    Abstract: A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: July 19, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Quentin P. Herr, Aaron A. Pesetski, John X. Przybysz, Donald L. Miller
  • Patent number: 7973691
    Abstract: A data recovery circuit includes an analog-digital converter creating a digital code sequence, a phase detector calculating a position of a crossing point from the digital code sequence, a phase estimator acquiring a presumed position of a data center point of a data sequence based on the position of the crossing point, and a data determining circuit extracting the sequence of data determination values from the digital code sequence based on the position of the crossing point and the presumed position of the data center point.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: July 5, 2011
    Assignee: Fujitsu Limited
    Inventors: Hisakatsu Yamaguchi, Hirotaka Tamura, Masaya Kibune
  • Patent number: 7952503
    Abstract: A voltage following device is described, for the driving of a sampling network coupleable to an analog/digital converter, comprising at least one first transistor provided with a first terminal to receive an input signal, and a second terminal to provide an output signal to the sampling network which is representative of the input signal translation of an amount equal to a gate and source voltage of said at least one first transistor. The voltage following device having a driving network of said at least one first transistor to keep said gate and source voltage equal to a shift reference voltage.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: May 31, 2011
    Assignee: ST-Ericsson SA
    Inventors: Andrea Barbieri, Germano Nicollini
  • Patent number: 7928875
    Abstract: A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an Nth-order bandpass sigma-delta ADC, with the order ā€œNā€ being at least 2. The ADC includes a sequence of stages, which stages include feedback loops and resonators. The ADC further includes active superconducting components which directionally couple resonator pairs of adjacent stages. The active superconducting components electrically shield the higher order resonator from the lower order resonator. These active superconductor components include a superconducting quantum interference device (SQUID) amplifier, which is inductively coupled to the higher order resonator, and may include a Josephson transmission line (JTL), which is configured to electrically connect the SQUID amplifier to the lower order resonator. The first stage of ADC may employ an implicit feedback loop.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: April 19, 2011
    Assignee: Hypres, Inc.
    Inventor: Dmitri Kirichenko