With Particular Solid State Devices (e.g., Gunn Effect Device, Josephson Device, Drift Transistor, Using Solid State Active Devices As Impedances) With Other At Longer Intervals) Patents (Class 341/133)
  • Patent number: 10320383
    Abstract: A technique relates to a lossless multiport device. The lossless multiport device includes a first port. A plurality of ports are operable to communicatively couple one at a time to the first port according to a pump drive.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: June 11, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Baleegh Abdo
  • Patent number: 10298254
    Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: May 21, 2019
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY CHINA
    Inventors: Hua Fan, Jingxuan Yang, Quanyuan Feng, Dagang Li, Daqian Hu, Yuanjun Cen, Hadi Heidari, Franco Maloberti, Jingtao Li, Huaying Su
  • Patent number: 10057527
    Abstract: An analog-digital converter may include a comparator suitable for comparing an input signal to a ramp signal to repetitively output a comparison signal a number of times corresponding to an analog gain for an analog-digital conversion; a counter receiving the repetitively outputted comparison signal from the comparator, the counter being suitable for performing a counting operation based on the repetitively outputted comparison signal; and a counting limiter suitable for limiting the counted number of bits by a maximum counted bit number of the counter.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: August 21, 2018
    Assignee: SK Hynix Inc.
    Inventors: Gun-Hee Yun, Hyun-Mook Park
  • Patent number: 9905295
    Abstract: A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a plurality of impedance states. Further, a programing circuit is provided. The programing circuit provides a plurality of programing signals in dependence of an input signal. Each programing signal configures an impedance state of a respective CES from the plurality of CESs.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: February 27, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Vikas Chandra, Brian Tracy Cline
  • Patent number: 9887700
    Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.
    Type: Grant
    Filed: November 26, 2016
    Date of Patent: February 6, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas Carmean, Alexander Braun, Anna Y. Herr, Quentin P. Herr
  • Patent number: 9799661
    Abstract: Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 24, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Hui Zang, Manfred Eller, Min-hwa Chi
  • Patent number: 9774338
    Abstract: The present invention relates to a digital-analog conversion method and device for adjusting a reference current to be used in a digital-analog conversion, by using a common mode feedback device, and the digital-analog conversion method of the present invention comprises the steps of: generating a reference current by receiving a reference voltage; converting a digital signal into an analog signal by receiving the generated reference current; detecting a common mode voltage, which is the average value of a both-end voltage of the converted analog signal; comparing the detected common mode voltage with the reference voltage; generating a feedback signal on the basis of the comparison result; and adjusting the reference current according to the generated feedback signal.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: September 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jongwoo Lee, Thomas Byunghak Cho
  • Patent number: 9712182
    Abstract: A digital to analog conversion circuit, DAC, comprises a number of serializing lanes, each serializing lane comprising at least two bit inputs, and each serializing lane being configured to output the two bit inputs serially via a serialized output port at a predetermined first clock rate. The DAC further comprises a number of non-serializing lanes, each non-serializing lane comprising at least two bit inputs and each non-serializing lane being configured to output the two bit inputs in parallel each via a separate parallel output port, at a second clock rate, which is half the clock rate of the first clock rate, and a current switching network comprising a bit input port for every one of the serialized output ports and for every one of the parallel output ports and being configured to produce a output current, based on the signals received via the bit input ports.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: July 18, 2017
    Assignee: ROHDE & SCHWARZ GMBH & CO. KG
    Inventor: Rich Huard
  • Patent number: 9618591
    Abstract: A magnetic resonance system, comprising at least one SQUID, configured to receive a radio frequency electromagnetic signal, in a circuit configured to produce a pulsatile output having a minimum pulse frequency of at least 1 GHz which is analyzed in a processor with respect to a timebase, to generate a digital signal representing magnetic resonance information. The processor may comprise at least one rapid single flux quantum circuit. The magnetic resonance information may be image information. A plurality of SQUIDs may be provided, fed by a plurality of antennas in a spatial array, to provide parallel data acquisition. A broadband excitation may be provided to address a range of voxels per excitation cycle. The processor may digitally compensate for magnetic field inhomogeneities.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: April 11, 2017
    Assignee: Hypres, Inc.
    Inventors: Masoud Radparvar, Alan M. Kadin, Elie K. Track, Richard E. Hitt
  • Patent number: 9614510
    Abstract: System and methods for input path matching in pipelined continuous-time Analog-to Digital Converters (ADCs), including pipelined Continuous-Time Delta Sigma Modulator (CTDSM) based ADCs, includes an input delay circuit disposed in a continuous-time input path from an input of an analog input signal to a first summing circuit of the continuous-time ADC. At least one digital delay line is disposed between an output of an earlier stage sub-ADC (of a plurality of pipelined sub-ADCs) and a sub-digital-to-analog converter (DAC) that is coupled to the first summing circuit, and between the earlier stage sub-ADC and a digital noise cancellation filter. The digital delay line(s) is configured to enable calibration of delay of output of the earlier stage sub-ADC provided to the sub-DAC and the digital noise cancellation filter in accordance with process variations of the input delay match circuit to minimize residue output at first summing circuit.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: April 4, 2017
    Assignee: Texas Instruments Incorporated
    Inventors: Venkatesh Srinivasan, Kun Shi, Victoria Wang, Nikolaus Klemmer
  • Patent number: 9543959
    Abstract: A device including Josephson junctions, and a terminal for receiving a sinusoidal clock signal for providing power to the Josephson junctions, is provided. The device further includes a terminal for receiving an input signal, a clock terminal for receiving a return-to-zero clock signal, and at least one latch. The device also includes at least one logic gate including at least a subset of the Josephson junctions, for processing the input signal and the return-to-zero clock signal to generate a first signal for the at least one latch. Additionally, the device includes at least one phase-mode logic inverter for processing the return-to-zero clock signal to generate a second signal for the at least one latch. The device also includes an output terminal for providing an output of the at least one latch by processing the first signal and the second signal.
    Type: Grant
    Filed: October 21, 2015
    Date of Patent: January 10, 2017
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Douglas Carmean, Alexander Braun, Anna Y. Herr, Quentin P. Herr
  • Patent number: 9350376
    Abstract: A digital to analog converter (DAC) includes a thermometer coder that generates a plurality of micro-current source analog controls on a frame-by-frame or symbol-by-symbol basis and to process digital inputs from symbols or frames of data based on a thermometer coding to generate a plurality of micro-current source inputs. A plurality of micro-current sources generate a corresponding plurality of micro-current source outputs in response to the plurality of micro-current source inputs, wherein first selected ones of the plurality of micro-current sources are powered-off in response to the plurality of micro-current source analog controls for a first symbol or frame of the plurality of symbols or frames of data. A summing circuit generates an analog output based a sum of the corresponding plurality of micro-current source outputs.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: May 24, 2016
    Assignee: BROADCOM CORPORATION
    Inventors: Ramon Alejandro Gomez, Thomas Joseph Kolze, Bruce Joseph Currivan
  • Patent number: 9311559
    Abstract: A device and method for the hardware detection of local edges in an image, comprised of a plurality of elemental cells for mixed signal processing, locally interconnected with each other, comprising in each cell a first switch configured to enable the pre-charging of a condenser at the supply voltage; and where once said condenser is pre-charged, it discharges via a second switch connected to a power source which varies in a monotonically increasing manner with the analog voltage representing the value of the pixel concerned; and where the value of the pixel is compared asynchronously with the neighboring pixels of the neighboring cells via two inverters, a digital NOR gate, a digital NAND gate, a third and fourth switch and a memory feature to store the result.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: April 12, 2016
    Assignees: Universidad de Sevilla, Consejo Superior de Investigaciones Cientificas (CSIC)
    Inventors: Jorge Fernández Berni, Ángel Rodríguez Vázquez, Ricardo Carmona Galán
  • Patent number: 9174840
    Abstract: One embodiment describes an AC/DC converter system. The system includes a flux-shuttle loop that is inductively coupled with an AC input signal. The system also includes a plurality of Josephson junctions spaced about the flux shuttle loop that are configured to sequentially trigger in response to the AC input signal and to provide a single-flux quantum (SFQ) pulse that moves sequentially around the flux-shuttle loop that results in a DC output signal being provided through an output inductor.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: November 3, 2015
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Quentin P. Herr, Anna Y. Herr
  • Patent number: 8872690
    Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: October 28, 2014
    Assignee: Hypres, Inc.
    Inventors: Amol Inamdar, Deepnarayan Gupta
  • Patent number: 8810440
    Abstract: A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: August 19, 2014
    Assignee: Southeast University
    Inventors: Jianhui Wu, Zixuan Wang, Xiao Shi, Meng Zhang, Cheng Huang, Chao Chen, Fuqing Huang, Xincun Ji, Ping Jiang
  • Patent number: 8786476
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: July 22, 2014
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Patent number: 8611974
    Abstract: A switching cell for a demultiplexer circuit includes a superconducting input signal path, at least two superconducting output signal paths, and transformers located between an intersection node and respective ends of the output signal paths. Flux applied via the transformers can influence which direction a signal propagates. The switching cell may also include power input nodes. Switching cells may be arranged in various configurations, for example a binary tree or H-tree. A superconducting inductor ladder circuit can perform a digital-to-analog conversion. Flux storage structures may be used with individual switching cells. Latching qubits may be employed. Buffer rows of switching cells may be used to reduce or eliminate cascade error.
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: December 17, 2013
    Assignee: D-Wave Systems Inc.
    Inventors: Felix Maibaum, Paul I. Bunyk, Thomas Mahon
  • Patent number: 8547263
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 1, 2013
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette Elisabeth Jackson
  • Patent number: 8547264
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 1, 2013
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette Elisabeth Jackson
  • Patent number: 8547262
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: October 1, 2013
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette Elisabeth Jackson
  • Patent number: 8416109
    Abstract: A superconducting bandpass sigma-delta modulator and a method for analog-to-digital signal conversion is disclosed. The superconducting bandpass sigma-delta modulator includes coupled resonators having a desired impedance ratio. A first resonator connects to a comparator, which comparator generates single-flux-quantum pulses. A feedback loop links from the comparator to a second resonator and includes a current amplifier. A digital RF receiver system is also disclosed. This system includes a second order bandpass sigma-delta modulator, which has a desired impedance ratio between resonators and a feedback loop with current amplification. The system further has an antenna configured to receive a GHz frequency radio transmission and to yield an analog signal which is accepted by the sigma-delta modulator.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: April 9, 2013
    Assignee: HYPRES, Inc.
    Inventor: Dmitri Kirichenko
  • Patent number: 8330633
    Abstract: A differential current steering (CS) circuit uses feedback from the differential output nodes A and B to cause current steering devices (e.g., MOSFETs) to effectively exhibit an infinite output impedance when conducting. Therefore, the signal on the output nodes A or B does not significantly change the voltage at the common node, This is particularly useful when the differential output nodes are connected to differential output buses in a digital-to-analog converter. The circuit dynamically cancels, though feedback, the signal induced at the common node by the signal present at the “steered” output node. Therefore, the CS circuit effectively presents an infinite output impedance between the common node and the output nodes. In some cases, it may be desirable to not create a substantially infinite output impedance for the CS circuit but control the impedance to a predefined level to counter other distortions in the system.
    Type: Grant
    Filed: April 28, 2011
    Date of Patent: December 11, 2012
    Assignee: Linear Technology Corporation
    Inventors: James L. Brubaker, Florin A. Oprescu
  • Publication number: 20120274494
    Abstract: A superconducting bandpass sigma-delta modulator and a method for analog-to-digital signal conversion is disclosed. The superconducting bandpass sigma-delta modulator includes coupled resonators having a desired impedance ratio. A first resonator connects to a comparator, which comparator generates single-flux-quantum pulses. A feedback loop links from the comparator to a second resonator and includes a current amplifier. A digital RF receiver system is also disclosed. This system includes a second order bandpass sigma-delta modulator, which has a desired impedance ratio between resonators and a feedback loop with current amplification. The system further has an antenna configured to receive a GHz frequency radio transmission and to yield an analog signal which is accepted by the sigma-delta modulator.
    Type: Application
    Filed: December 16, 2010
    Publication date: November 1, 2012
    Applicant: HYPRES, INC.
    Inventor: Dmitri Kirichenko
  • Patent number: 8188897
    Abstract: An analog to digital converter includes a dielectric substrate, an analog input wire, and digital output wires, with a metal insulator extending over the digital output wires. The analog input wire can be in proximity to the dielectric substrate and can generate heat when an electric current flows through the analog input wire. The digital output wires can also be in proximity to the dielectric substrate. The metal insulator can have a phase transition temperature above which the metal insulator is electrically conductive to short circuit at least one of the digital output wires in contact with a metal insulator portion above the phase transition temperature. The digital output wires can be arranged at predetermined distances from the analog input wire such that output wires have varying short circuit thresholds.
    Type: Grant
    Filed: October 29, 2010
    Date of Patent: May 29, 2012
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: John Paul Strachan, Philip J. Kuekes
  • Patent number: 8188901
    Abstract: Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.
    Type: Grant
    Filed: August 17, 2009
    Date of Patent: May 29, 2012
    Assignee: Hypres, Inc.
    Inventors: Amol Inamdar, Deepnarayan Gupta
  • Publication number: 20120092199
    Abstract: In conventional pipelined analog-to-digital converters (ADCs), it is common to employ digital-to-analog converters (DACs) in the ADC stages that use two-state switches or segments. A problem with this arrangement is that for each DAC state there is a noise contribution from each DAC switch, resulting from its current source. Here, however, a DAC is employed that uses three-state DAC switches, which reduces the noise contributions from the DAC switches' current sources and reduces the amount of area used.
    Type: Application
    Filed: October 14, 2010
    Publication date: April 19, 2012
    Applicant: Texas Instruments Incorporated
    Inventors: Marco Corsi, Robert F. Payne
  • Patent number: 8098179
    Abstract: A superconducting flux digital-to-analog converter includes a superconducting inductor ladder circuit. The ladder circuit includes a plurality of closed superconducting current paths that each includes at least two superconducting inductors coupled in series to form a respective superconducting loop, successively adjacent or neighboring superconducting loops are connected in parallel with each other and share at least one of the superconducting inductors to form a flux divider network. A data signal input structure provides a respective bit of a multiple bit signal to each of the superconducting loops. The data signal input structure may include a set of superconducting quantum interference devices (SQUIDs). The data signal input structure may include a superconducting shift register, for example a single-flux quantum (SFQ) shift register or a flux-based superconducting shift register comprising a number of latching qubits.
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: January 17, 2012
    Assignee: D-Wave Systems Inc.
    Inventors: Paul I. Bunyk, Felix Maibaum, Andrew J. Berkley, Thomas Mahon
  • Patent number: 8050648
    Abstract: Digital mixers which permit mixing of asynchronous signals may be constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: November 1, 2011
    Assignee: Hypres, Inc.
    Inventors: Alexander F. Kirichenko, Deepnarayan Gupta, Saad Sarwana
  • Patent number: 8035540
    Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: October 11, 2011
    Assignee: D-Wave Systems Inc.
    Inventors: Andrew J. Berkley, Paul I. Bunyk, Geordie Rose
  • Patent number: 7994955
    Abstract: The invention provides a system of generation of multi-channel analog output signals, from a single analog input signal, and the controlled activation of peripheral devices responsive to the multi-channel analog output signals. A single-channel to multi-channel analog-to-analog converter is provided to convert the single analog input signal to multiple output channels. Uni-directional coupling is used for coupling and mixing the multi-channel outputs and transferring the mixed outputs to a data bus. Signals on the data bus are used to drive the multiple peripheral devices.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: August 9, 2011
    Assignee: Light-Based Technologies Incorporated
    Inventors: Verne S. Jackson, Jeanette E. Jackson
  • Patent number: 7982646
    Abstract: A second order superconductor delta-sigma analog-to-digital modulator having an input for receiving an analog signal, a first integrator coupled to the input, a second integrator cascaded with the first integrator, and a quantum comparator digitizing output from the second integrator reduces quantization noise by providing matched quantum accurate DACs in a feedback loop between output from the quantum comparator and input to the first integrator. The matched quantum accurate feedback DACs produce identically repeatable voltage pulses, may be configured for multi-bit output, may be time-interleaved to permit higher clocking rates, and may be employed in a balanced bipolar configuration to allow inductive input coupling. Bipolar feedback is balanced when gain of a first DAC exceeds gain of a matched, opposite polarity DAC by the amount of implicit feedback from the comparator into the second integrator.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: July 19, 2011
    Assignee: Northrop Grumman Systems Corporation
    Inventors: Quentin P. Herr, Aaron A. Pesetski, John X. Przybysz, Donald L. Miller
  • Patent number: 7973691
    Abstract: A data recovery circuit includes an analog-digital converter creating a digital code sequence, a phase detector calculating a position of a crossing point from the digital code sequence, a phase estimator acquiring a presumed position of a data center point of a data sequence based on the position of the crossing point, and a data determining circuit extracting the sequence of data determination values from the digital code sequence based on the position of the crossing point and the presumed position of the data center point.
    Type: Grant
    Filed: November 19, 2009
    Date of Patent: July 5, 2011
    Assignee: Fujitsu Limited
    Inventors: Hisakatsu Yamaguchi, Hirotaka Tamura, Masaya Kibune
  • Patent number: 7952503
    Abstract: A voltage following device is described, for the driving of a sampling network coupleable to an analog/digital converter, comprising at least one first transistor provided with a first terminal to receive an input signal, and a second terminal to provide an output signal to the sampling network which is representative of the input signal translation of an amount equal to a gate and source voltage of said at least one first transistor. The voltage following device having a driving network of said at least one first transistor to keep said gate and source voltage equal to a shift reference voltage.
    Type: Grant
    Filed: June 15, 2009
    Date of Patent: May 31, 2011
    Assignee: ST-Ericsson SA
    Inventors: Andrea Barbieri, Germano Nicollini
  • Patent number: 7928875
    Abstract: A superconducting Analog-to-Digital Converter (ADC) employing rapid-single-flux-quantum (RSFQ) logic is disclosed. The ADC has only superconductor active components, and is characterized as being an Nth-order bandpass sigma-delta ADC, with the order “N” being at least 2. The ADC includes a sequence of stages, which stages include feedback loops and resonators. The ADC further includes active superconducting components which directionally couple resonator pairs of adjacent stages. The active superconducting components electrically shield the higher order resonator from the lower order resonator. These active superconductor components include a superconducting quantum interference device (SQUID) amplifier, which is inductively coupled to the higher order resonator, and may include a Josephson transmission line (JTL), which is configured to electrically connect the SQUID amplifier to the lower order resonator. The first stage of ADC may employ an implicit feedback loop.
    Type: Grant
    Filed: August 26, 2009
    Date of Patent: April 19, 2011
    Assignee: Hypres, Inc.
    Inventor: Dmitri Kirichenko
  • Patent number: 7924196
    Abstract: A parallel digital-analog converter for the conversion of a plurality of differential digital input signals into a differential analog output signal, including a group of 1-bit digital-analog converters (200) which respectively include an intermediate storage cell (202) and a current cell (201) and which are adapted to feed a respective output current to a first (204) or a second output contact (206) in dependence on a logic state of the intermediate storage cell, wherein a first of two outputs of an intermediate storage cell (202) is connected by way of an input resistor (220) to a first signal terminal (208.1) of a first transistor (208) and a second of the two outputs of the intermediate storage cell (202) is connected by way of an input resistor (218) to a first signal terminal (210.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: April 12, 2011
    Assignee: IHP GmbH Innovations for High Performance Microelectronics/Leibniz Institut for Innovative Mikroelektronik
    Inventor: Hans Gustat
  • Patent number: 7917798
    Abstract: An important component in digital circuits is a phase rotator, which permits precise time-shifting (or equivalently, phase rotation) of a clock signal within a clock period. A digital phase rotator can access multiple discrete values of phase under digital control. Such a device can have application in digital clock synchronization circuits, and can also be used for a digital phase modulator that encodes a digital signal. A digital phase rotator has been implemented in superconducting integrated circuit technology, using rapid single-flux-quantum logic (RSFQ). This circuit can exhibit positive or negative phase shifts of a multi-phase clock. Arbitrary precision can be obtained by cascading a plurality of phase rotator stages. Such a circuit forms a phase-modulator that is the core of a direct digital synthesizer that can operate at multi-gigahertz radio frequencies.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: March 29, 2011
    Assignee: Hypres, Inc.
    Inventor: Amol Ashok Inamdar
  • Publication number: 20110057823
    Abstract: An asynchronous analog to digital convertor for converting an analog input signal into a digital output is presented. According to an embodiment, the analog to digital convertor comprises a clock input operable to receive an external clock signal having a clock period, a comparator operable to compare the analog input signal to a reference signal, a digital to analog converter operable to generate the reference signal corresponding to a state of a successive approximation register, and a control block connected to the comparator and to the digital to analog converter. The control block is operable to generate and receive a sequence of control signals according to a successive approximation algorithm, to perform a plurality of comparisons, and to update the state of the successive approximation register thereby generating the digital output.
    Type: Application
    Filed: September 9, 2010
    Publication date: March 10, 2011
    Applicant: STICHTING IMEC NEDERLAND
    Inventor: Pieter Harpe
  • Patent number: 7876248
    Abstract: Systems, methods and apparatus for a scalable quantum processor architecture. A quantum processor is locally programmable by providing a memory register with a signal embodying device control parameter(s), converting the signal to an analog signal; and administering the analog signal to one or more programmable devices.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: January 25, 2011
    Assignee: D-Wave Systems Inc.
    Inventors: Andrew J. Berkley, Paul I. Bunyk, Geordie Rose
  • Publication number: 20100245142
    Abstract: Systems and methods using the same to achieve a tri-level multi-bit delta-sigma DAC having reduced power consumption and voltage droop have been achieved. A new rotation-based first order noise-shaping Dynamic Element Matcher (DEM) technique for use with 3-level unit elements have been disclosed. Reduced reference loading has been achieved when the tri-level DEM scheme is applied to switched capacitor implementations in particular. Furthermore a differential switched-capacitor DAC implementation, which enables use of the DEM technique is disclosed. The invention allows reduced circuit complexity required to implement a N-bit DAC when constructed using 3-level unit elements.
    Type: Application
    Filed: April 1, 2009
    Publication date: September 30, 2010
    Inventors: Andrew Myles, Andrew Terry
  • Patent number: 7750715
    Abstract: A clock generation circuit has two output ends to provide a first clock signal and a second clock signal, in response to first and second input signals, respectively. A charge storage component is used to transfer some charge from the first output end to the charge storage component when the first clock signal is high for a period of time, and to transfer the charge from the charge storage component to the second output end when the second clock signal is low. At a different period of time in the clock cycle, the charge storage component is used to transfer some charge from the second output end to the charge storage component when the second clock signal is high for a period of time, and to transfer the charge from the charge storage component to the first output end when the first clock signal is low.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: July 6, 2010
    Assignee: AU Optronics Corporation
    Inventors: Chao-Ching Hsu, Mu-Lin Tung, Chung-Shen Cheng
  • Publication number: 20100164770
    Abstract: An Analog-to-Digital Converter (ADC) has a Successive-Approximation-Register (SAR) driving a digital-to-analog converter (DAC) that generates an analog voltage compared to an input voltage by a series of stages. The last stage feeds a compare signal to the SAR. Each stage has a dual-input differential amplifier that operates as a unity gain op amp during an auto-zeroing phase and as a high-speed low-gain amplifier during an amplifying phase. The dual-input differential amplifier has two pairs of differential inputs. A secondary pair has an offset-storing capacitor across it, and connects to the output pair through feedback switches during auto-zeroing. A primary pair connects to stage inputs through input switches during the amplifying phase. Since two pairs of differential inputs are provided to the dual-input differential amplifier, the offset capacitor is completely isolated from the input pair. The current sink in the dual-input differential amplifier is adjusted higher during the amplifying period.
    Type: Application
    Filed: December 31, 2008
    Publication date: July 1, 2010
    Applicant: Hong Kong Applied Science & Technology Research Institute Company Limited
    Inventors: Ho Ming (Karen) Wan, Yat To (William) Wong, Kwai Chi Chan, Kwok Kuen Kwong
  • Publication number: 20100149011
    Abstract: A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an Nth-order, having N resonators, with N being at least 2. The ADC also may have N-1 amplifiers, where the amplifiers directionally couple sequential pairs of the resonators. The ADC further includes a Josephson Junction (JJ) comparator. All N resonators connect in parallel to the JJ comparator, and the JJ comparator is providing an implicit feedback for all N resonators. A method for implementing the sigma-delta ADC without any explicit feedback loops is also disclosed.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Applicant: HYPRES, INC.
    Inventor: Dmitri Kirichenko
  • Patent number: 7733253
    Abstract: A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: June 8, 2010
    Assignee: HYPRES, Inc.
    Inventor: Dmitri Kirichenko
  • Patent number: 7728748
    Abstract: A superconducting bandpass sigma-delta Analog-to-Digital Converter (ADC) is disclosed. The ADC is characterized as being an Nth-order, having N resonators, with N being at least 2. The ADC also may have N?1 amplifiers, where the amplifiers directionally couple sequential pairs of the resonators. The ADC further includes a Josephson Junction (JJ) comparator. All N resonators connect in parallel to the JJ comparator, and the JJ comparator is providing an implicit feedback for all N resonators. A method for implementing the sigma-delta ADC without any explicit feedback loops is also disclosed.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: June 1, 2010
    Assignee: HYPRES, Inc.
    Inventor: Dmitri Kirichenko
  • Patent number: 7719453
    Abstract: The present invention relates to an analog-to-digital converter (ADC) and an analog-to-digital conversion method employing a Josephson digital-to-analog converter (DAC) into an extremely accurate ADC of a physical metrology grade. The ADC includes: a front end ADC for converting an analog input signal into digital data; the Josephson DAC for receiving the digital data from the front end ADC and converting the received digital data into reference analog voltage; a differential ADC for extracting a difference voltage between a reference analog voltage of the Josephson DAC and an unknown input signal; and a data processor for summing output data of the differential ADC and output data of the front end ADC and outputting the summed result.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: May 18, 2010
    Assignee: Korea Research Institute of Standards and Science
    Inventors: Kyu Tae Kim, Mun Seog Kim, Yon Uk Chong
  • Publication number: 20100117880
    Abstract: An improvement in sampling a high frequency input analog signal and converting it to a digital output signal is disclosed. This is accomplished by using a multitude of analog-to-digital converters in conjunction with a distributed sampling system. This combination of multiple converters and a distributed sampling system allows use of conventional device processing, such as that of 0.18 micron silicon, and also provides accurate sampling of very high frequency input signals. The distributed sampling system provides multiple samplings of the input signal by using multiple ADCs for multiple samplings, wherein each sampling is sequentially offset a fixed amount of time from the most recent preceding sampling. Each ADC has a designated central processing unit (CPU) to obtain sufficient data transfer capabilities. The samplings from the multitude of ADCs are a series of sequential digital output values.
    Type: Application
    Filed: August 10, 2009
    Publication date: May 13, 2010
    Inventors: Charles H. Moore, Leslie O. Snively, John Huie
  • Patent number: 7683813
    Abstract: A current cell matrix type of digital-to-analog (D/A) converter to prevent deterioration of a.c. characteristics on a current path for digital-to-analog conversion includes a array of current source cells arranged in a matrix configuration. Each current source cell includes a current source transistor to generate the cell current. During the regular operation, the cell current is flowed on output lines via a first transistor connected in cascode to the current source transistor. During the calibration operation, the cell current is flowed into a current comparator via a second transistor connected in cascode to the current source transistor. This prevents parasitic capacitance from being additively caused in switches for the first transistor and in another switch for the second transistor to prevent deterioration of a.c. characteristics on the current path.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: March 23, 2010
    Assignee: Oki Semiconductor Co., Ltd.
    Inventor: Danya Sugai
  • Publication number: 20100066576
    Abstract: A superconductor multi-level quantizer is disclosed, which quantizer includes a number N of Josephson junction (JJ) comparators connected in parallel to a common input node. The quantizer further includes at least one flux bias device. Each flux bias device is capable to adjust the flux threshold for at least one of the JJ comparators. The quantizer is so configured a feedback current from the output is capable to shift the flux threshold for each of the JJ comparators.
    Type: Application
    Filed: September 17, 2008
    Publication date: March 18, 2010
    Applicant: HYPRES, INC.
    Inventor: Dmitri Kirichenko
  • Patent number: 7680474
    Abstract: Digital mixers which permit mixing of asynchronous signals are constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), an RSFQ D flip-flop, an RSFQ XOR circuit, and an RSFQ T flip-flop. A binary tree arrangement of T flip-flops can be used to provide in-phase and quadrature phase-divided replicas of a reference signal. The mixing elements can be either an XOR circuit, a dual port NDRO circuit functioning as a multiplexer or an RS type NDRO functioning as an AND gate. The RSFQ logic elements utilize Josephson junctions which operate in superconducting temperature domains.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: March 16, 2010
    Assignee: Hypres Inc.
    Inventors: Alexander F. Kirichenko, Deepnarayan Gupta, Saad Sarwana