Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: A data readout system with non-uniform resolution has a pick up head for reading data stored in an optical disc and generating an analog signal, a reference voltage unit for producing a plurality of reference voltage levels, wherein voltage differences between two adjacent reference voltage levels are not all the same, a plurality of comparators for comparing the reference voltage levels with the analog signal and generating comparison results, and an encoder for encoding the comparison results into a digital signal.

Abstract: Embodiments of the invention relate to a method and a corresponding circuit for digitizing an analog signal. Applying a nonlinear function to the signal, digitizing the signal and applying the inverse of the nonlinear function to the digital samples improve the digital samples.

Abstract: A selection circuit receives a plural number (m) of respective different values of voltages as reference voltages to select and output two voltages. An amplifier receives at two input terminals the two reference voltages output from the selection circuit to output an output voltage extrapolated.

Abstract: A method is provided to produce an error corrected digital output from a temperature measurement system that generates digital outputs representative of the output of one or more temperature sensors. In an embodiment of the invention the method comprises: storing in a plurality of memory locations corresponding error correction data, with each memory location having a correlation to a corresponding range of the digital outputs; utilizing each digital output to identify a corresponding one of the memory locations; accessing the corresponding one memory location to obtain error correction data specific to the digital output; and utilizing the error correction data specific to the digital output to correct the digital output, whereby an error corrected digital output is generated.

Abstract: Embodiments of a digital-to-analog converter (DAC) with a logarithmic response and methods for converting digital signals to analog are generally described herein. Other embodiments may be described and claimed. In some embodiments, the DAC includes a wedge-shaped resistive array having a plurality of linearly-spaced contact nodes and a switching array to selectively couple one of the contact nodes with an analog output based on a control signal. Each of the contact nodes may provide a corresponding reference voltage that varies logarithmically with respect to the linearly-spaced contact nodes.

Abstract: Circuitry for providing non-uniform analog-to-digital (“A/D”) signal conversion for wideband signals is provided. The circuitry of the invention is optimized for wideband signals because it does not sacrifice the small-scale resolution of high-probability signal amplitudes while preventing the clipping of low-probability signal amplitudes. The circuitry includes a nonlinear amplifier and an A/D converter that may be uniform or non-uniform. The digital output of the A/D converter may be further processed by circuitry that has an output function that is the inverse of that of the nonlinear amplifier, so as to maintain linear A/D conversion.

Abstract: An integrated circuit includes a comparator having a first input, a second input, and an output for providing a comparison result. The first input is connected to a readable component having a predefined value, and the second input is connected to a reference component. A control unit is at the output of the comparator. The control unit controls at least one function block based on the comparison result.

Abstract: A system for making a pulse domain linear programming circuit. The inputs and the outputs to the pulse domain linear programming circuit are time encoded pulse signals. The circuit includes arrays of two types of cross-coupled time encoding elements. The first type of elements includes two integrators, adders, a hysteresis quantizer, and a 1-bit self-feedback DAC. The second type of elements includes a bias element, a leaky integrator, adders, a fixed memory-less non-linearity, a regular integrator, a hysteresis quantizer and a 1-bit self-feedback DAC. The cross-coupling signals between the two types of elements are pulse time-encoded signals. All of the cross-coupling weights are set via 1-bit DACs having variable gains. The cross-coupling weights are used to set a constraint equation of a pulse domain linear programming problem. Methods to make the foregoing circuit are also described.

Abstract: A method for detecting saturation in a cascaded ?? ADC can include receiving an output of the cascaded ?? ADC, determining a magnitude of the output, and squaring the magnitude. The squared magnitude can be added to a feedback signal, wherein the sum represents a saturation signal. The saturation signal can be filtered and then amplified, wherein the amplified, filtered saturation signal is the feedback signal. The saturation signal can then be compared to a threshold to determine whether the cascaded ?? ADC is in saturation.

Abstract: The management of unit element selections in a system that includes multiple unit elements. The system includes an element selection component that is configured so that each of the multiple elements is used the same number of times over a certain number of selection cycles. This preserves the first order noise shaping of the mismatch noise thereby keeping a high signal to noise ratio. In addition, the selection of the unit elements is not done in a periodic fashion. This allows the system to avoid tones within the signal band.

Abstract: A gamma reference voltages generating circuit is disclosed in the present invention. The gamma reference voltages generating circuit comprises a voltage provider, a plurality of first digital-to-analog converters and a plurality of second digital-to-analog converters. The voltage provider generates a plurality of first supply voltages and a plurality of second supply voltages according to a first gamma reference voltage. The first digital-to-analog converters are electrically coupled to the first supply voltages for generating a plurality of second gamma reference voltages. The second digital-to-analog converters are electrically coupled to the second supply voltages for generating a plurality of third gamma reference voltages.

Abstract: An adjustable analog-digital converter arrangement comprising: an input adapted for receiving an input signal; an analog-digital converter operating by successive approximation, having a signal input coupled with the input, wherein said converter is adapted for converting an analog signal at the signal input into a digital value; an attenuator with an output, wherein an input of said attenuator is coupled to the signal input and is adapted for an amplitude change of signals applied to its input, wherein the amplitude change is controllable by means of a control input, and wherein the attenuator comprises switchable capacitors and forms a part of a first stage of said analog-digital converter; a control circuit having an output coupled to the control input of the attenuator and adapted to initialize, as a function of a comparison of a signal output by the analog-digital converter with a threshold, an automatic adjustment of the attenuation by generating a control signal, and having an output for the output of

Abstract: An on die thermal sensor (ODTS) in a memory device includes: a band gap unit for detecting a temperature of the memory device to output a first voltage corresponding to the temperature; and an analog-to-digital converting unit for outputting a digital code having temperature information based on the first voltage, the digital code having varied resolution according to temperature ranges.

Abstract: In a non-linear processing system, the main non-linear processing and filtering is performed with low precision in a separate branch. A low-precision version (22) of the input signal (14) is created in an extractor (20), which is processed non-linearly in a low-precision non-linear processing unit (11) under constraints put on the non-linear processing. Quantisation errors or other artefacts, created by the use of low precision signals are finally removed by a precision restoring processing in a precision restoring unit (26) using the full-precision signal (14).

Abstract: A method of operating an imaging device, an imaging device, a camera system including an imaging device, and a processing system including an imaging device for calibrating an analog-to-digital converter of the imaging device to generate a look-up table of correction values, and correcting an output of the analog-to-digital converter with the correction values.

Abstract: Disclosed is a data driver including a reference voltage generation circuit that generates and outputs a plurality of reference voltages, a decoder circuit that selects from among the reference voltages n (where n is an integer greater than or equal to two) reference voltages inclusive of reference voltages that may be identical and outputs the n reference voltages from n output terminals thereof, and an amplifying circuit that includes n differential circuits, a feedback resistor, and a resistor. The n output terminals are connected to non-inverting input terminals of the n differential circuits, respectively. The amplifying circuit outputs an output voltage obtained by operating and synthesizing the n reference voltages. One end of the feedback resistor is connected to an output terminal of the amplifying circuit, and the other end is connected to inverting input terminals of the n differential circuits connected in common.

Abstract: A system and a method for converting an analog signal to a digital signal are provided. The technique involves receiving a sampled analog signal, and selecting one of a plurality of segments of a segmented relation between DAC output values and desired ADC input values. Desired gain and offset values are applied to the DAC output values or to the sampled analog signal based upon the selected segment. The sampled analog signal is converted to a digital signal based upon the desired gain and offset values.

Abstract: Circuitry for providing non-uniform analog-to-digital (“A/D”) signal conversion for wideband signals is provided. The circuitry of the invention is optimized for wideband signals because it does not sacrifice the small-scale resolution of high-probability signal amplitudes while preventing the clipping of low-probability signal amplitudes. The circuitry includes a nonlinear amplifier and an A/D converter that may be uniform or non-uniform. The digital output of the A/D converter may be further processed by circuitry that has an output function that is the inverse of that of the nonlinear amplifier, so as to maintain linear A/D conversion.

Abstract: A method for conversion of signals between analog and digital characterised by; applying a non-linear transfer function to an input signal, such that the relation between the quantisation levels of the converter and the input signal vary as a non-linear function of the magnitude of the input signal. The non-linear transfer function is related to the probability density function of the input signal so that larger quantisation bins of the converter correspond to less probable values of the input signal.

Abstract: Embodiments of an analog-to-digital converter (ADC) and methods for controlling RF power levels are generally described herein. Other embodiments may be described and claimed. In some embodiments, the ADC includes an internal-reference digital-to-analog converter (DAC) having a resistive structure with linearly-spaced contact nodes. The linearly-spaced contact nodes may provide corresponding reference voltages that vary exponentially with respect to the linearly-spaced contact nodes allowing the ADC to achieve a logarithmic response.

Abstract: Circuitry for providing non-uniform analog-to-digital (“A/D”) signal conversion for wideband signals is provided. The circuitry of the invention is optimized for wideband signals because it does not sacrifice the small-scale resolution of high-probability signal amplitudes while preventing the clipping of low-probability signal amplitudes. The circuitry includes a nonlinear amplifier and an A/D converter that may be uniform or non-uniform. The digital output of the A/D converter may be further processed by circuitry that has an output function that is the inverse of that of the nonlinear amplifier, so as to maintain linear A/D conversion.

Abstract: A signal processing system includes a receiving terminal configured to receive a digital signal comprising a plurality of samples associated with a plurality of original sampling times, wherein the original sampling times have a period of T, and a compensation module coupled to the receiving terminal. The compensation module is configured to generate, based on the digital signal, a nominal phase shifted signal having a plurality of nominal phase shifted samples associated with a plurality of phase shifted sampling times, wherein the plurality of phase shifted sampling times correspond to fractional intervals of the original sampling times. The compensation module is further configured to generate a compensated signal based at least in part on the digital signal and the nominal phase shifted signal.

Abstract: An analog-to-digital converter according to the invention is provided. The analog-to-digital converter preferably includes an analog input signal, a first reference signal, a second reference signal, and a range compression signal. The range compression signal is preferably characterized by a magnitude greater than the first reference signal and smaller than the second reference signal. In addition, when the analog input signal is sampled N times and the range compression signal is sampled N1 times, a compression factor related at least in part to the ratio N1/(N+N1) is obtained.

Abstract: In a non-linear processing system, the main non-linear processing and filtering is performed with low precision in a separate branch. A low-precision version (22) of the input signal (14) is created in an extractor (20), which is processed non-linearly in a low-precision non-linear processing unit (11) under constraints put on the non-linear processing. Quantisation errors or other artefacts, created by the use of low precision signals are finally removed by a precision restoring processing in a precision restoring unit (26) using the full-precision signal (14).

Abstract: An AD converter includes: a reference voltage generator circuit having a plurality of resistors connected in series with predetermined reference voltage applied to both ends thereof, the reference voltage being divided at connecting points between the individual resistors to generate a plurality of reference voltages; a voltage comparator circuit configured to compare the plurality of reference voltages and analog input signals for conversion into predetermined comparison output signals; and a variable voltage circuit connected to the connecting points of the reference voltage generator circuit and provided with a control signal input terminal inputted with control signals, configured to set an output voltage to be outputted to the connecting points at a predetermined value based on the control signals.

Abstract: A D/A converter inputted with non-linear conversion digital data such as a digital signal encoded according to a ?-Law system or the like as it is to convert into an analog signal. A D/A converter is of resistor string type, in which a resistance value of each of resistors of a resistor string is not set uniform but weighted so that a non-linear relationship between an encoded input digital signal and an output analog signal is converted into a linear relationship. Consequently, a decode circuit for converting non-linear conversion digital data into linear conversion digital data is not required.

Abstract: An analog-to-digital converter (ADC) architecture to implement a non-linear flash ADC. The apparatus includes a non-linear resistor, a non-linear comparator, and an inverse non-linear encoder. The non-linear resistor has an input and a plurality of non-linear voltage outputs. The non-linear comparator ladder is coupled to the plurality of non-linear voltage outputs of the non-linear resistor. The non-linear comparator ladder includes a bank of comparators to compare an input signal to each of a plurality of non-linear voltage signals corresponding to the plurality of non-linear voltage outputs. The inverse non-linear encoder is coupled to the non-linear comparator ladder. The inverse non-linear encoder generates a digital output code based on the input signal and the plurality of non-linear voltage signals.

Abstract: A method for analog to digital conversion (ADC) characterised by; applying a non-linear transfer function to an input signal, such that the relation between the quantisation levels of the converter and the input signal vary as a non-linear function of the magnitude of the input signal. The non-linear transfer function is related to an at least approximate measurement of probability density function ‘p(x)’ of said input signal so that larger quantisation bins of the converter correspond to less probable values of the input signal. The relation is iteratively updated by updating quantisation levels.

Abstract: An analog-to-digital converter error detector suitable for single-chip control loop applications employs a single comparator determining the difference between an initial input voltage and a reference voltage in one or more conversion iterations, with the difference reduced in nonlinear steps during each conversion iteration based on the ratio between sampling and discharge capacitances. The number of conversion iterations required to reduce the initial input voltage to below the reference voltage is counted as representing the difference, with output codes representing the conversion iteration count having a step size increasing with the count value and selected to reduce downstream processing.

Abstract: A power converter including a hardware efficient control loop architecture. Error detection circuitry may generate an error signal based on the difference between a power converter output voltage and a reference voltage. An oversampling ADC may digitize the error signal. The transfer function associated with the ADC may include quantization levels spaced at non-uniform intervals away from a center code. A digital filter may calculate the average of the digitized error signal. A nonlinear requantizer may reduce the number of codes corresponding to the output of the digital filter. A proportional integral derivative (PID) unit may multiply the output of the nonlinear requantizer by PID coefficients to generate a PID duty cycle command, and a gain compensation unit may dynamically adjust the PID coefficients to maintain a constant control loop gain. A noise-shaped truncation unit including a multi-level error-feedback delta sigma modulator may reduce the resolution of the PID duty cycle command.

Abstract: A digitally programmable gain control circuit and method of operating the same is disclosed. The gain control circuit includes a programmable gain amplifier having an amplifier structure represented by a plurality of overlapping discrete monotonic transfer function segments, wherein at least one point of non-monotonicity occurs among one or more of the plurality of overlapping discrete monotonic transfer function segments, and a gain segment translator circuit operative to translate a monotonic gain value to a segment code to match the non-monotonic characteristics of the programmable gain amplifier. The programmability of the gain amplifier is provided by a coarse gain control circuit and a fine gain control circuit.

Abstract: Circuitry for providing non-uniform analog-to-digital (“A/D”) signal conversion for wideband signals is provided. The circuitry of the invention is optimized for wideband signals because it does not sacrifice the small-scale resolution of high-probability signal amplitudes while preventing the clipping of low-probability signal amplitudes. The circuitry includes a nonlinear amplifier and an A/D converter that may be uniform or non-uniform. The digital output of the A/D converter may be further processed by circuitry that has an output function that is the inverse of that of the nonlinear amplifier, so as to maintain linear A/D conversion.

Abstract: A digital equalization apparatus is provided with an analog low pass filter for removing a high-frequency component from an input analog signal, a non-linear analog to digital (A/D) converter for non-linearly sampling the analog signal to output a digital signal, and an equalizer 2 for waveform-equalizing the digital signal outputted from the non-linear A/D converter. The non-linear A/D converter non-linearly A/D converts the analog signal so that, with a center value of amplitude of the analog signal being a reference, resolution per least significant bit (LSB) becomes higher as an input center of the non-linear A/D converter is closer to the center value while the resolution per LSB becomes lower as the input center of the non-linear A/D converter is farther from the center value.

Abstract: A circuit arrangement (10) for compensating for nonlinearities (NL1, NL2) from analog/digital converters (15, 16) operating with different timing, having at least two analog/digital converters (15, 16) which are each clocked with different timing and which each have a predetermined nonlinear converter characteristic with integral nonlinearities (NL1, NL2), and which accept an analog input signal (VIN) applied to an input (11) on the circuit arrangement and respectively convert it into a digital intermediate signal (Z1, Z2); and having a multiplexer (22) which is arranged downstream of the analog/digital converters and which successively switches through the digital intermediate signals (Z1, Z2) in order to produce a digital output signal (ZD) from the circuit arrangement (10); where at least one of the nonlinear converter characteristics of the various analog/digital converters (15, 16) is predetermined such that after the intermediate signals have been combined in the multiplexer (22) the integral nonlineari

Abstract: Circuits and methods to convert a digital floating-point number into an analog current have been achieved. The conversion is performed directly by using an exponential current digital-to-analog converter (DAC) and a cascaded linear current digital-to-analog converter (DAC). The exponential current DAC is converting exponentially the exponent of the floating-point number, its output current is biasing the linear DAC, which is converting the mantissa of the floating-point number. The output current of the linear current DAC is correlates linearly with the value of the floating-point number. This technique is commutative, this means the sequence of the linear and the exponential converter can be interchanged. In this case the linear converter provides a biasing current to the exponential converter. The sign bit can be considered by converting the direction of the output current of the converter. This floating-point number conversion can handle a very high dynamic range and requires a minimum of chip space.

Abstract: A method and signal processing apparatus for reducing the number of bits of a digital input signal (Mi), includes adding a pseudo-random noise signal (Na) to the digital input signal (Mi) to obtain an intermediate signal (Di), the pseudo-random noise signal (Na) being defined by noise parameters (Np), and quantizing the intermediate signal (Di), having a word length of n bits, to a reduced word-length signal (Me) having a word length of m bits, n being larger than or equal to m. The method further includes quantizing the intermediate signal (Di) using a first transfer function which is non-linear, the first transfer function being defined by non-linear device parameters (NLDp).

Abstract: A device for correcting a digital estimate of an electric signal is described. The device includes a comparator that generates a current proportional to the difference between an analog estimate signal, which derives from the digital estimate, and the electric signal. The device also includes a capacitor positioned to be charged by the current, a transistor that discharges the capacitor, and a comparator that compares the voltage at the terminal of the capacitor with a reference voltage. The device also includes a controller that drives the transistor in response to the output signal of the comparator and a logic device that generates a correction digital signal to be added to or subtracted from the digital estimate of the electric signal in correspondence of an ascending or descending waveform of the electric signal.

Abstract: A method for calibrating a segmented analog to digital signal conversion system is provided. The method includes segmenting a desired relationship between DAC output values and desired ADC input values into a plurality of segments. Each of the plurality of segments includes an offset value and a gain value. The method also includes computing the offset value and an offset coefficient for each of the plurality of segments, computing the gain value and an gain coefficient for each of the plurality of segments, and storing the offset value and the gain value for each of the plurality of segments in a memory unit for reference in converting an analog signal to a digital signal based upon the gain value and offset value.

Abstract: A method for constellation design in a telecommunications network using pulse code modulation to transmit data signals upstream between client and server voice-band modems. The invention selects a constellation for transmission over an analog channel of an equivalence class of data points using pulse code modulation based on the presence or absence of robbed bit signaling and interference from echo levels. The constellation is designed by determining noise in a PCM channel using a cumulative distribution function for echo, determining the extent of said noise for an array of possible constellation points, and selecting constellation points such that the largest negative noise of a first point remains above the largest positive noise level of a neighboring second point. Constellations are created off-line and stored for retrieval during modulation depending on the level of the echo.

Abstract: A nonlinearity detection system for an analog to digital converter (ADC) comprises a signal generator that generates a periodic signal that is output to the ADC and that comprises first and second intervals. The periodic signal monotonically increases during the first interval and monotonically decreases during the second interval. A differentiator module communicates with the ADC and that generates an output signal that is based on an output of the ADC and a delayed output of the ADC. A nonlinearity detection module detects slope discontinuities in the output signal of the differentiator module.

Abstract: A method of, and a converter for, converting an analogue input signal (X) to a digital output signal (Y) by incremental-delta conversion in which, at clock intervals, a non-uniform quantizer (7) produces digital quantizer signals, a digital-to-analogue converter (5) produces analogue quantizer signals that are a function of the digital quantizer signals, analogue difference signals (Q) are applied over a feedback loop to the quantizer (7) that are a function of the difference between the input signal (X) and the integral of the analogue quantizer signals since a reset signal, and the digital output signal (Y) is produced as a function of the sum of the digital quantizer signals since the reset signal.

Abstract: An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.

Abstract: A method of, and a converter for, converting an analogue input signal (X) to a digital output signal (Y) by incremental-delta conversion in which, at clock intervals, a non-uniform quantizer (7) produces digital quantizer signals, a digital-to-analogue converter (5) produces analogue quantizer signals that are a function of the digital quantizer signals, analogue difference signals (Q) are applied over a feedback loop to the quantizer (7) that are a function of the difference between the input signal (X) and the integral of the analogue quantizer signals since a reset signal, and the digital output signal (Y) is produced as a function of the sum of the digital quantizer signals since the reset signal.

Abstract: A method of digitally processing an analog signal in continuous time includes producing a continuous-time digital signal from an analog signal via a technique that does not include periodic sampling, then producing one or more delayed versions of the continuous-time digital signal. Each delayed version is delayed by nT, where n is an integer greater than zero, and T is a delay interval. The method further includes multiplying the continuous-time digital signal and each of the delayed versions by one or more associated coefficients, so as to produce a set of products, then adding the set of products, so as to produce a sum value corresponding to the analog signal processed by a transfer function defined by the associated coefficients. The individual bit paths of the continuous-time digital signal are multiplied by the coefficients, and the resulting products are combined by a binary-weighted adder.

Abstract: An analog multiplier 11 raises a base reference voltage “Vref0” to the nth power so that a reference voltage “Vref1” is produced. Analog multipliers 12 and 13 sequentially raise the reference voltage “Vref1” to the nth power so that reference voltages “Vref2” and “Vref3” are produced. Switch groups 38-41 control the reference voltages “Vref0” to “Vref3”, which are then sent to an analog multiplier 14 together with an input voltage “Vin”. A comparator 14 sequentially compares a multiplication result “Vx” of the multiplier 14 with a voltage “Vout” outputted from a sensor circuit 2, so that a digital output value “Dout” is produced. The analog multiplier 14 is set as appropriate.

Abstract: The variable gain analog-to-digital conversion device (1) for an image sensor comprises at least one N-bit non-linear coarse first converter (21) receiving a pixel voltage signal (Vpix) and at least one M-bit linear fine second converter (22) connected to the first converter (21) in order for the device to supply a binary word of N+M bits relating to the voltage level of the pixel. The first converter (21) comprises comparison means (33) for comparing the voltage level of the pixel with one or more voltage thresholds (V0 to V4) delimiting voltage ranges within the voltage dynamic range of the sensor. The successive voltage ranges represent areas of illumination of the pixel ranging from a weakly lit area to a strongly lit area. The first comparator supplies an N-bit binary word relating to the area of illumination determined for the pixel.

Abstract: Improved digital to analog converter (DAC) circuitry incorporating the ability to utilize a single DAC to generate either voltage or current outputs, and the ability to digitally adjust the gain and offset. Previous digital to analog circuitry has been limited to a single type of analog output per DAC and to the use of external precision resistors to set the gain and offset for a single DAC, or a group of DACs. By utilizing the same on-chip circuitry to supply both types of outputs, chip area, power consumption and cost is reduced while offering more flexibility to the customer. The ability to digitally adjust the gain and offset for a group of DACs eliminates the cost of external resistors, lowers the board area, and lowers the assembly cost for the end product. In addition, since gain and offset can be adjusted dynamically, maximum flexibility is provided to the customer.

Abstract: A semiconductor integrated circuit comprises a digital-to-analogue converter for converting a digital signal into an analogue signal to output an analogue current signal, a current-to-voltage converter for converting the analogue current signal output by the digital-to-analogue converter, into an analogue voltage signal whose level has been controlled, and a filter for filtering the analogue voltage signal converted by the current-to-voltage converter. The current-to-voltage converter converts the current signal into the voltage signal in which a factor variable in accordance with manufacturing process conditions and/or environmental conditions has been corrected.

Abstract: A digital equalization apparatus is provided with an analog LPF 4 for removing a high-frequency component from an input analog signal, a non-linear A/D converter for non-linearly sampling the analog signal to output a digital signal, and an equalizer 2 for waveform-equalizing the digital signal outputted from the non-linear A/D converter. The non-linear A/D converter non-linearly A/D converts the analog signal so that, with a center value of amplitude of the analog signal being a reference, resolution per LSB becomes higher as an input center of the non-linear A/D converter is closer to the center value while the resolution per LSB becomes lower as the input center of the non-linear A/D converter is farther from the center value.