Abstract: In some examples, a system includes a digital-to-analog converter (DAC) configured to operate at a clock rate; a mixer configured to up-convert an intermediate-frequency (IF) signal from the DAC to a radio-frequency (RF) signal based on a local oscillator (LO) signal; and an RF filter configured to generate a filtered signal by at least removing, from the RF signal, frequency components greater than a difference between a frequency of the LO signal and one-half of the clock rate and less than a sum of a frequency of the LO signal and one-half of the clock rate, wherein an output node of the RF filter is configured to be coupled to an antenna for transmission of the filtered signal.

Abstract: Systems, devices, computer-implemented methods, and/or computer program products that facilitate low power, wideband multitone generation. In one example, a multitone generator device can comprise a controller operatively coupled to first and second digital-to-analog converters (DACs). The controller can apply different delays of a sampling signal to the first and second DACs to facilitate sideband suppression of signals output by the first and second DACs. One aspect of such a multitone generator device is that the multitone generator device can facilitate low power, wideband multitone generation.

Abstract: A servovalve includes a torque motor section and a hydraulic section. The torque motor section may comprise first and second opposing pole pieces and first and second permanent magnets may be positioned between these first and second pole pieces. The torque motor section also comprises an armature/flapper assembly which comprises a torsion bridge, an armature plate and a flapper that is connected at a first end to the armature plate. The flapper extends from said armature plate along a first longitudinal axis X. The armature plate may extend between the first and second permanent magnets and along a second longitudinal axis Y that is perpendicular to the first axis X. The hydraulic section comprises: a housing that comprises a body section and a chimney section. The chimney section extends from the body section to a first end.

Abstract: A signal quantizer includes a summing junction, a loop filter, a quantizer and a reconstruction filter. The summing junction is responsive to an input signal and to a modulated signal and is operative to combine the modulated signal and the input signal to generate a summing junction output. The loop filter is responsive to the summing junction output and is operative to generate a loop filter output and has a first regenerative gain associated therewith. The quantizer is responsive to the loop filter output and is operative to generate the modulated signal. The reconstruction filter is responsive to the modulated signal and is operative to generate a quantized output signal and has a second regenerative gain associated therewith that is substantially equal to that of the loop filter.

Abstract: An improved quadrature bandpass-sampling delta-sigma analog-to-digital demodulator is provided, which includes a loop filter, an A/D responsive to the loop filter, and a first feedback D/A responsive to the A/D up-converted in frequency by a first multiplier and a clock. A first summing circuit is responsive to the first D/A and an RF input for providing an input to the loop filter. A plurality of feedback D/As is responsive to the A/D up-converted in different frequencies by a plurality of multipliers and a plurality of clocks for providing feedback inputs to the loop filter. The loop filter comprises a plurality of resonators arranged in cascade configuration, a plurality of analog mixers to provide frequency shifting of the error signals propagating through the resonators, and a plurality of summing circuits responsive to the feedback D/As.

Abstract: Examples are provided for converting an analog signal to a digital signal by processing more than one bit per cycle in a number of successive approximation cycles. A system may include capacitive sub-DAC circuits and comparators. Switches may isolate the capacitive sub-DAC circuits during one or more first cycles, and merge the sub-DAC circuits during one or more last cycles. A successive approximation register (SAR) may generate digital output signals or DAC digital signals. In another example, a system may include a DAC circuit. An input capacitor may be pre-charged to at least one of an analog input signal and a DAC analog signal. A programmable gain amplifier may amplify an error signal. A multi-bit ADC may convert the amplified error signal to a multi-bit digital signal. An SAR may use the multi-bit digital signal to generate a DAC digital signal or a digital output signal.

Abstract: In a method for improving resolution and for correcting distortions for a sigma-delta modulator, a modulator converts an analog input signal into a secondary output digital signal sampled at a frequency fe and coded on NB bits, a second main output digital signal s?(t) is represented on NMSB bits also being available at the output. At least three processings are applied successively to the outputs, a first processing carrying out a demodulation by a frequency f0 and a decimation of factor N in an independent manner, z second processing carrying out an improvement of the resolution and a third processing carrying out a correction of the distortions. These three processings are carried out after decimation. A sigma-delta modulator implements the method.

Abstract: A digital to analog conversion apparatus includes a plurality of gain/phase adjusters configured to receive a digital signal and to output a plurality of adjusted digital input signals, a plurality of digital to analog converters coupled to respective ones of the plurality of gain/phase adjusters and configured to receive the adjusted digital input signals and to generate respective analog signals representative of the adjusted digital input signals, a plurality of phase shift elements coupled to respective ones of the plurality of digital to analog converters and configured to shift the phases of the analog signals generated by the digital to analog converters, and a combiner coupled to the outputs of the plurality of digital to analog converters and configured to combine the respective phase-shifted analog signals to form an analog output signal.

Abstract: A method and apparatus for a Gigabit Ethernet transceiver that has a Class-B amplifier in a main transmitter for higher efficiency and power handling capabilities. The output current of the main transmitter is produced by a reference voltage applied across a resistor, where the reference voltage generator, resistor and amplifier are fabricated on the same substrate, such that the output current is constant across process voltage and temperature. The transceiver also has a replica transmitter whose signal is used to cancel the main transmitter signal at the input of the receiver section of the transceiver. The replica transmitter is fabricated on the same substrate as the main transmitter, such that its output signal reflects non-linearities in the main transmitter across process voltage and temperature.

Abstract: In a high-fidelity digital modulator, a mapper is provided to minimize quantization noise, jitter, and cross-talk between multiple digital-to-analog or analog-to-digital converters. The mapper receives a quantized level from a quantizer and maps the quantized level to an output sequence. The mapper includes a table defining multiple sequences corresponding to each quantized level. Each sequence includes two or more symbols, having one of multiple values. The mapper also includes a generator that selects one of the multiple sequences as the output sequence. The last symbol of a first output sequence is equal to the first symbol of the next output sequence and so on. The generator selects the output sequence by alternating between a first and a second sequence for each quantized level received. The generator selects the output sequence by alternating between sequences having a positive and a negative common mode energy for each odd valued quantized level received.

Abstract: A digital to analog converter (DAC) is provided. The DAC includes a first loop unit to receive a plurality of sources and comprising a plurality of primary winding of transistors formed at a plurality of locations, and a second loop unit comprising secondary windings to correspond to the primary windings, to receive the plurality of sources through the first loop unit, and combine the plurality of sources and output the result. Accordingly, a DAC is capable of directly converting a digital signal into an RF analog signal.

Abstract: Disclosed herein is a reconfigurable mixed signal distributed arithmetic system including: an array of tunable voltage references operable for receiving a delayed digital input signal; a combination device in electrical communication with the array of tunable floating-gate voltage references that selectively combines an output of the array of tunable voltage references into an analog output signal; and a feedback element in electrical communication with the combination device, wherein the array of tunable voltages and the delayed digital input signal combine to perform a distributed arithmetic function and the reconfigurable mixed signal distributed arithmetic system responsively generates the analog output signal.

Abstract: A high-performance superconducting digital-to-analog (D/A) converter providing asynchronous high-speed, low-power D/A conversion. The high-performance superconducting D/A converter includes a double-junction superconducting quantum interference device (SQUID) voltage divider circuit, which generates a series of discrete binary voltages, and a double-junction SQUID voltage selector circuit, which selects the binary voltages in accordance with a digital input signal. The currents generated by the selected binary voltages are added together to produce an analog output current that represents the digital input.

Abstract: A DC current-comparator-based circuit generates an adjustable output proportional to an input signal, i.e. an input voltage or current. One use of the circuit is in the formation of a DC resistance bridge that can be controlled automatically by a microprocessor. The ends of a pair of test resistors (the resistances of which are to be compared) are connected to respective ratio windings of the current comparator. The same potential is applied across these resistors by a master power supply. A microprocessor is alternately supplied with two voltage signals, a first being proportional to the current in a variable one of the ratio windings of the comparator, and the second being proportional to any inequality between the current in the other ratio winding and the test resistor to which it is connected. The microprocessor controls a slave power supply that receives both the first signal and a third signal that is indicative of any unbalance in the bridge.

Abstract: In a superconducting digital to analog converter, shunt branches of a ladder resistor network are connected to corresponding Josephson devices, the states of which are switched by a digital signal. Currents following through the Josephson devices or load resistors of the Josephson devices are collected to obtain an analog signal corresponding to the digital signal.

Abstract: An absolute encoder for detecting the absolute (as opposed to the relative) rotational displacement of an encoder shaft includes a pair of pitch signals recorded on tracks and an associated signal processing circuit. The pair of pitch signals have different periods (wave lengths) which are such that they have no common factors. The signal processing circuit includes magnetic sensors for producing absolute position data indicative of the degree of displacement of the encoder shaft, on the basis of the pitch signals. Through the use of a pair of pitch signals having periods with no common factor, a high degree of resolution is obtained, without having no significantly increase the number of pitch signal tracks.