Digital To Analog Conversion Patents (Class 341/144)
  • Patent number: 11875716
    Abstract: A dual source driver includes first and second gamma voltage generators configured to generate first and second gamma voltages, respectively, first and second latches configured to latch first and second data, respectively, a first driving cell configured to receive the first gamma voltage and the first data, and to transmit a first voltage corresponding to the first data and the first gamma voltage to a panel load based on a first switching operation, and a second driving cell configured to receive the second gamma voltage and the second data, and to transmit a second voltage corresponding to the second data and the second gamma voltage to the panel load based on a second switching operation. The first switching operation and the second switching operation may operate complementarily to each other.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: January 16, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sungho Lee, Hohak Rho, Junjae Lee
  • Patent number: 11876530
    Abstract: An example apparatus includes: a voltage-to-current circuit including a first input terminal, a first output terminal and a second output terminal, a subtraction circuit including a second input terminal and a third output terminal, the second input terminal coupled to the second output terminal, a first driver circuit including a third input terminal and a fourth output terminal, the third input terminal coupled to the third output terminal, and a second driver circuit including a fourth input terminal and a fifth output terminal, the fourth input terminal coupled to the first output terminal, the fifth output coupled to the fourth output terminal.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: January 16, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Atul Kumar Agrawal, Kanak Chandra Das
  • Patent number: 11791832
    Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO? signals, and outputs a second controlled LO signal output to a sense circuit.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: October 17, 2023
    Assignee: NXP B.V.
    Inventors: Erik Olieman, Rene Verlinden, Helmut Kranabenter
  • Patent number: 11757610
    Abstract: A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.
    Type: Grant
    Filed: April 18, 2022
    Date of Patent: September 12, 2023
    Assignee: NXP B.V.
    Inventors: Martin Kessel, Andreas Johannes Gerrits, Sebastian Bohn, Prince Thomas
  • Patent number: 11750209
    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50?.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventor: Franz Kuttner
  • Patent number: 11742874
    Abstract: A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.
    Type: Grant
    Filed: November 29, 2022
    Date of Patent: August 29, 2023
    Assignee: Rambus Inc.
    Inventors: Ravi Shivnaraine, Marcus Van Ierssel
  • Patent number: 11742869
    Abstract: A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: August 29, 2023
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Anthony Eugene Zortea, Hananel Faig, Boris Sharav, Mor Goren, Alik Gorshtein, Nir Sheffi
  • Patent number: 11736118
    Abstract: A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the nth current source set is twice a total quantity of current sources of the (n?1)th current source set.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: August 22, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Juei Chin Shen, Liang Huan Lei, Chien Wen Chen
  • Patent number: 11687110
    Abstract: A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 27, 2023
    Assignee: Efficient Power Conversion Corporation
    Inventors: John S. Glaser, Stephen L. Colino
  • Patent number: 11688320
    Abstract: Disclosed is a gamma amplifier which includes a first amplification device that receives a first input signal during a first track period in a first time period, compensates for a first offset voltage from the first input signal during a first compensation period in the first time period, and generates a first output signal during a second time period after the first time period based on a control signal, and a second amplification device that receives a second input signal during a second track period in the second time period, compensates for a second offset voltage from the second input signal during a second compensation period in the second time period, and generates a second output signal during a third time period after the second time period based on the control signal and processing circuitry configured to generate the control signal.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: June 27, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-Suk Kim, Yeonjeong Lee
  • Patent number: 11646750
    Abstract: An analog-to-digital converter (ADC) is provided. In some examples, the ADC includes a first reference voltage supply input, a second reference voltage supply input, a comparator comprising an input node, and a first reference switch coupled between the second reference voltage supply input and the input node of the comparator. The ADC also includes a set of capacitors, where each capacitor of the set of capacitors comprises a first terminal. In addition, the ADC includes a second reference switch coupled between the first reference voltage supply input and the first terminal of each capacitor of the set of capacitors. The ADC further includes a third switch coupled between the input node of the comparator and the first terminal of each capacitor of the set of capacitors.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: May 9, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Abhijit Kumar Das
  • Patent number: 11626883
    Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: April 11, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Zhengzheng Wu, Chao Song, Karthik Nagarajan
  • Patent number: 11611840
    Abstract: A sound generation system and related method include a user interface device and a processing device to obtain a specification of a three-dimensional space, obtain one or more sound tracks each comprising a corresponding sound signal associated with a corresponding sound source, present, in a user interface, representations representing one or more listeners and the one or more sound sources corresponding to the one or more sound signals in the three-dimensional space, responsive to a configuration of the locations of the one or more listeners or the locations of the one or more sound sources in the three-dimensional space in the user interface, determine filters based on the configuration and pre-determined locations of one or more loudspeakers, and apply the filters to the one or more sound signals to generate filtered sound signals for driving the one or more loudspeakers.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: March 21, 2023
    Assignee: Li Creative Technologies, Inc.
    Inventors: Qi Li, Yin Ding, Jorel Olan, Jason Thai
  • Patent number: 11551076
    Abstract: A method of processing asynchronous event-driven input samples of a continuous time signal, includes calculating a convolutional output directly from the event-driven input samples. The convolutional output is based on an asynchronous pulse modulated (APM) encoding pulse. The method further includes interpolating output between events.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: January 10, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Xin Wang, Young Cheul Yoon, Manu Rastogi
  • Patent number: 11552623
    Abstract: The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: January 10, 2023
    Assignee: POSTECH Research and Business Development Foundation
    Inventors: Jae Yoon Sim, Ki Seo Kang
  • Patent number: 11528032
    Abstract: Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 13, 2022
    Assignee: TELEDYNE E2V SEMICONDUCTORS SAS
    Inventor: Grégory Wagner
  • Patent number: 11496149
    Abstract: Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.
    Type: Grant
    Filed: October 9, 2020
    Date of Patent: November 8, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Vijay S. Ramesh
  • Patent number: 11489534
    Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: November 1, 2022
    Assignee: Cirrus Logic, Inc.
    Inventors: Seung Bae Lee, Sunny Bhagia, Jaiminkumar Mehta, Anindya Bhattacharya, John L. Melanson
  • Patent number: 11469769
    Abstract: Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: October 11, 2022
    Assignee: Cadence Design Systems, Inc.
    Inventors: Louis-Francois Tanguay, Jean-Francois Delage, Guillaume Fortin
  • Patent number: 11417272
    Abstract: A pixel circuit and driving method are provided. The pixel circuit includes a light emitting device having a first terminal and a second terminal; a driving circuit, electrically connected to the first terminal of the light emitting device, for providing power to the light emitting device; a voltage comparator for generating a pulse width modulated signal having a duty cycle based on a data voltage and a reference voltage; an offset voltage detecting circuit, electrically connected to an output terminal of the voltage comparator, for detecting an input offset voltage of the voltage comparator; and a data voltage compensation circuit, electrically connected to the offset voltage detecting circuit, for compensating the data voltage according to the input offset voltage detected.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: August 16, 2022
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Ming Yang, Ning Cong, Han Yue, Can Zhang, Can Wang, Jiao Zhao, Angran Zhang, Minghua Xuan, Xiaochuan Chen
  • Patent number: 11368163
    Abstract: This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: June 21, 2022
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Gideon Van Zyl
  • Patent number: 11359247
    Abstract: Provided herein are genetic circuits and cell state classifiers for detecting the microRNA profile of a cell. The cell state classifiers of the present disclosure are designed to incorporate multiple genetic circuits integrated together by transcriptional or translational control. Multiple inputs can be sensed simultaneously by coupling their detection to different portions of the genetic circuit such that the output molecule is produced only when the correct input profile of miRNAs is detected. The genetic circuits and cell state classifiers may be used in various applications (e.g., therapeutic or diagnostic applications).
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: June 14, 2022
    Assignee: Massachusetts Institute of Technology
    Inventors: Ron Weiss, Jin Huh
  • Patent number: 11356114
    Abstract: In some examples, a system includes an integrated circuit comprising a transistor, a first amplifier coupled to the transistor, a second amplifier having an output and coupled to the transistor and the first amplifier, and an R-2R resistor ladder having multiple rungs. Each rung is switchably coupled to a terminal of the transistor and to the output of the second amplifier. The R-2R resistor ladder includes a resistor coupled to either the transistor or the output of the second amplifier.
    Type: Grant
    Filed: March 4, 2021
    Date of Patent: June 7, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Binan Wang
  • Patent number: 11356110
    Abstract: A voltage-to-time converter (VTC) for a time-domain analog-to-digital converter is disclosed, which provides a time-domain analog-to-digital converter (T-ADC) with low power consumption and high precision. By combining the advantages of current-starving technology, current mirror technology, and body biasing technology, compared with the traditional structure, the VTC and T-ADC achieve excellent performance, such as low power consumption, high linearity, wide input dynamic range, and strong anti-interference to PVT variations. Compared with the traditional voltage-to-time converter, the disclosed voltage-to-time converter has a wider input dynamic range and higher linearity. The input voltage is connected to transistors in the circuit as a body bias, resulting in a very small body current, and no apparent increase in power consumption. The design of a low-power voltage-to-time converter is realized.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: June 7, 2022
    Assignee: University of Electronic Science and Technology of China
    Inventors: Hua Fan, Xiaohu Qi, Qianqian Deng, Quanyuan Feng, Shaoqing Lu, Huaying Su, Guosong Wang
  • Patent number: 11341892
    Abstract: A display driver includes a D/A converter circuit outputting a gradation voltage to an output line based on display data, an assist circuit including a capacitor group and a drive circuit outputting a drive signal group to a first end of the capacitor group based on the display data, the assist circuit being coupled to the output line and configured to perform assist driving of the output line, and an amplifier circuit configured to drive an electro-optical panel. The assist circuit includes an output switch provided between a second end of the capacitor group and the output line, the output switch being ON in an assist period, and an initialization switch including a first end coupled to the second end of the capacitor group and a second end to which an initialization voltage is input, and in an initialization period, the output switch and the initialization switch are ON.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 24, 2022
    Assignee: SEIKO EPSON CORPORATION
    Inventor: Takeshi Nomura
  • Patent number: 11336293
    Abstract: An electronic device may include digital circuitry that operates via digital signals and a digital to analog converter (DAC) to convert a digital signal into a modulated analog signal. The DAC may include multiple unit cells to generate an analog signal and multiple local oscillator (LO) tiles to modulate the analog signal and generate the modulated analog signal. The electronic device may also include LO circuitry to dynamically adjust an LO enable signal based at least in part on the digital signal. The LO enable signal may enable a reduced number of LO tiles supporting one or more respective sets of unit cells operatively enabled based on the digital signal.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 17, 2022
    Assignee: Apple Inc.
    Inventor: Antonio Passamani
  • Patent number: 11309857
    Abstract: A device is provided that includes a plurality of signal processing paths coupled in parallel, an adding circuit and an amplifier circuit. The number of the signal processing paths is N and each of the signal processing paths receives a same input signal to generate an output analog signal after a signal processing is performed, wherein each of the signal processing paths at least includes a DAC circuit and the signal processing at least includes a digital to analog conversion corresponding to the DAC circuit. The adding circuit adds the output analog signal generated from each of the signal processing paths to generate a total output analog signal. The amplifier circuit receives the total output analog signal to adjust a signal intensity of the total output analog signal according to a gain to generate an output audio signal, wherein the gain is 1/N.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: April 19, 2022
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Li-Lung Kao, Chia-Chi Tsai
  • Patent number: 11308415
    Abstract: Methods, systems, and apparatus for quantum analog-digital conversion. In one aspect, a method includes obtaining a quantum analog signal; applying a hybrid analog-digital encoding operation to the quantum analog signal and a qudit in an initial state to obtain an evolved state of the qudit, wherein the hybrid analog-digital encoding operation is based on a swap operation comprising multiple adder operations; and providing the qudit in the evolved state as a quantum digital encoding of the quantum analog signal.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 19, 2022
    Assignee: X Development LLC
    Inventor: Guillaume Verdon-Akzam
  • Patent number: 11245413
    Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: February 8, 2022
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Si Herng Ng, Wen-Chi Wang
  • Patent number: 11245410
    Abstract: In accordance with an embodiment, a circuit includes a current digital-to-analog converter (DAC) having a current switching network coupled to a current DAC output, a first cascode current source coupled between a first supply node and the current switching network, a second cascode current source between a second supply node and the current switching network, and a shorting switch coupled between a first cascode node of the first cascode current source, and a second cascode node of the second cascode current source.
    Type: Grant
    Filed: December 10, 2020
    Date of Patent: February 8, 2022
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Matteo Dalla Longa, Francesco Conzatti
  • Patent number: 11233013
    Abstract: Devices, systems and methods for uniquely identifying integrated circuits are provided. For at least one embodiment, an identifiable integrated circuit in a lot of integrated circuits includes a plurality of identifier devices. Each of the identifier devices, when tested, returns a series of first test results that form an analog identifier for the integrated circuit. For one embodiment, the identifier devices is a Zener diode. The test results may be based on reverse breakdown voltage measurements determined prior to packaging of the integrated circuit. Later testing of the integrated circuit returns a second series of reverse breakdown voltage measurements that monotonically vary over time and temperature, as compared to the first series of test results. Such monotonical variation facilitates correlation of the first series of test results with the second series of test results and, thereby, identification of the integrated circuit.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: January 25, 2022
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jan Lucie Axel Lettens, Wim Dobbelaere, Bart Arthur Norbert De Leersnyder, Thomas Van Vossel
  • Patent number: 11233523
    Abstract: An apparatus is configured to generate, from a stream of periodic digital samples, a first sub-stream of periodic analog samples and a second sub-stream of periodic analog samples, each sub-stream comprising substantially stable time intervals. The apparatus is further configured to generate a sign-modulated sub-stream by applying to the second sub-stream a sign modulation operation effecting a sign transition during a stable time interval of the second sub-stream. The apparatus is further configured to generate an output stream of periodic analog samples based on a sum of the first sub-stream and the sign-modulated sub-stream, wherein a period of the output stream is shorter than periods of the first and second sub-streams.
    Type: Grant
    Filed: January 26, 2021
    Date of Patent: January 25, 2022
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, Ian Roberts, Yuriy Greshishchev, Naim Ben-Hamida, Kim B. Roberts
  • Patent number: 11222600
    Abstract: Disclosed are a source driver capable of achieving high speed and high resolution and a display driving circuit including the same. The source driver may include: a first channel group and a second channel group configured to output source driving signals; a first gradation voltage divider configured to generate first gradation voltages using gamma reference voltages and provide the first gradation voltages to the first channel group; and a second gradation voltage divider configured to generate second gradation voltages having the same level as the first gradation voltages using the gamma reference voltages, and provide the second gradation voltages to the second channel group. The first and second gradation voltage dividers are connected to a gamma reference voltage generator configured to provide the gamma reference voltages, and receive the gamma reference voltages having the same voltage range from the gamma reference voltage generator.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 11, 2022
    Assignee: Silicon Works Co., Ltd.
    Inventors: Hae Won Lee, Hyun Ho Cho, Jung Bae Yun, Ju Young Shin
  • Patent number: 11212893
    Abstract: An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 28, 2021
    Assignee: STMicroelectronics S.r.l.
    Inventors: Salvatore Difazio, Stefano Corradi, Giuseppe Calcagno
  • Patent number: 11195464
    Abstract: A display device and a driving method are disclosed. The display device includes a plurality of pixel areas disposed in a display panel. Each pixel area includes at least one row of pixel units. The display panel further includes a plurality of collecting modules, a comparing module, and a processing module. Each collecting module is connected to the pixel units in each pixel area and configured to obtain and transmit input power voltage signals of the pixel units in a corresponding pixel area to the comparing module. The comparing module receives and compares the input power voltage signals with a base voltage respectively and transmits comparison results to the processing module respectively. The processing module adjusts data voltages of the pixel units in the corresponding pixel area respectively based on the comparison results in order to compensate the pixel units in the corresponding pixel area for resistive voltage drop differences.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 7, 2021
    Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.
    Inventors: Shingo Kawashima, Jun Li
  • Patent number: 11196439
    Abstract: The present invention provides a device for processing digital signals. The device comprises a digital signal source configured to output codewords, a converter circuit configured to generate an output signal based on a first codeword received from the digital signal source, and a feed forward circuit configured to generate an output current based on a second codeword received from the digital signal source. The output current generated by the feed forward circuit is connected to a current supply of the converter circuit. The digital signal source is configured to generate the second codeword based on the first codeword in order to compensate for variations of a supply current of the converter circuit.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: December 7, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Mathias Helsen, Koen Cornelissens, Alexandre Daubenfeld, Sofia Vatti, Marc Borremans, Johannes Samsom
  • Patent number: 11190200
    Abstract: A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: November 30, 2021
    Assignee: Texas Instruments Incorporated
    Inventor: Jun Zhang
  • Patent number: 11177819
    Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.
    Type: Grant
    Filed: December 3, 2020
    Date of Patent: November 16, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Zhengzheng Wu, Chao Song, Karthik Nagarajan
  • Patent number: 11171661
    Abstract: A controlled switch having N inputs and a single output (N?2) is switchable between N states. In each state a respective one of the inputs is connected to the single output. There are N sources of sub-streams of analog samples, each sub-stream composed of pairs of adjacent analog samples. Each source is coupled to a respective one of the inputs. In operation, the controlled switch is controlled by a control signal to switch between the N states. While the controlled switch is in any one of the states, a data transition occurs between two adjacent analog samples in the sub-stream whose source is coupled to the input that is connected to the single output. The single output yields a high-bandwidth analog signal. Any pair of adjacent analog samples in any one of the sub-streams substantially determines a corresponding pair of adjacent analog samples in the high-bandwidth analog signal.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Ciena Corporation
    Inventors: Shahab Oveis Gharan, Yuriy Greshishchev, Naim Ben-Hamida, Kim B. Roberts
  • Patent number: 11159173
    Abstract: The present technology relates to a DAC circuit, a solid-state imaging element, and electronic equipment that can be achieved with a small-scale circuit configuration. The DAC circuit includes: a ramp DAC that generates a ramp signal that changes in voltage with a constant time gradient; an injection DAC that outputs a predetermined voltage during a reset period for resetting a comparison target voltage to be compared with the ramp signal; and an adding circuit that adds an output of the ramp DAC and an output of the injection DAC and outputs the outputs to a comparison circuit as a comparison reference voltage. The present technology can be applied to, for example, a DAC circuit of a solid-state imaging element, and the like.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: October 26, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shin Kitano, Masaki Sakakibara, Hidekazu Kikuchi, Mitsuaki Osame
  • Patent number: 11145243
    Abstract: A digital-analog conversion circuit includes an arithmetic circuit, a voltage output unit, decoders, and output lines. The arithmetic circuit receives a digital signal of multiple bits, divides the multiple bits into groups of two or more bits, and outputs a logical operation result of each group. The voltage output unit outputs voltages having different values. The decoders receive each voltage and the logical operation result, and outputs an analog signal corresponding to the digital signal. The output lines correspond to the decoders. Each decoder includes switches and selection units. The switches correspond to the voltages. Each switch alternates between output, of a corresponding voltage, to a corresponding output line and non-output, of a corresponding voltage, to a corresponding output line. The selection units correspond to the switches. The selection units receive the logical operation result, and each selection unit controls a corresponding switch based on the logical operation result.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: October 12, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yu Maehashi
  • Patent number: 11144316
    Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers, and MACs. Typically, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers, and MACs increase, usually the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: October 12, 2021
    Inventor: Ali Tasdighi Far
  • Patent number: 11094248
    Abstract: An LED driving apparatus for driving an LED array including an output terminal group and a converter group is provided. The output terminal group includes a plurality of output terminals. The converter group includes a plurality of digital-to-analog converters. Each of the digital-to-analog converters outputs a driving current according to pixel data to drive a corresponding one of the LEDs. Each of digital-to-analog converters includes a plurality of sub-driving current generating circuits. The sub-driving current generating circuits are coupled to the corresponding output terminal of the output terminal group. Each of the sub-driving current generating circuits generates a sub-driving current having a current value corresponding to a bit order of a bit of the pixel data. The driving current is generated by summing up the sub-driving currents.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventor: Sheng-Wen Hsiao
  • Patent number: 11082056
    Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 3, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Rares Bodnar, Asif Ahmad, Christopher Peter Hurrell
  • Patent number: 11056169
    Abstract: A system for comparing currents is disclosed. The system may include a first current signal and a second current signal. The system may also include a subtractor that is configured to receive a plurality of current input signals and generate a single output current signal that is equal to a difference between the plurality of current input signals. The system may also include a current-to-voltage converter that is configured to receive the output current signal and convert it into an output voltage.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: July 6, 2021
    Assignee: MENTIUM TECHNOLOGIES INC.
    Inventors: Farnood Merrikh Bayat, Jaroslaw Sulima, Mirko Prezioso
  • Patent number: 11038362
    Abstract: The present general inventive concept is directed to a signal generation system, device, and method for meter testing, including a digital signal generator to generate an arbitrary digital test signal, a digital-to-analog converter to convert the arbitrary digital test signal to an analog test signal, a signal converter to convert the analog test signal to a differential pair of signals corresponding to the analog test signal, and a power signal generator including: an input module to receive the differential pair of signals; an amplifier to amplify the differential pair of test signals; and an output module to output an output differential pair of signals to a load, to feed back a proportional representation of the output differential pair of signals to the input module, and to receive the amplified differential pair of signals from the amplifier.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 15, 2021
    Assignee: Technology for Energy Corporation
    Inventors: Kevin Christopher Omoumi, Allen Vaughn Blalock, Kai Bouse, Robert Stephen Hudson
  • Patent number: 11025229
    Abstract: A circuit includes a binary weighted divider having a first set of switches coupled in series between an input node and a feedback node. The first set of switches is configured to set a feedback voltage at the feedback node in response to activating or deactivating respective switches in the first set of switches. A set of compensation switches is coupled to the first set of switches. The set of compensation switches is configured to reduce resistance of one or more of the respective switches in the first set of switches that are activated by activating one or more switches in the set of compensation switches to provide one or more respective parallel current paths for each of the switches in the first set of switches that are activated.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Niko Bako, Stefan Reithmaier
  • Patent number: 11025267
    Abstract: The present technology relates to a DAC (Digital to Analog Converter) and an oscillation circuit that allow widening of a range of a voltage to be output from the DAC. A plurality of first switches is connected to a voltage-dividing resistor and each configured to output, as a first voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of first switches. A plurality of second switches is connected to the voltage-dividing resistor and each configured to output, as a second voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of second switches. The present technology can be applied to, for example, a VCO (Voltage-Controlled Oscillator) and the like that oscillates a signal with a frequency according to a voltage to be output from a DAC.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 1, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshinobu Kawasaki, Kentaro Yasunaka, Takashi Masuda
  • Patent number: 11025266
    Abstract: Embodiments of the present disclosure provide a digital-to-analog converter, a conversion circuit and a display device. An M-bit digital-to-analog converter includes a higher M?N-bit digital-to-analog conversion circuit, a voltage conversion circuit, an output circuit. The higher M?N-bit digital-to-analog conversion circuit includes: a higher M?N-bit voltage division generation circuit, a first voltage selection circuit. The first voltage selection circuit selects a first voltage from the higher M?N-bit voltage division generation circuit based on a higher M?N-bit digital signal, to be output from a first voltage end. The voltage conversion circuit charges a capacitor circuit under the control of a first switch circuit and a second switch circuit, and discharges a second voltage to a second voltage end through the capacitor circuit.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: June 1, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tangxiang Wang, Chen Song, Zhan Gao, Yi Chen
  • Patent number: 11011437
    Abstract: The present disclosure provides a method for determining a width-to-length ratio of a channel region of a thin film transistor (TFT). The method includes: S1, setting an initial width-to-length ratio of the channel region; S2, manufacturing a TFT by using a mask plate according to the initial width-to-length ratio; S3, testing the TFT manufactured according to the initial width-to-length ratio; S4, determining whether or not the test result satisfies a predetermined condition, performing S5 if the test result satisfies the predetermined condition, and performing S6 if the test result does not satisfy the predetermined condition; S5, determining the initial width-to-length ratio as the width-to-length ratio of the channel region of the TFT; S6, changing the value of the initial width-to-length ratio, adjusting a position of the mask plate according to the changed initial width-to-length ratio, and performing S2 to S4 again.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 18, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingbin Hu, Ce Zhao, Yuankui Ding, Wei Song, Jun Wang, Yang Zhang, Wei Li, Liangchen Yan