Digital To Analog Conversion Patents (Class 341/144)
  • Patent number: 11094248
    Abstract: An LED driving apparatus for driving an LED array including an output terminal group and a converter group is provided. The output terminal group includes a plurality of output terminals. The converter group includes a plurality of digital-to-analog converters. Each of the digital-to-analog converters outputs a driving current according to pixel data to drive a corresponding one of the LEDs. Each of digital-to-analog converters includes a plurality of sub-driving current generating circuits. The sub-driving current generating circuits are coupled to the corresponding output terminal of the output terminal group. Each of the sub-driving current generating circuits generates a sub-driving current having a current value corresponding to a bit order of a bit of the pixel data. The driving current is generated by summing up the sub-driving currents.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventor: Sheng-Wen Hsiao
  • Patent number: 11082056
    Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: August 3, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Rares Bodnar, Asif Ahmad, Christopher Peter Hurrell
  • Patent number: 11056169
    Abstract: A system for comparing currents is disclosed. The system may include a first current signal and a second current signal. The system may also include a subtractor that is configured to receive a plurality of current input signals and generate a single output current signal that is equal to a difference between the plurality of current input signals. The system may also include a current-to-voltage converter that is configured to receive the output current signal and convert it into an output voltage.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: July 6, 2021
    Assignee: MENTIUM TECHNOLOGIES INC.
    Inventors: Farnood Merrikh Bayat, Jaroslaw Sulima, Mirko Prezioso
  • Patent number: 11038362
    Abstract: The present general inventive concept is directed to a signal generation system, device, and method for meter testing, including a digital signal generator to generate an arbitrary digital test signal, a digital-to-analog converter to convert the arbitrary digital test signal to an analog test signal, a signal converter to convert the analog test signal to a differential pair of signals corresponding to the analog test signal, and a power signal generator including: an input module to receive the differential pair of signals; an amplifier to amplify the differential pair of test signals; and an output module to output an output differential pair of signals to a load, to feed back a proportional representation of the output differential pair of signals to the input module, and to receive the amplified differential pair of signals from the amplifier.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: June 15, 2021
    Assignee: Technology for Energy Corporation
    Inventors: Kevin Christopher Omoumi, Allen Vaughn Blalock, Kai Bouse, Robert Stephen Hudson
  • Patent number: 11025229
    Abstract: A circuit includes a binary weighted divider having a first set of switches coupled in series between an input node and a feedback node. The first set of switches is configured to set a feedback voltage at the feedback node in response to activating or deactivating respective switches in the first set of switches. A set of compensation switches is coupled to the first set of switches. The set of compensation switches is configured to reduce resistance of one or more of the respective switches in the first set of switches that are activated by activating one or more switches in the set of compensation switches to provide one or more respective parallel current paths for each of the switches in the first set of switches that are activated.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: June 1, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Niko Bako, Stefan Reithmaier
  • Patent number: 11025267
    Abstract: The present technology relates to a DAC (Digital to Analog Converter) and an oscillation circuit that allow widening of a range of a voltage to be output from the DAC. A plurality of first switches is connected to a voltage-dividing resistor and each configured to output, as a first voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of first switches. A plurality of second switches is connected to the voltage-dividing resistor and each configured to output, as a second voltage, a voltage at a corresponding one of connection points between the voltage-dividing resistor and the plurality of second switches. The present technology can be applied to, for example, a VCO (Voltage-Controlled Oscillator) and the like that oscillates a signal with a frequency according to a voltage to be output from a DAC.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 1, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshinobu Kawasaki, Kentaro Yasunaka, Takashi Masuda
  • Patent number: 11025266
    Abstract: Embodiments of the present disclosure provide a digital-to-analog converter, a conversion circuit and a display device. An M-bit digital-to-analog converter includes a higher M?N-bit digital-to-analog conversion circuit, a voltage conversion circuit, an output circuit. The higher M?N-bit digital-to-analog conversion circuit includes: a higher M?N-bit voltage division generation circuit, a first voltage selection circuit. The first voltage selection circuit selects a first voltage from the higher M?N-bit voltage division generation circuit based on a higher M?N-bit digital signal, to be output from a first voltage end. The voltage conversion circuit charges a capacitor circuit under the control of a first switch circuit and a second switch circuit, and discharges a second voltage to a second voltage end through the capacitor circuit.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: June 1, 2021
    Assignee: BOE Technology Group Co., Ltd.
    Inventors: Tangxiang Wang, Chen Song, Zhan Gao, Yi Chen
  • Patent number: 11011437
    Abstract: The present disclosure provides a method for determining a width-to-length ratio of a channel region of a thin film transistor (TFT). The method includes: S1, setting an initial width-to-length ratio of the channel region; S2, manufacturing a TFT by using a mask plate according to the initial width-to-length ratio; S3, testing the TFT manufactured according to the initial width-to-length ratio; S4, determining whether or not the test result satisfies a predetermined condition, performing S5 if the test result satisfies the predetermined condition, and performing S6 if the test result does not satisfy the predetermined condition; S5, determining the initial width-to-length ratio as the width-to-length ratio of the channel region of the TFT; S6, changing the value of the initial width-to-length ratio, adjusting a position of the mask plate according to the changed initial width-to-length ratio, and performing S2 to S4 again.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: May 18, 2021
    Assignees: HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yingbin Hu, Ce Zhao, Yuankui Ding, Wei Song, Jun Wang, Yang Zhang, Wei Li, Liangchen Yan
  • Patent number: 11005492
    Abstract: A signal source device includes at least one digital-to-analog converter, at least one connector, a first output path from the at least one digital-to-analog converter to the at least one connector, and a second output path from the at least one digital-to-analog converter to the at least one connector. A method of generating a analog signal includes generating at least one analog signal from at least one digital-to-analog converter, transmitting a first analog signal of the at least one analog signal along a first output path from the at least one digital-to-analog converter to at least one connector, and transmitting a second analog signal of the at least one analog signal along a second output path from the at least one digital-to-analog converter to the at least one connector.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: May 11, 2021
    Assignee: Tektronix, Inc.
    Inventors: Gregory A. Martin, Pirooz Hojabri
  • Patent number: 11005494
    Abstract: A DAC driver includes a number of DAC drivers coupled to a load network. A first DAC driver includes a first set of data switches that can be controlled by a first digital input signal. The first DAC driver further includes a first set of output switches, a first set of dump switches and a first set of current sources. Another DAC driver includes a second set of output switches, dump switches, and current sources. The first set of output switches or the second set of output switches are operable to respectively couple either one of the first set of data switches or the first set of current sources to the load network. The first set of dump switches or the second set of dump switches are operable to respectively dump the first set of current sources or the second set current sources into a respective dump load.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: May 11, 2021
    Assignee: Jariet Technologies, Inc.
    Inventors: Ark-Chew Wong, Richard Dennis Alexander
  • Patent number: 10996732
    Abstract: A power supply has a reference regulation circuit and a voltage regulator. The reference regulation circuit receives a VID code and a slew rate command from a processor and regulates a reference voltage based on the VID code and the slew rate command. The voltage regulator converts an input voltage to an output voltage based on the reference voltage. The circuit has a ?-? modulation unit to generate a count duration signal based on a target count signal, wherein the target count signal is generated by dividing a voltage regulation step by the slew rate command, both the target count signal and the count duration signal are digital signals, the target count signal represents a real number having an integer part and a decimal part, the count duration signal represents an integer number, the circuit further regulates the reference voltage based on the count duration signal and the VID code.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: May 4, 2021
    Assignee: Chengdu Monolithic Power Systems Co., Ltd.
    Inventors: Suhua Luo, Lijie Jiang
  • Patent number: 10985954
    Abstract: A data transmission device includes first and second lines, and a transmitter configured to convert received binary data into ternary data and output the ternary data onto the first and second lines by toggling only one of the first and second lines during each of a plurality of consecutive 2-bit data transmission time intervals. A receiver is also provided, which is configured to receive the ternary data from the first and second lines and convert the received ternary data into binary data. The transmitter is configured to output the ternary data onto the first and second lines using return-to-zero toggling during each of the 2-bit data transmission time intervals.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: April 20, 2021
    Inventor: Young-Hwa Kim
  • Patent number: 10985768
    Abstract: A ultra-high speed DAC apparatus (e.g., with a full sampling frequency not less than 20 GHz) may include one or more digital pre-coders and DAC modules. Each DAC module may include multiple current-mode DAC systems and a first power combiner. The gate length of transistors within each DAC module may be between 6 and 40 nm. Each current-mode DAC system includes a transmission line (e.g., 40 to 80 microns long) coupled to multiple interleaving sub-DAC systems (within the current-mode DAC systems) and the first power combiner. The first power combiner combines, without interleaving, analog signals that have been interleaved within the current-mode DAC systems. The impedance of the first power combiner matches the impedance of each of the current-mode DAC systems and a load of the first power combiner. A second power combiner combines, without interleaving, analog signals from the DAC modules.
    Type: Grant
    Filed: August 11, 2020
    Date of Patent: April 20, 2021
    Assignee: JARIET TECHNOLOGIES, INC.
    Inventors: Ark-Chew Wong, Richard Dennis Alexander, Craig A. Hornbuckle
  • Patent number: 10979068
    Abstract: A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: April 13, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Yi-Hung Tseng, Karthik Nagarajan
  • Patent number: 10971397
    Abstract: A method of fabricating a semiconductor device includes the following steps. A substrate is provided. The substrate includes a pixel region having a first conductive region and a logic region having a second conductive region. A dielectric layer is formed on the substrate to cover the first conductive region. A first contact opening is formed in the dielectric layer to expose the first conductive region. A doped polysilicon layer is sequentially formed in the first contact opening. A first metal silicide layer is formed on the doped polysilicon layer. A second contact opening is formed in the dielectric layer to expose the second conductive region. A barrier layer and a metal layer are respectively formed in the first contact opening and the second contact opening.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: April 6, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chih-Kai Hsu, Ssu-I Fu, Chia-Jung Hsu, Chun-Ya Chiu, Chin-Hung Chen, Yu-Hsiang Lin
  • Patent number: 10970041
    Abstract: A list of digital elements to be sorted are converted to a group of analog signals. The group of analog signals are simultaneously compared to each other to determine the largest analog signal in the group. The largest analog signal is then compared to each of the analog signals in the group to determine which one or more of the analog signals in the group matches the largest analog signal. The matching one or more of the analog signals is removed from the group and the process is repeated until the group of analog signals have been sorted.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: April 6, 2021
    Assignees: AT&T Intellectual Property I, L.P., AT&T Mobility II LLC
    Inventors: Sheldon K. Meredith, William C. Cottrill
  • Patent number: 10964378
    Abstract: Embodiments of the disclosure are drawn to apparatuses, systems, and methods for analog row access rate determination. Accesses to different row addresses may be tracked by storing one or more received addresses in a slice of stack. Each slice includes an accumulator circuit which provides a voltage based on charge on a capacitor. When a row address is received, it may be compared to the row addresses stored in the stack, and if there is a match, the charge on the capacitor in the associated accumulator circuit is increased. Each slice may also include a voltage to time (VtoT) circuit which may be used to identify the highest of the voltages provided by the accumulator circuits. The row address stored in the slide with the highest voltage may be refreshed.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sujeet Ayyapureddi, Raghukiran Sreeramaneni
  • Patent number: 10965302
    Abstract: Digital to analog conversion generates an analog output corresponding to a digital input by controlling unit elements or cells using data bits of the digital input. The unit elements or cells individually make a contribution to the analog output. Due to process, voltage, and temperature variations, the unit elements or cells may have mismatches. The mismatches can degrade the quality of the analog output. To extract the mismatches, a transparent dither can be used. The mismatches can be extracted by observing the analog output, and performing a cross-correlation of the observed output with the dither. Once extracted, the unit elements or cells can be adjusted accordingly to reduce the mismatches.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 30, 2021
    Assignee: ANALOG DEVICES INTERNATIONAL UNLIMITED COMPANY
    Inventors: Jialin Zhao, Hajime Shibata, Gil Engel
  • Patent number: 10963991
    Abstract: An information processing device according to the present invention includes a memory; and at least one processor coupled to the memory. The processor performing operations. The operations includes: receiving first multiple-images; and generating, based on a first image in the first multiple-images, a third image relating to a second image in a second wavelength band different from a first wavelength band of the first image.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: March 30, 2021
    Assignee: NEC Corporation
    Inventor: Eiji Kaneko
  • Patent number: 10958858
    Abstract: Disclosed are devices, systems and methods for allowing a ramp signal generator to reduce noise. A ramp signal generator may include a reference voltage generator configured to generate a reference voltage, a gain controller configured to control a gain of the reference voltage, a ramp signal controller configured to generate a ramp signal in response to an output signal of the gain controller, and an offset controller coupled to an output terminal of the gain controller in the form of a current mirror, and control an offset of the ramp signal in response to a control signal.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: March 23, 2021
    Assignee: SK hynix Inc.
    Inventors: Jin Seon Kim, Min Seok Shin
  • Patent number: 10948355
    Abstract: A high-resolution thermopile infrared sensor array having monolithically integrated signal processing and a plurality of parallel signal processing channels for the signals from pixels of a sensor array, and a digital port for the serial output of the pixel signals are provided, wherein the sensor array is located on one or more sensor chips. The thermal piled infrared sensor array possesses low power loss, high integration density and high thermal and geometric resolution. Each signal processing channel (K1 . . . KN) has at least one analogue/digital converter (ADC), and is assigned a memory region in a memory (RAM) for storing the signals from the pixels (SE).
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: March 16, 2021
    Assignee: HEIMANN SENSOR GMBH
    Inventors: Bodo Forg, Michael Schnorr, Jörg Schieferdecker, Karlheinz Storck, Marion Simon, Wilhelm Leneke
  • Patent number: 10951226
    Abstract: A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: March 16, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srinivasa Rao Madala, Rahul Sharma, Sandeep Kesrimal Oswal
  • Patent number: 10938404
    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter comprises an input configured to receiving a first digital control code for controlling a plurality of digital-to-analog converter cells. Further, the digital-to-analog converter comprises a code converter circuit configured to converter the first digital control code to a second digital control code. Further, the digital-to-analog converter comprises a shift code generation circuit configured to generate a shift code based on a code difference between the first digital control code and a third digital control code. The digital-to-analog converter additionally comprises a bit-shifter circuit configured to bit-shift the second digital control code based on the shift code in order to obtain a modified second digital control code.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 2, 2021
    Assignee: Intel Corporation
    Inventors: Ramon Sanchez, Kameran Azadet, Martin Clara, Daniel Gruber
  • Patent number: 10917127
    Abstract: A radio frequency transmitter includes a digital-to-analog converter, a passive network, two buffers, a frequency mixer, and a power amplifier. Two output ends of the digital-to-analog converter are respectively coupled to two input nodes of the passive network, and the two output ends of the digital-to-analog converter are respectively coupled to input ends of the two buffers. Output ends of the two buffers are respectively coupled to two input ends of the frequency mixer. An output end of the frequency mixer is coupled to an input end of the power amplifier. An output end of the power amplifier is coupled to an antenna. The passive network is configured to perform filtering processing on an input current signal, and convert the current signal into a voltage signal.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: February 9, 2021
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Zemin Feng, Chenlong Hou
  • Patent number: 10911059
    Abstract: A signal processing system includes an analog-to-digital converter (ADC) that is used to convert a first analog value into a first digital value and convert a second analog value into a second digital value. The ADC includes a first digital-to-analog converter (DAC) circuit and a second DAC circuit operating in different voltage domains. A first bit segment and a second bit segment of each digital value are determined via the first DAC circuit and the second DAC circuit, respectively. An analog injection value is injected to the second analog value, the analog injection value is converted from a digital injection value formed by a subset of bits of the second bit segment of the first digital value, and the second bit segment of the second digital value is derived from injecting the digital injection value to a digital value determined by the second DAC circuit.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: February 2, 2021
    Assignee: MEDIATEK INC.
    Inventors: Wei-Hsiang Huang, Yun-Shiang Shu, Su-Hao Wu
  • Patent number: 10892935
    Abstract: A wideband, linear, direct-digital RF modulator (DDRM) for a digitally-intensive transmitter (DTX) includes an interpolation filter and an in-phase/quadrature (I/Q)-interleaving RF digital-to-analog converter (RF-DAC). The interpolation filter suppresses sampling replicas in the DDRM's output RF spectrum. I/Q interleaving performed by the interleaving RF-DAC avoids problems associated with using two separate I- and Q-path RF-DACs. Each unit cell of the interleaving RF-DAC is capable of producing four unique non-overlapping waveforms covering all four quadrants of the I/Q signal plane. In one embodiment of the invention, the interleaving RF-DAC includes three parallel-connected RF-DACs operating in accordance with a multi-phase set of LO clocks to both cancel 3rd-order and 5th-order LO harmonics generated by the RF-DAC unit cells' interleaving logic and prevent 3rd-order intermodulation from occurring in the DTX's final stage RF power amplifier.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: January 12, 2021
    Assignee: Technische Universiteit Delft
    Inventors: Mohammed Reza Mehrpoo, Leonardus Cornelis Nicolaas de Vreede, Seyed Morteza Alavi
  • Patent number: 10892767
    Abstract: A circuit for high accuracy element matching is provided. The circuit includes an analog to digital converter (ADC) configured to generate an output code. A current source is configured to provide a signal to the ADC. The current source includes a first current branch including a first unit element group having a first unit element coupled by way of a first set of switches to a first node and a second node and a second unit element coupled by way of a second set of switches to the first node and the second node. A second current branch includes a second unit element group having a third unit element coupled by way of a third set of switches to the first node and the second node and a fourth unit element coupled by way of a fourth set of switches to the first node and the second node. A control circuit is configured to provide control signals to the sets of switches based on the output code. The control circuit is further configured to sort unit element currents and to dynamically switch unit elements.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: January 12, 2021
    Assignee: NXP USA, INC.
    Inventors: Tao Chen, Robert S. Jones, III
  • Patent number: 10879923
    Abstract: Methods and systems to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a current mode digital-to-analog converter (DAC) configured to multiply an input signal with an input current to generate a signal. The device can further include a current divider coupled to the current mode DAC. The current divider can be configured to divide the signal into at least a first current having a first amplitude and a second current having a second amplitude. The device can further include a mixer configured to multiply the second current with a clock signal to generate a third current. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 10868555
    Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: December 15, 2020
    Assignee: NXP B.V.
    Inventors: Vladislav Dyachenko, Erwin Janssen, Yu Lin, Athon Zanikopoulos
  • Patent number: 10862506
    Abstract: The present disclosure relates to an encoder and an encoding method thereof, as well as a decoder and a decoding method thereof, which can be used to reduce the number of wires necessary for data transmission and transmit more data at a faster speed with the same number of wires, thereby improving the efficiency of data transmission. The encoder may comprises two input terminals configured to receive two input signals simultaneously, each input terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage; and a plurality of output terminals, wherein each output terminal comprises a wire identifying a positive voltage and a wire identifying a negative voltage, a combination of the two input signals corresponds to one of the plurality of output terminals, and the output terminal to which the current combination of the two input signals corresponds is configured to output signals through the two wires of the output terminal.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: December 8, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Lei Dai, Taehyun Kim
  • Patent number: 10861375
    Abstract: A method of operating a source driver, a display driving circuit, and a method of operating the display driving circuit are provided. The method of operating the source driver including a receiver, includes determining a parameter value of the receiver for optimizing a receiving of the receiver, through training, and transmitting the parameter value to a timing controller external to the source driver. The method of operating the source driver further includes, based on an abnormal state occurring in the receiving of the receiver, receiving the transmitted parameter value from the timing controller, and optimizing the receiving of the receiver based on the received parameter value.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: December 8, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-wook Lim, Kwi-sung Yoo, Young-min Choi, Jae-youl Lee, Dong-hoon Baek, Kyong-ho Kim, Eun-young Jin
  • Patent number: 10862500
    Abstract: Apparatus and associated methods relate to maintaining a total current of a switch cell in a digital-to-analog converter at a controllable operating point by adjusting shunt current control signals applied to programmable shunt current sources in opposite polarity with respect to a tail current control signal applied to a programmable tail current source. In an illustrative example, the total current may flow through differential legs of a switch cell. The programmable shunt current sources may, for example, be configured to compensate for adjustments to the programmable tail current source. In an illustrative example, tail current and shunt currents may flow through a pair of cascode transistors. In various examples, controlling the programmable shunt current sources to compensate adjustments to the tail current source may, for example, permit controlled common mode voltage or operating point so as to reduce device voltage stress over a wider dynamic range of output voltages.
    Type: Grant
    Filed: November 14, 2019
    Date of Patent: December 8, 2020
    Assignee: XILINX, INC.
    Inventors: Roberto Pelliconi, Bob Verbruggen, Brendan Farley, Christophe Erdmann
  • Patent number: 10854267
    Abstract: Virtual ground sensing circuits, control circuit, electrical systems, computing devices, and related methods are disclosed. A control circuit includes a virtual ground sensing circuit configured to provide a virtual ground to a conductive line. The virtual ground sensing circuit is further configured to selectively operably couple the conductive line to a sense node of a sense circuit, wherein the sense node having a sense node capacitance less than a capacitance of the conductive line. Further, virtual ground sensing circuit is configured to compare a sense node voltage to a reference voltage.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: December 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Giulio Giuseppe Marotta, Marco Domenico Tiburzi
  • Patent number: 10854127
    Abstract: A gamma voltage generator includes a reference gamma selecting circuit that receives first and second reference voltages and selects an upper reference gamma voltage (e.g., corresponding to a maximum gamma tab voltage among voltages between the first and second reference voltages) and a lower reference gamma voltage (e.g., corresponding to a minimum gamma tab voltage among the voltages) based on a dimming level, a bias control circuit that calculates the minimum gamma tab voltage based on the upper and lower reference gamma voltages and outputs bias control signals when the minimum gamma tab voltage is less than a reference voltage, a gamma tab voltage generating circuit that generates gamma tab voltages between the minimum and maximum gamma tab voltages based on the upper and lower reference gamma voltages, and a gamma output circuit that distributes the gamma tab voltages to output gamma voltages corresponding to a gamma curve.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventor: Jinyoung You
  • Patent number: 10855300
    Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to generate an analog cell output signal based on a drive signal. The at least one of the plurality of digital-to-analog converter cells further includes a driver circuit configured to generate the drive signal, and a resistive element exhibiting a resistance of at least 20?. The resistive element is coupled between the driver circuit and the capacitive element or between the capacitive element and the output node.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: December 1, 2020
    Assignee: MaxLinear, Inc.
    Inventors: Daniel Gruber, Franz Kuttner, Davide Ponton, Kameran Azadet, Hundo Shin, Martin Clara, Matej Kus
  • Patent number: 10847068
    Abstract: A method of operating a display device comprising a drive circuit is disclosed. The drive circuit comprises a plurality of single grey-level channels, each comprising an input (412, 422), an output (418, 428) and a signal processor connected between the input and output. Each signal processor comprises a digital-to-analog converter (414, 424) and an operational amplifier (416, 426) having a voltage offset. The method comprises: converting a digital signal received at the input (412, 422) into an analog voltage (410, 420) at the output (418, 428) using each respective signal processor; switching between the analog voltage (410, 420) of each single grey-level channel using a switching circuit (430); receiving and analysing the analog voltages (410, 420) in a calibration subsystem (440), and individually compensating for the voltage offset of each op-amp (416, 426) based on the received analog voltage (410, 420) for that grey-level channel using the calibration subsystem (440).
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 24, 2020
    Assignee: Dualitas Ltd
    Inventor: Jamieson Christmas
  • Patent number: 10848172
    Abstract: An IC can include shared reference voltage buffer circuitry having an amplifier circuit. A commonly-routed amplifier shared output voltage node can be shared between at least two digital-to-analog converters (DACs) respectively via at least first and second individually routed traces from the shared output voltage node to respective first and second local reference voltage nodes at the DACs. Respective first and second routing trace resistances can be based on current draw of the corresponding DAC, such as to provide an equal voltage drop across the first and second routing resistances. This can help avoid voltage contention or conflict at the shared output voltage node from forcing/sensing the voltages at the first and second local reference voltage nodes. In a further example, at least one of the first and second individually routed traces can include a binary tree hierarchical routing arrangement of at least some of the DACs.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: November 24, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Kirubakaran Ramalingam, Ayan Das, Hrishikesh Ravi Mathukkarumukku, Mahesh Madhavan Kumbaranthodiyil
  • Patent number: 10848167
    Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: November 24, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10840929
    Abstract: Certain aspects of the present disclosure are directed to a digital-to-analog converter (DAC) system. The DAC system generally includes a first current-steering DAC having a positive output, a negative output, and a bypass output; a common-mode (CM) path coupled between the positive and negative outputs; and a CM current compensation path coupled to the CM path.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: November 17, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Weil, Jaswinder Singh, Debesh Bhatta, Haibo Fei
  • Patent number: 10840941
    Abstract: A signal converter includes a first converter, a second converter, a signal generator, and a controller. The first converter generates a first analog signal from a digital signal, and the second converter generates a second analog signal from the digital signal. The signal generator outputs a converted analog signal based on the first analog signal and the second analog signal. The controller generates one or more control signals to change a power supply state of at least one of the first converter and the second converter. The change in power supply state suppress even order harmonics.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 17, 2020
    Assignee: NXP B.V.
    Inventors: Muhammad Kamran, Harry Neuteboom
  • Patent number: 10840930
    Abstract: A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Texas Instruments Incorporated
    Inventor: Jun Zhang
  • Patent number: 10831231
    Abstract: A circuit for implementing a polar decoder is described. The circuit includes a log-likelihood ratio processing circuit. A path metric update circuit is coupled to receive log-likelihood values for decoded bits from the log-likelihood ratio processing circuit, wherein the path metric circuit generates path metric values for the decoded bits. A partial sum calculation circuit is coupled to receive the path metrics; and a sort and cull circuit is coupled to receive a list of child path, wherein the sort and cull circuit eliminates invalid paths from the list of child paths. A method of implementing a polar decoder is also described.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: November 10, 2020
    Assignee: XILINX, INC.
    Inventor: Gordon I. Old
  • Patent number: 10833700
    Abstract: Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: November 10, 2020
    Assignee: Micron Technology, Inc
    Inventor: Vijay S. Ramesh
  • Patent number: 10833699
    Abstract: A digital to analog converter that includes a delta sigma modulator coupled to receive a digital data. The delta sigma modulator supplies a multi-bit resistor digital to analog converter (DAC). The multi-bit resistor digital to analog converter supplies an amplifier with an analog signal corresponding to the digital data. A first low pass filter is coupled between the multi-bit digital to analog converter and the amplifier stage and filters out shaped quantization noise before it reaches the amplifier. A second low pass filter is coupled to an output of the amplifier stage and filters out residual quantization noise and chopping artifacts from the amplifier stage.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 10, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: Dinesh Babu Mugunthu Maheswaran
  • Patent number: 10833697
    Abstract: Circuits and methods for converting digital input signals into the analog domain are described. Such circuits may perform the conversion in a segmented fashion. For example, a circuit may include a most significant bit (MSB) path and a least significant bit (LSB) path. The MSB path may include a first delta-sigma modulator having first and second outputs and a first digital-to-analog converter coupled to the first output of the first delta-sigma modulator. The LSB path comprises a second delta-sigma modulator comprising a loop filter and a quantizer. The quantizer may have an input coupled to the loop filter and to the digital filter. The LSB path may further include a second digital-to-analog converter coupled to an output of the quantizer. The circuit may further include a digital filter and/or a gain stage interposed between the MSB path and the LSB path.
    Type: Grant
    Filed: September 3, 2019
    Date of Patent: November 10, 2020
    Assignee: MEDIATEK Singapore Pte. Ltd.
    Inventors: Ayman Shabra, Stacy Ho, Michael A. Ashburn, Jr.
  • Patent number: 10826525
    Abstract: Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications.
    Type: Grant
    Filed: January 19, 2020
    Date of Patent: November 3, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10819315
    Abstract: A voltage mode signal transmitter includes a front-end signal processor and a signal transformer. The front-end signal processor receives a first and second data signal, and delays and inverts the data signals to generate a third and fourth data signal. The front-end signal processor selects two of the first data signal to the fourth data signal to generate a plurality of signal pairs according to a first control signal. The signal transformer selects one data signal of each of the signal pairs to generate input voltages according to a second control signal, and generates an output voltage according to the input voltages. A working frequency of the first control signal is lower than a working frequency of the second control signal.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 27, 2020
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Hsu Chien, Yen-Chung T. Chen, Cho-Ru Yang
  • Patent number: 10819364
    Abstract: A radiation hardened, digital to analog converter includes first and second serial communication circuits, a common bus interface configured to connect the first and second serial communication circuits to first and second digital serial communication buses, respectively, and a digital to analog converter circuit, where the first and second serial communication circuits are configured to receive data over the first and second digital serial communication buses, respectively, for use by the digital to analog converter circuit.
    Type: Grant
    Filed: July 17, 2019
    Date of Patent: October 27, 2020
    Assignee: United States of America as represented by the Adminstrator of NASA
    Inventors: George Suarez, Jeffrey Dumonthier, Nikolaos Paschalidis
  • Patent number: 10812098
    Abstract: An analog-to-digital converter (ADC) includes a capacitive digital-to-analog converter (CDAC), a comparator, and a successive approximation register (SAR) control circuit. The comparator is coupled to an output of the CDAC. The SAR control circuit is coupled to an output of the comparator and to an input of the CDAC. The SAR control circuit includes a flip-flop. The flip-flop includes a clock input terminal, a data input terminal, and an output. The clock input terminal is coupled to the output of the comparator. The data input terminal coupled to a constant voltage source. The flip-flop can include an enable input terminal coupled to a SAR state circuit. The output is coupled to the CDAC.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: October 20, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ramamurthy Vishweshwara, Pramod Kumar Baskar
  • Patent number: 10804928
    Abstract: A DA conversion device includes a level determiner determining whether a level of the digital signal or the analog signal is higher than a predetermined threshold value; a DA converter including plural capacitors, an operational amplifier which generates the analog signal, and a plurality of transistors which connects each of the plural capacitors to a first or a second reference voltage according to the digital signal in a first connection state and connects the plural capacitors between an input terminal and an output terminal of the operational amplifier in a second connection state; and a setting part which receives a clock signal and sets gate-source voltages of the plurality of transistors such that the plurality of transistors is in the first connection state in a first period of the clock signal and the plurality of transistors is in the second connection state in a second period of the clock signal.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: October 13, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Naoto Tamura