Abstract: A digital-to-analog converter and an operation method thereof are provided. The digital-to-analog converter includes a current source module, a decoder, a change indicator, and a random number generator. The decoder is coupled to the current source module and receives a digital input signal. The change indicator is coupled to the decoder and provides an indication signal to the decoder. The random number generator is coupled to the change indicator and provides a random number signal to the change indicator. The change indicator generates an indication signal according to the random number signal, and the decoder generates a control signal to the current source module according to the digital input signal and the indication signal, so that the current source module generates an analog output signal corresponding to the digital input signal according to the control signal.

Abstract: Embodiments of the disclosure provide improved mismatch shaping for a digital to analog converter, the method including splitting an original input of a circuit into a plurality of time interleaved data streams; element rotation selection (ERS) logic to process the plurality of time interleaved data streams; and directing one of the plurality of time interleaved data streams to the ERS logic according to a decision of a data-weighted sigma-delta (SD) modulator. In other example implementations, the method can further include multiplexing one of the plurality of time interleaved data streams to be provided to a barrel shifter. In yet other examples, the method can include monitoring a difference between the plurality of time interleaved data streams as a basis for the directing such that a data sample rate for the digital to analog converter is reduced over a time interval.

Abstract: An electronic device may include digital circuitry to operate via digital signals and analog circuitry to operate via analog signals. The electronic device may also include a fractal digital to analog converter (DAC) to convert a digital signal into an analog signal. The fractal DAC may include a unit cell array having a branching data path and multiple unit cells disposed in a fractal pattern. The fractal DAC may also include multiple decision units disposed within the unit cell array on the branching data path. Each decision unit may receive an incoming signal representative of at least a portion of the digital signal and direct each decision unit output to different branches of the unit cell array. The unit cells may be enabled based at least in part on the decision unit outputs to generate the analog signal.

Abstract: A transmission circuit according to an embodiment includes: a plurality of constant current circuits, a plurality of switching elements, and controlling circuitry. The plurality of constant current circuits are connected in parallel to a power source line connected to a single power source and a transducer element. Each of the plurality of switching elements is connected to a different one of the plurality of constant current circuits and to the transducer element. The controlling circuitry is configured to control the plurality of switching elements on the basis of a waveform signal indicating a waveform of an ultrasound wave output from the transducer element.

Abstract: A device including at least one processor, and an analog-to-digital (ADC) circuit, wherein the at least one processor is configured to generate an excitation signal and provide the excitation signal to a crystal in a pierce oscillation configuration, wherein after providing the excitation signal, the ADC circuit is configured to obtain as input a signal output from the crystal and convert the signal to a digital output; the at least one processor is configured to compare the digital output of the ADC circuit to a plurality of thresholds and based on the comparisons is further configured to drive the crystal to cause the crystal to operate as a pierce oscillator and to generate a clock signal from at least of one of the comparisons.

Abstract: A digital slope analog to digital converter includes a charge injection digital to analog converter (DAC) circuit, a comparator circuit, a detector circuit, and a control logic circuitry. The charge injection DAC circuit respectively samples input signals via first and second capacitors and generates a first signal via the first capacitor and a second signal via the second capacitor. The comparator circuit compares the first signal with the second signal to generate decision signals. The detector circuit generates a flag signal according to the decision signals. The control logic circuitry generates an enable signal according to the flag signal and generates a digital output when the comparator circuit detects a crossing point of the first and second signals. The charge injection DAC circuit gradually adjusts charges stored in the first and/or the second capacitor according to the enable signal until the crossing point is detected.

Abstract: An example apparatus includes: resistor ladder circuitry including a plurality of intermediate voltage nodes; a first plurality of switches having inputs coupled to a plurality of intermediate voltage nodes and having outputs; first level decoder circuitry configured to: receive a set of input bits; and open or close ones of the first plurality of switches based on a first subset of the input bits; a second plurality of switches having inputs coupled to the outputs of the first plurality of switches and having outputs coupled to a common node; and second level decoder circuitry configured to: receive the set of input bits; and open or close ones of the second plurality of switches based on a second subset of the input bits, the first and the second subsets sharing one of the input bits, wherein the output voltage is to be coupled to the common node.

Abstract: The present disclosure provides a transmitter, a transceiver and a signal transmission method thereof. The transmitter comprises a signal amplification module, a balun and a feedback current generation module; the signal amplification module is configured to receive an input signal, amplify the input signal and output a differential signal to the balun; the balun is configured to receive the differential signal and convert the differential signal into a single-ended signal; and the feedback current generation module is configured to form electromagnetic coupling with the balun to generate a feedback current signal, wherein the feedback current signal is used as an input signal to a receiver.

Abstract: Methods and apparatus for adaptively adjusting a resistance of a resistor network in a digital-to-analog converter (DAC), such as a current-steering DAC for a transmit chain. An example DAC generally includes a plurality of DAC cells. One or more of the DAC cells generally includes a current source and a resistor network. The resistor network includes a plurality of resistive elements, has an adjustable resistance, and is coupled between a power supply rail and the current source. In this manner, the DAC may support a wide range of full-scale currents, while maintaining a higher degeneration voltage and reduced noise and mismatch for a given headroom. For certain aspects, the one or more of the DAC cells further include a plurality of switches (e.g., implemented with PFETs) coupled to one or more of the resistive elements and configured to adjust the resistance of the resistor network.

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a delay circuit configured to iteratively delay a digital input signal based on a clock signal for generating a plurality of delayed digital input signals. Further, the digital-to-analog converter includes a plurality of groups of inverter cells. Each group of inverter cells is configured to generate a respective analog signal based on one of the plurality of delayed digital input signals. The inverter cells includes a respective inverter circuit configured to invert the respective delayed digital input signal. The plurality of groups of inverter cells include different numbers of inverter cells. The digital-to-analog converter additionally includes an output configured to output an analog output signal based on the analog signals of the plurality of groups of inverter cells.

Abstract: A digital-to-analog converter may include an integrator, an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator, and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables an even number of members at a time, with half of such enabled members in a first group and half of such enabled members in a second group.

Abstract: A digital-to-analog converter includes a current cell array including a plurality of current cells, each current cell of the plurality of current cells being configured to generate a current of a same magnitude; a first pattern connecting first current cells, among the plurality of current cells, arranged along a diagonal line of the current cell array; a second pattern connecting second current cells, among the plurality of current cells, arranged along a first oblique line parallel to the diagonal line; and a third pattern connecting third current cells, among the plurality of current cells, arranged along a second oblique line parallel to the diagonal line, the third pattern being electrically connected to the second pattern, wherein the diagonal line is between the first oblique line and the second oblique line.

Abstract: A circuit includes a digital-to-analog converter (DAC) and a compensation circuit. The DAC has first and second terminals. The compensation circuit includes a capacitor and a transistor. The capacitor has first and second terminals, with the first terminal of the capacitor coupled to the first terminal of the DAC. The transistor has a source coupled to the second terminal of the capacitor, and has a gate coupled to the second terminal of the DAC.

Abstract: A circuit that receives a series a digital signal values from a digital circuit output where the output has a propensity to produce digital values with a metastable error. The circuit produces an analog output signal having values over time corresponding to the digital signal values. The circuit includes two data paths that receive the digital signal values and produce a delayed analog signal. One data path includes an analog delay and the other data path includes a digital delay and a digital to analog converter. The circuit uses the output of the two data paths to adjust a later output analog signal value that is produced by the analog circuit output subsequent to a former output analog signal value produced by the analog circuit output that corresponds to a digital signal value of the series with a metastable error to compensate for the metastable error in the output signal.

Abstract: An example apparatus includes: a voltage-to-current circuit including a first input terminal, a first output terminal and a second output terminal, a subtraction circuit including a second input terminal and a third output terminal, the second input terminal coupled to the second output terminal, a first driver circuit including a third input terminal and a fourth output terminal, the third input terminal coupled to the third output terminal, and a second driver circuit including a fourth input terminal and a fifth output terminal, the fourth input terminal coupled to the first output terminal, the fifth output coupled to the fourth output terminal.

Abstract: A dual source driver includes first and second gamma voltage generators configured to generate first and second gamma voltages, respectively, first and second latches configured to latch first and second data, respectively, a first driving cell configured to receive the first gamma voltage and the first data, and to transmit a first voltage corresponding to the first data and the first gamma voltage to a panel load based on a first switching operation, and a second driving cell configured to receive the second gamma voltage and the second data, and to transmit a second voltage corresponding to the second data and the second gamma voltage to the panel load based on a second switching operation. The first switching operation and the second switching operation may operate complementarily to each other.

Abstract: A calibration system comprises an actuator circuit comprising a first delay circuit that receives a plurality of data pulses and a second delay circuit that receives the pulses, wherein one of the first and second delay circuits delays the data pulses independently of the other of the first and second delay circuits; a data switch that receives an output of the actuator circuit including delay data signals of the data pulses from the first and second delay circuits and switches and outputs a plurality of local oscillator (LO) signals for output as a controlled LO signal according to control signals of the delay data signals and applied to the data switch. At least one calibration switch receives the output of the actuator circuit and the plurality of LO+ and LO? signals, and outputs a second controlled LO signal output to a sense circuit.

Abstract: A system includes a first integrated circuit device, a second integrated circuit device, and a reference clock provided to the first and second integrated circuit devices. The first integrated circuit device detects a first edge of a first clock utilized by the first integrated circuit device, detects a second edge of the first clock, determines a first count of cycles of the reference clock between the first edge and the second edge, and communicates the first count to the second integrated circuit device. The second integrated circuit device receives the first count, provides a third edge of a second clock utilized by the second integrated circuit device, determines that a first number of cycles of the reference clock since providing the third edge is equal to the first count, and provides a fourth edge of the second clock in response to determining that the first number of cycles is equal to the first count.

Abstract: A digital-to-analog converter is provided. The digital-to-analog converter includes a plurality of digital-to-analog converter cells coupled to an output node of the digital-to-analog converter. At least one of the plurality of digital-to-analog converter cells includes a capacitive element configured to provide an analog output signal of the digital-to-analog converter cell to the output node. Further, the at least one of the plurality of digital-to-analog converter cells includes an inverter circuit coupled to the capacitive element. The inverter circuit is configured to generate an inverter signal for the capacitive element based on an oscillation signal. The at least one of the plurality of digital-to-analog converter cells additionally includes a resistive element coupled to the inverter circuit and the capacitive element. A resistance of the resistive element is at least 50?.

Abstract: A voltage ladder is used to generate reference voltages. The voltage ladder is used by multiple digital-to-analog converters (DACs). In particular, the voltage ladder is used by multiple pulse-width modulation (PWM) DACs. Having multiple DACs utilize a common voltage ladder for their reference voltages reduces mismatched output voltages between DACs. Having multiple DACs utilize the common voltage ladder helps ensure that the reference voltages used by different DACs are not affected by process, voltage, and/or temperature variations in the reference voltages that would occur when using different voltage ladders for each DAC.

Abstract: A transmitter including a digital-to-analog converter (DAC) to generate an analog output corresponding to a transmitted signal. The transmitter further includes an analog-to-digital converter (ADC) coupled to the DAC. The ADC measures the analog output of the DAC to identify a set of digital samples. The ADC identifies, from the set of digital samples, a set of valid samples, wherein each valid sample has a voltage within a voltage range. The ADC extracts one or more signal properties from the set of valid samples.

Abstract: A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the nth current source set is twice a total quantity of current sources of the (n?1)th current source set.

Abstract: Disclosed is a gamma amplifier which includes a first amplification device that receives a first input signal during a first track period in a first time period, compensates for a first offset voltage from the first input signal during a first compensation period in the first time period, and generates a first output signal during a second time period after the first time period based on a control signal, and a second amplification device that receives a second input signal during a second track period in the second time period, compensates for a second offset voltage from the second input signal during a second compensation period in the second time period, and generates a second output signal during a third time period after the second time period based on the control signal and processing circuitry configured to generate the control signal.

Abstract: A multi-channel current pulse generator for driving a plurality of loads with unique positive terminals and a shared negative terminal. The pulse generator comprises a pulse control transistor and, for each load, a load capacitor and a charging control transistor. The pulse control transistor allows or blocks current pulses through the loads and has a drain terminal connected to the shared negative terminal, a source terminal connected to ground, and a gate terminal for receiving a load driver control signal. The load capacitors are discharged by current pulses through the corresponding loads. The charging control transistors allow or block charging currents for the corresponding load capacitors. The pulse control transistor is preferably an enhancement mode GaN FET and is chosen to withstand current pulses through a maximum number of loads to be driven simultaneously.

Abstract: An analog-to-digital converter (ADC) is provided. In some examples, the ADC includes a first reference voltage supply input, a second reference voltage supply input, a comparator comprising an input node, and a first reference switch coupled between the second reference voltage supply input and the input node of the comparator. The ADC also includes a set of capacitors, where each capacitor of the set of capacitors comprises a first terminal. In addition, the ADC includes a second reference switch coupled between the first reference voltage supply input and the first terminal of each capacitor of the set of capacitors. The ADC further includes a third switch coupled between the input node of the comparator and the first terminal of each capacitor of the set of capacitors.

Abstract: A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

Abstract: A sound generation system and related method include a user interface device and a processing device to obtain a specification of a three-dimensional space, obtain one or more sound tracks each comprising a corresponding sound signal associated with a corresponding sound source, present, in a user interface, representations representing one or more listeners and the one or more sound sources corresponding to the one or more sound signals in the three-dimensional space, responsive to a configuration of the locations of the one or more listeners or the locations of the one or more sound sources in the three-dimensional space in the user interface, determine filters based on the configuration and pre-determined locations of one or more loudspeakers, and apply the filters to the one or more sound signals to generate filtered sound signals for driving the one or more loudspeakers.

Abstract: The present disclosure provides a device and method of generating a nonlinear waveform signal dissipating low power and operating at a high speed. The device includes: a digital preprocessing unit configured to quantize an effective input signal to generate a linear data signal and a residual signal that is a difference between the effective input signal and the linear data signal; a nonlinear digital-to-analog conversion circuit (DAC) having a nonlinear relationship between an input and an output and configured to convert the linear data signal into a first analog signal; a linear interpolation DAC configured to convert the residual signal into a second analog signal to enable a generation of a converted analog signal by an addition of the second analog signal to the first analog signal; and an output circuit configured to output the converted analog signal as a nonlinear waveform signal.

Abstract: A method of processing asynchronous event-driven input samples of a continuous time signal, includes calculating a convolutional output directly from the event-driven input samples. The convolutional output is based on an asynchronous pulse modulated (APM) encoding pulse. The method further includes interpolating output between events.

Abstract: Device for generating analogue signals comprises a digital-to-analogue converter comprising at least one digital input and one analogue output, a circuit for generating a first clock signal of frequency fs, and a digital register configured so as to receive at the input and to store N bits representative of an analogue output signal of the converter, N being an integer greater than or equal to 1, and for receiving the first clock signal, the register comprising, for each bit, two complementary digital outputs.

Abstract: Systems, apparatuses, and methods related to bit string conversion are described. A memory resource and/or logic circuitry may be used in performance of bit string conversion operations. The logic circuitry can perform operations on bit strings, such as universal number and/or posit bit strings, to alter a level of precision (e.g., a dynamic range, resolution, etc.) of the bit strings. For instance, the memory resource can receive data comprising a bit string having a first quantity of bits that correspond to a first level of precision. The logic circuitry can determine that the bit string having the first quantity of bits has a particular data pattern and alter the first quantity of bits to a second quantity of bits that correspond to a second level of precision based, at least in part, on the determination that the bit string has the particular data pattern.

Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.

Abstract: Various embodiments provide for a data sampler with one or more capacitive digital-to-analog converters (DACs) for adjusting a threshold voltage range of the data sampler. According to some embodiments, two or more capacitive DACs can be used to set a threshold voltage for a data sampler and, by doing so, serve as a trigger mechanism for the data sampler.

Abstract: A pixel circuit and driving method are provided. The pixel circuit includes a light emitting device having a first terminal and a second terminal; a driving circuit, electrically connected to the first terminal of the light emitting device, for providing power to the light emitting device; a voltage comparator for generating a pulse width modulated signal having a duty cycle based on a data voltage and a reference voltage; an offset voltage detecting circuit, electrically connected to an output terminal of the voltage comparator, for detecting an input offset voltage of the voltage comparator; and a data voltage compensation circuit, electrically connected to the offset voltage detecting circuit, for compensating the data voltage according to the input offset voltage detected.

Abstract: This disclosure describes systems, methods, and apparatus for a digital-to-analog (DAC) converter, that can be part of a variable capacitor and/or a match network. The DAC can include a digital input, an analog output, N contributors (e.g., switched capacitors), and an interconnect topology connecting the N contributors, generating a sum of their contributions (e.g., sum of capacitances), and providing the sum to the analog output. The N contributors can form a sub-binary sequence when their contributions to the sum are ordered by average contribution. Also, the gap size between a maximum contribution of one contributor, and a minimum contribution of a subsequent contributor, is less than D, where D is less than or equal to two time a maximum contribution of the first or smallest of the N contributors.

Abstract: Provided herein are genetic circuits and cell state classifiers for detecting the microRNA profile of a cell. The cell state classifiers of the present disclosure are designed to incorporate multiple genetic circuits integrated together by transcriptional or translational control. Multiple inputs can be sensed simultaneously by coupling their detection to different portions of the genetic circuit such that the output molecule is produced only when the correct input profile of miRNAs is detected. The genetic circuits and cell state classifiers may be used in various applications (e.g., therapeutic or diagnostic applications).

Abstract: In some examples, a system includes an integrated circuit comprising a transistor, a first amplifier coupled to the transistor, a second amplifier having an output and coupled to the transistor and the first amplifier, and an R-2R resistor ladder having multiple rungs. Each rung is switchably coupled to a terminal of the transistor and to the output of the second amplifier. The R-2R resistor ladder includes a resistor coupled to either the transistor or the output of the second amplifier.

Abstract: A voltage-to-time converter (VTC) for a time-domain analog-to-digital converter is disclosed, which provides a time-domain analog-to-digital converter (T-ADC) with low power consumption and high precision. By combining the advantages of current-starving technology, current mirror technology, and body biasing technology, compared with the traditional structure, the VTC and T-ADC achieve excellent performance, such as low power consumption, high linearity, wide input dynamic range, and strong anti-interference to PVT variations. Compared with the traditional voltage-to-time converter, the disclosed voltage-to-time converter has a wider input dynamic range and higher linearity. The input voltage is connected to transistors in the circuit as a body bias, resulting in a very small body current, and no apparent increase in power consumption. The design of a low-power voltage-to-time converter is realized.

Abstract: A display driver includes a D/A converter circuit outputting a gradation voltage to an output line based on display data, an assist circuit including a capacitor group and a drive circuit outputting a drive signal group to a first end of the capacitor group based on the display data, the assist circuit being coupled to the output line and configured to perform assist driving of the output line, and an amplifier circuit configured to drive an electro-optical panel. The assist circuit includes an output switch provided between a second end of the capacitor group and the output line, the output switch being ON in an assist period, and an initialization switch including a first end coupled to the second end of the capacitor group and a second end to which an initialization voltage is input, and in an initialization period, the output switch and the initialization switch are ON.

Abstract: An electronic device may include digital circuitry that operates via digital signals and a digital to analog converter (DAC) to convert a digital signal into a modulated analog signal. The DAC may include multiple unit cells to generate an analog signal and multiple local oscillator (LO) tiles to modulate the analog signal and generate the modulated analog signal. The electronic device may also include LO circuitry to dynamically adjust an LO enable signal based at least in part on the digital signal. The LO enable signal may enable a reduced number of LO tiles supporting one or more respective sets of unit cells operatively enabled based on the digital signal.

Abstract: Methods, systems, and apparatus for quantum analog-digital conversion. In one aspect, a method includes obtaining a quantum analog signal; applying a hybrid analog-digital encoding operation to the quantum analog signal and a qudit in an initial state to obtain an evolved state of the qudit, wherein the hybrid analog-digital encoding operation is based on a swap operation comprising multiple adder operations; and providing the qudit in the evolved state as a quantum digital encoding of the quantum analog signal.

Abstract: A device is provided that includes a plurality of signal processing paths coupled in parallel, an adding circuit and an amplifier circuit. The number of the signal processing paths is N and each of the signal processing paths receives a same input signal to generate an output analog signal after a signal processing is performed, wherein each of the signal processing paths at least includes a DAC circuit and the signal processing at least includes a digital to analog conversion corresponding to the DAC circuit. The adding circuit adds the output analog signal generated from each of the signal processing paths to generate a total output analog signal. The amplifier circuit receives the total output analog signal to adjust a signal intensity of the total output analog signal according to a gain to generate an output audio signal, wherein the gain is 1/N.

Abstract: In accordance with an embodiment, a circuit includes a current digital-to-analog converter (DAC) having a current switching network coupled to a current DAC output, a first cascode current source coupled between a first supply node and the current switching network, a second cascode current source between a second supply node and the current switching network, and a shorting switch coupled between a first cascode node of the first cascode current source, and a second cascode node of the second cascode current source.

Abstract: The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

Abstract: Devices, systems and methods for uniquely identifying integrated circuits are provided. For at least one embodiment, an identifiable integrated circuit in a lot of integrated circuits includes a plurality of identifier devices. Each of the identifier devices, when tested, returns a series of first test results that form an analog identifier for the integrated circuit. For one embodiment, the identifier devices is a Zener diode. The test results may be based on reverse breakdown voltage measurements determined prior to packaging of the integrated circuit. Later testing of the integrated circuit returns a second series of reverse breakdown voltage measurements that monotonically vary over time and temperature, as compared to the first series of test results. Such monotonical variation facilitates correlation of the first series of test results with the second series of test results and, thereby, identification of the integrated circuit.

Abstract: An apparatus is configured to generate, from a stream of periodic digital samples, a first sub-stream of periodic analog samples and a second sub-stream of periodic analog samples, each sub-stream comprising substantially stable time intervals. The apparatus is further configured to generate a sign-modulated sub-stream by applying to the second sub-stream a sign modulation operation effecting a sign transition during a stable time interval of the second sub-stream. The apparatus is further configured to generate an output stream of periodic analog samples based on a sum of the first sub-stream and the sign-modulated sub-stream, wherein a period of the output stream is shorter than periods of the first and second sub-streams.

Abstract: Disclosed are a source driver capable of achieving high speed and high resolution and a display driving circuit including the same. The source driver may include: a first channel group and a second channel group configured to output source driving signals; a first gradation voltage divider configured to generate first gradation voltages using gamma reference voltages and provide the first gradation voltages to the first channel group; and a second gradation voltage divider configured to generate second gradation voltages having the same level as the first gradation voltages using the gamma reference voltages, and provide the second gradation voltages to the second channel group. The first and second gradation voltage dividers are connected to a gamma reference voltage generator configured to provide the gamma reference voltages, and receive the gamma reference voltages having the same voltage range from the gamma reference voltage generator.

Abstract: An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.

Abstract: A display device and a driving method are disclosed. The display device includes a plurality of pixel areas disposed in a display panel. Each pixel area includes at least one row of pixel units. The display panel further includes a plurality of collecting modules, a comparing module, and a processing module. Each collecting module is connected to the pixel units in each pixel area and configured to obtain and transmit input power voltage signals of the pixel units in a corresponding pixel area to the comparing module. The comparing module receives and compares the input power voltage signals with a base voltage respectively and transmits comparison results to the processing module respectively. The processing module adjusts data voltages of the pixel units in the corresponding pixel area respectively based on the comparison results in order to compensate the pixel units in the corresponding pixel area for resistive voltage drop differences.

Abstract: The present invention provides a device for processing digital signals. The device comprises a digital signal source configured to output codewords, a converter circuit configured to generate an output signal based on a first codeword received from the digital signal source, and a feed forward circuit configured to generate an output current based on a second codeword received from the digital signal source. The output current generated by the feed forward circuit is connected to a current supply of the converter circuit. The digital signal source is configured to generate the second codeword based on the first codeword in order to compensate for variations of a supply current of the converter circuit.