Abstract: An integrated circuit component is provided for the analog signal-to-frequency conversion independent of temperature variations. The integrated circuit component contains circuits for generating known analog balancing currents in the form of impressed, load-independent currents. The analog input signal is converted into a load-independent current and in sequence with the balancing signals applied to a current controlled oscillator. The frequencies obtained therefrom are converted into digital values by a frequency-to-digital converter. A microprocessor computes the digital value corresponding to the input signal.

Abstract: A multi-mode, adaptable, implantable pacemaker is described including a microprocessor and memory programmed or capable of being programmed with a variety of processes for stimulating the patient's heart and/or for sensing and transmitting to a device external of the patient's body, various conditions of or activities of the patient's heart, or conditions of the pacemaker itself. The pacemaker includes a multiplexer by which a variety of analog and digital inputs are accessed under the control of the microprocessor and operated upon by the processes stored in the memory and executed by the microprocessor. The output of the pacemaker comprises a plurality of latch drivers and switches, which are selectively operable to apply stimulation to the patient's heart, as well as to sense signals indicative of the patient's heart activity as well as other internal conditions. The pacemaker is capable of transmitting these signals via a link such as an RF or acoustical link to an external monitoring apparatus.

Abstract: A frequency-to-digital converter is constructed as an integrated device in which the following functions are implemented: a processor bus interface (38) having data, address and control lines; at least one converter channel (10) having at least one clock generator (24), at least one input (12,14), frequency-to-digital converter means (18), a comparator (44) for comparing a digital frequency equivalent with a programmed digital word (limit value register (48)) and which is arranged to signal the exceeding of a limit value at an output (56) of the device through a programmable time-counter (50) (delay register (124)) as well as a status memory (flip-flop 52) and means (54) for the internal gating of external states, a command register (58) which is arranged to determine and initiate the conversion mode, a range register which is arranged to determine the conversion range (frequency range 22) as well as the test frequency (66) and a output frequency (67), and a status register (88) which is arranged to output in

Abstract: A method for converting voltage to frequency and a device for implementing the method where an extremely rapid and highly accurate digitization of an input signal at a great freqency deviation is achieved using simple means. An input voltage which is raised into the positive range, is integrated, and as an integrated voltage is compared with a reference voltage which is variable in constant voltage steps. The resulting differential voltage acts upon a voltage controlled oscillator through a control element. The voltage controlled oscillator emits a pulse repetition frequency which is proportional to the output voltage of the controlling element. The reference voltage is incremented with each pulse so that this voltage follows the integrated voltage in a step-like manner. The pulse repetition frequency of the pulses, which are generated by the voltage controlled oscillator, is therefore proportional to the input voltage.

Abstract: A method and device for converting voltage to frequency performs an extremely rapid and highly accurate digitization of an analog input signal at a large frequency deviation. An input voltage, which is increased into the positive range, is integrated and compared with a reference voltage which is variable in constant steps. When the integrated voltage is greater than the reference voltage, a binary signal logic "1" is generated. If the integrated voltage is less than the reference voltage, a binary signal logic "0" is formed. When the integrated voltage is less than the reference voltage, a pulse repetition frequency is formed which is proportional to the input voltage. At each pulse, the reference voltage is incremented so that this reference voltage follows the integrated voltage in a step-like manner.

Abstract: A digital optical conversion module used to convert an analog signal to a computer compatible digital signal including a voltage-to-frequency converter, frequency offset response circuitry, and an electrical-to-optical converter. Also used in conjunction with the digital optical conversion module is an optical link and an interface at the computer for converting the optical signal back to an electrical signal. Suitable for use in hostile environments having high levels of electromagnetic interference, the conversion module retains high resolution of the analog signal while eliminating the potential for errors due to noise and interference. The module can be used to link analog output scientific equipment such as an electrometer used with a mass spectrometer to a computer.

Abstract: A DSB-SC signal is demodulated using an up/down counter, the count direction of which is alternately switched in synchronism with the polarity of a reference carrier signal for the DSB-SC signal. The converter includes an integrator, a comparator and a charge-rebalancing current source to reset the integrator. Correction of the court value of the up/down counter is obtained by tracking and storing a partial-bit analog signal. The partial-bit analog signal corresponds to and is obtained from the output of the integrator just prior to the pahse transition of the reference carrier signal. A capacitor samples the partial-bit analog signal information and subsequently transfers that information to the integrator input. The transfer of a charge of twice the magnitude and opposite polarity to the integrator compensates for the partial bit analog signal as it is detected by the up/down counter. A digital system for converting the partial-bit analog signal to a binary code word is provided.

Abstract: An analog baseband signal modulates a reference-frequency carrier signal to provide a double-sideband, suppressed-carrier DSB-SC signal. The DSB-SC signal is converted in a voltage-to-frequency converter to a series of pulses, which are demodulated to produce a digitally formatted version of the baseband signal. A notch filter for rejecting an undesired analog signal includes a voltage-to-frequency converter and a selective feedback path which demodulates the undesired signal from a frequency-encoded domain back to the analog domain for a cancellation in a summer preceding the voltage-to-frequency converter.

Abstract: An analog to digital converter comprises coarse (15, 16) and fine (24, 19) quantization. The coarse quantization is of the frequency-current type or frequency-voltage frequency type. The fine quantization measures the discharge period of a residual charge stored in an integration capacitor (3) at the end of the coarse quantization phase. The discharger of this capacitor includes a capacitor (14) for quantifying this discharge.

Abstract: A bipolar analog voltage is converted into a digital signal by sensing the polarity of the voltage and selectively supplying a bias voltage to an analog-to-digital converter, which can preferably be a charge balanced voltage to frequency converter, as a function of the sensed polarity. The voltage to frequency converter has a double valued variable frequency output with a discontinuity at zero volt such that the converter derives a maximum output frequency for a maximum positive voltage and also for a negative value slightly displaced from zero; the voltage to the frequency converter minimum output frequency is derived from positive voltages slightly greater than zero and for maximum negative voltages. The converter output frequency and the sensed polarity are supplied to a frequency to digital converter which derives an output signal having a bit representing the polarity of the analog voltage and additional bits indicative of the magnitude of the analog voltage.

Abstract: A system is described for correcting errors in a waveform comprising a plurality of binary pulses, each having a different rise time and fall time with respect to the positive going and negative going transitions of each pulse. The system generates a plurality of correction pulses, each synchronously with a corresponding positive going or negative going transition of the binary pulses; and adds each of the correction pulses to the waveform so that the signal area lost by the rise characteristic of the resulting binary pulses will equal the signal area gained by the fall characteristics of the resulting binary pulses.

Abstract: To obtain better accuracy, it is known to modify the mechanical metered volume reading of the flow through a gas pipeline according to the gas laws, which incorporate the pressure and temperature parameters of the gas. The present invention samples those parameters with analog sensors and inputs them into an analog to digital converter. The digital output from the converter is employed to obtain a more accurate digital volume reading.

Abstract: A priority encoder having MxN input lines and M output lines included M N-bit input priority encoder units, a precharging device, and a zero detecting device. Each N-bit input priority encoder unit includes an N-bit priority detecting device, a memory, a selector, a carry signal generating device, and a control device. The control device controls the output of the N-bit input prioroity encoder in accordance with the outputs of the N-bit priority detecting device and the carry signal generating device.

Abstract: The system includes a synchronous voltage-to-frequency converter connected to receive an analog input signal voltage and to generate a train of output pulses. A counter is connected to receive and count the output pulses and a digital register is connected to the counter for periodically receiving and storing the count in the counter. A conversion interval timer circuit is connected to control the operation of the counter and the register to determine a conversion interval during which the output pulses from the synchronous voltage-to-frequency converter are accumulated in the counter and then stored in the register. The conversion interval timer circuit is operable to determine the end of a prior conversion interval and the beginning of a new conversion interval in response to a predetermined phase of a predetermined cycle of the ac power line voltage.

Abstract: Computer control apparatus uses sensing apparatus converts a mechanical movement into a direct current electrical signal. An electrical interface circuit is connected to the sensing apparatus for converting the direct current electrical signal into a pulse output used in controlling a computer. The preferred sensor is an inclinometer, which comprises an opaque body having a chamber. A light source is connected to the body to provide light in the chamber. Photocell apparatus is connected to the body to receive light emitted from the light source for providing an electrical resistance in relation to the amount of light received. Supported in the chamber is a liquid filter medium to absorb light emitted from the light source. A sufficient quantity of liquid filter medium is provided in the chamber to prevent light emitted from the light source from impinging upon the photocell apparatus in response to the angular placement of the body with respect to gravity.

Abstract: A voltage-to-frequency converter comprising a triwave generator responsive to an input signal to produce an output triangular signal the frequency of which corresponds to the magnitude of the input signal, and a voltage-slope-to-periodic-function (VSTPF) generator which receives the output of the triwave generator and produces a pulsed output signal having a frequency which is a multiple of that of the triwave generator.

Abstract: A clock-controlled pulse width modulator comprising an integrator for receiving a variable input voltage and producing an output having a triangular waveform, the integrator including a capacitor which is charged at a rate proportioal to the input voltage and discharged at a rate proportional to the difference between a reference voltage and the input voltage, the charging and discharging occurring during a time interval T.sub.o, a clock pulse source for generating a continuous series of clock pulses, a counter receiving the clock pulses and producing a binary control signal which changes state in response to the counting of a preselected number of clock pulses, the control signal having a period T.sub.

Abstract: In a digital control system wherein control voltages are analog voltages, a method and control system for generating a variable output bit resolution from an N bit analog to digital converter utilizing a control circuit to control the input spread of the voltage references to the A/D converter. Depending on the binary value of the MSD position, the input reference voltage spread is controlled. If the binary value is zero, the input reference voltage spread is one-half the normal value and the resolution is N+1 bits and if the binary value is zero for both the MSD and MSD-1 positions, the input reference voltage spread is one-fourth the normal value and the resolution is N+2 bits and so on until the first binary one value is found after consecutive preceding binary zero values.

Abstract: A method and apparatus of converting analog voltage signals to digital frequency signals comprises a voltage to frequency converter having an output which produces pulse trains that are proportional to the voltage level of an analog voltage signal applied to the converter. A microprocessor is connected to the converter for sampling the pulse trains during a fixed sampling period. The microprocessor detects the leading edges of the first and last pulse in the pulse train, stores the occurrence time for the two leading edges and then subtracts the occurrence times to calculate the duration time for all the pulses in the sample period between the leading edges of the first and last pulses. A counter counts the number of pulses between the first and last pulse, and a calculation is made dividing the number of pulses by the time duration to yield an accurate measurement of the frequency for the pulse train.