Analog To Digital Conversion Patents (Class 341/155)
  • Patent number: 11357986
    Abstract: A system for estimating a volume of activation around an implanted electrical stimulation lead for a set of stimulation parameters includes a display; and a processor coupled to the display and configured to: receive a set of stimulation parameters including a stimulation amplitude and a selection of one of more electrodes of the implanted electrical stimulation lead for delivery of the stimulation amplitude; determine an estimate of the volume of activation based on the set of stimulation parameters using the stimulation amplitude and a database including a plurality of planar distributions of stimulation threshold values and a map relating the planar distributions to spatial locations based on the one or more electrodes of the implanted electrical stimulation lead selected for delivery of the stimulation amplitude; and output on the display a graphical representation of the estimate of the volume of activation.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: June 14, 2022
    Assignee: Boston Scientific Neuromodulation Corporation
    Inventors: G. Karl Steinke, Richard Mustakos
  • Patent number: 11363225
    Abstract: It is an object of the present technology to provide an image sensor capable of reducing crosstalk in an AD conversion unit. The image sensor includes: capacitors in an even-numbered column region; and a capacitor in an odd-numbered column region disposed facing the capacitors in the even-numbered column region with different areas.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 14, 2022
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Takashi Moue, Hiroaki Yatsuda
  • Patent number: 11356236
    Abstract: Circuit including a first port to couple to a first device; a second port to couple to a second device; a first channel having an input coupled to first port and an output coupled to second port, the first channel to re-drive a signal and output re-driven signal; a second channel having an input coupled to second port and an output coupled to first port, the second channel to re-drive a signal and output re-driven signal; and a controller to: enable first channel and disable second channel responsive to detecting a signal edge at first port; enable second channel and disable first channel responsive to detecting a signal edge at second port; sample impedance at first port if signal received at first port is de-asserted while first channel is enabled; and sample impedance at second port if signal received at second port is de-asserted while second channel is enabled.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: June 7, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Win Naing Maung, Charles Michael Campbell
  • Patent number: 11344213
    Abstract: An apparatus for sensing a heart rate of a subject, including an eyewear frame and a heart rate sensing circuit. The sensing circuit includes first and second piezoelectric sensors configured to be in communication with the subject's skin and to generate first and second voltage signals in response to a periodic vibration in at least one artery of the subject, a first voltage amplifier configured to receive the first voltage signal and output a first amplified voltage signal related to the heart rate of the subject, a second voltage amplifier configured to receive the second voltage signal and output a second amplified voltage signal related to the heart rate of the subject, and a device configured to output a differential signal that is a representation of a difference between the first amplified voltage signal and the second amplified voltage signal that relates to the heart rate.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Amit Sudhir Baxi, Vincent S. Mageshkumar, Indira Negi
  • Patent number: 11340995
    Abstract: An integrated circuit includes a processing core, memory coupled to the processing core, a plurality of pins, an input/output (IO) control module operably coupled to provide control signaling indicating desired functions for the plurality of pins, and a plurality of programmable IO interface modules. A programmable IO interface module includes: a front-end module coupled to at least one pin of the plurality of pins, a back-end module coupled to at least one of the processing core and the memory, and an IO configuration module coupled to the IO control module. Each of the front-end module and the back-end module are configurable, via the control signaling, to configure the at least one pin to operate as one of: a bidirectional interface, an input, an output, a concurrent drive & sense interface, and a concurrent transmit-receive data interface.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: May 24, 2022
    Assignee: SigmaSense, LLC.
    Inventors: Richard Stuart Seger, Jr., Gerald Dale Morrison, Daniel Keith Van Ostrand, Patrick Troy Gray, Timothy W. Markison
  • Patent number: 11343427
    Abstract: An imaging device according to the present disclosure includes: an imaging unit configured to perform an imaging operation; a data generator configured to generate first power supply voltage data corresponding to a first power supply voltage; and a flag generation section configured to generate a flag signal for the first power supply voltage by comparing the first power supply voltage data and first reference data. The first power supply voltage is supplied to the imaging unit.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: May 24, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Naoki Kawazu, Keita Sasaki, Takumi Oka, Yuichi Motohashi, Atsushi Suzuki
  • Patent number: 11329664
    Abstract: An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.
    Type: Grant
    Filed: March 29, 2021
    Date of Patent: May 10, 2022
    Assignee: VIAVI SOLUTIONS INC.
    Inventor: Sean Hamlin
  • Patent number: 11316526
    Abstract: An analog-to-digital converter includes a voltage-to-delay device, such as a pre-amplifier array, for generating a delay signal based on a first voltage, and delay-based stages for generating digital signals based on the delay signal. In operation, the delay signal is transmitted to a first delay-based stage, or to an intermediate delay-based stage, bypassing the first delay-based stage, to overcome non-linearity of previous stages. If desired, different pre-amplifiers may be used to generate signals for calibration of different delay-based stages. The present disclosure may also involve converting to pseudo-static signals before signals are handed over to a calibration engine, to ease timing and preserve interface area and power. If desired, simple delay elements may be used to correct for non-linearity in a delay-based analog-to-digital converter. The present disclosure may be employed, if desired, in connection with any suitable cascade of non-linear stages.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: April 26, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Narasimhan Rajagopal, Visvesvaraya Appala Pentakota, Eeshan Miglani
  • Patent number: 11313980
    Abstract: The present technology relates to a radiation detection apparatus that makes it possible to obtain a projection image of a radiation in a short period of time. The radiation detection apparatus includes a scintillator that emits scintillation light in response to incidence of a radiation, a pixel substrate on which a plurality of pixels each of which photoelectrically converts the scintillation light and outputs a pixel signal according to a light amount of the scintillation light is disposed in an array, a detection circuit substrate that includes an A/D (Analog to Digital) conversion unit for A/D converting the pixel signal and is stacked on the pixel substrate, and a compression unit that compresses digital data outputted from the A/D conversion unit. The present technology can be applied, for example, to an X-ray imaging apparatus that detects an X-ray to perform imaging and so forth.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: April 26, 2022
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Toshiyuki Nishihara, Tsutomu Imoto, Masao Matsumura, Hiroyasu Baba
  • Patent number: 11290121
    Abstract: A successive approximation ADC includes: a comparator generating a judge signal related to an input analog and a reference signals; a SAR successively generating a register signal including a first and a second bit signals based on the judge signal and generating an AD conversion value of the input analog signal; a thermometer decoder switching different thermometer code conversion rules and converting the first bit signal to thermometer codes corresponding to the different thermometer code conversion rules in one AD conversion cycle; a first and a second DA converters respectively converting the thermometer codes to a first analog signal and the second bit signal to a second analog signal; an average value calculator averaging the AD conversion values by the thermometer codes. Two of the different thermometer codes have values that a high-order bit and a low-order bit groups by dividing total bits of the thermometer code equally are exchanged.
    Type: Grant
    Filed: January 31, 2021
    Date of Patent: March 29, 2022
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Shota Konno
  • Patent number: 11275344
    Abstract: A time to digital converter includes a polarity detecting module and a time digital conversion module. The time digital conversion module includes a digital coding unit, a ring vibration enabling unit, multistage differential time delay units sequentially forming a closed loop in series and a plurality of trigger units. Each differential time delay unit includes a first input end, a second input end, a first output end and a second output end. The first output end and the second output end of each differential time delay unit outputs differential signals which are complementary to each other. Mismatching between the ascending and descending time of a phase inverter and sampling of a trigger can be improved to enable signals entering the trigger units to be phase-complementary signals, thus improving the linearity of digital conversion.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: March 15, 2022
    Assignee: AMLOGIC (SHANGHAI) CO., LTD.
    Inventor: Yan Wang
  • Patent number: 11264959
    Abstract: A precharge circuit comprises a gain amplifier, a comparator, a reservoir capacitor, a switch, a current source, and a switching network. The gain amplifier has a gain G1 and receives an input voltage Vrefp. The gain amplifier outputs an amplified voltage G1Vrefp to the comparator, which compares G1Vrefp to a voltage across the reservoir capacitor. The comparator outputs a control signal for the switch based on the comparison. The switch couples the current source to the reservoir capacitor. The current from the current source charges the reservoir capacitor. The switching network couples the reservoir capacitor to an output of the precharge circuit during a first operating mode and provides the input voltage Vrefp to the output during a second operating mode.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 1, 2022
    Assignee: Texas Instruments Incorporated
    Inventors: Amit Kumar Gupta, Peng Cao
  • Patent number: 11258469
    Abstract: In some examples, a system includes at least two antennas configured to receive signals encoding first, second, and third messages in first, second, and third frequency bands. The system also includes a set of splitters configured to generate separate signals in the first, second, and third frequency bands. The system further includes a set of combiners, wherein each combiner of the set of combiners is configured to combine two or more of the separate signals. The system includes a set of mixers configured to down-convert the combined signals and at least one analog-to-digital converter configured to sample the down-converted signals. The system also includes processing circuitry configured to determine data in the first, second, and third messages based on an output of the at least one analog-to-digital converter.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: February 22, 2022
    Assignee: Honeywell International Inc.
    Inventors: Thomas W. Hastings, David Larsen
  • Patent number: 11255879
    Abstract: A measuring device comprises a first interface, which is adapted to receive a first measuring signal. The measuring device further comprises an acquisition memory, which is adapted to store at least one data segment of the first measuring signal. The measuring device further comprises an analyzer, which is connected to the acquisition memory, and is adapted to analyze the at least one data segment of the first measuring signal and generate a first analysis result therefrom. The measuring device further comprises a memory controller, which is adapted to either keep, in the acquisition memory, or discard, the at least one data segment based upon the first analysis result.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: February 22, 2022
    Assignee: Rohde & Schwarz GmbH & Co. KG
    Inventor: Thomas Guenther
  • Patent number: 11258978
    Abstract: The present invention encompasses methods and systems of representing video in continuous time. Photons incident on pixels in an imaging array are continuously captured using a continuous time imaging sensor array to produce respective continuous time analog signals without any discontinuity in time. At each pixel, the respective continuous time analog signal is modulated into respective continuous time binary analog signals. The continuous time binary analog signals from all pixels can then be aggregated to produce a frame free video. Further, at each pixel, the respective continuous time analog signal may be modulated using a continuous time sigma delta modulator to produce the corresponding continuous time binary analog signal. The sigma delta modulator may be one of charge-based or current-based.
    Type: Grant
    Filed: April 3, 2020
    Date of Patent: February 22, 2022
    Assignee: Solsona Enterprise, LLC
    Inventor: Chong Lee
  • Patent number: 11252358
    Abstract: The present technology relates to a signal processing apparatus, a control method, an image pickup element, and an electronic device which make it possible to suppress RTS noise. The signal processing apparatus of the present technology may include an amplifying transistor and a short-circuit unit. The amplifying transistor amplifies a signal input to a gate, and the short-circuit unit is capable of short-circuiting the gate of the amplifying transistor to a potential which reduces a gate-to-source voltage of the amplifying transistor. For example, it is determined whether the amplifying transistor is in a period of a non-operating state, and when the amplifying transistor is determined to be in the period of a non-operating state, the gate of the amplifying transistor may be short-circuited. The present technology can be applied, for example, to an image pickup element and an electronic device.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: February 15, 2022
    Assignee: SONY CORPORATION
    Inventor: Katsuhiko Hanzawa
  • Patent number: 11252364
    Abstract: An image sensing device includes a coarse current generation circuit suitable for generating a coarse ramp current adjusted to a coarse level for a single ramp period, a fine current generation circuit suitable for generating a fine ramp current adjusted to a fine level for the single ramp period, and a current-to-voltage conversion circuit suitable for generating a ramp voltage corresponding to a resultant current of the coarse ramp current and the fine ramp current for the single ramp period.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: February 15, 2022
    Assignee: SK hynix Inc.
    Inventor: Tae-Gyu Kim
  • Patent number: 11249500
    Abstract: A regulator includes a switch array, a feedback circuit, first and second voltage-controlled oscillators, and a switch driver. The switch array generates an output voltage based on a number of enabled switches from among a plurality of switches. The feedback circuit generates a feedback voltage which depends on a level of the output voltage. The first voltage-controlled oscillator generates a first signal having a first frequency which depends on a difference between a reference voltage and the feedback voltage. The second voltage-controlled oscillator generates a second signal having a second frequency which depends on a difference between the feedback voltage and the reference voltage. The switch driver determines a turn-on time point of each of the plurality of switches based on the first signal and determining a turn-off time point of each of the plurality of switches based on the second signal.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: February 15, 2022
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Changsik Yoo, Jin-Gyu Kang
  • Patent number: 11252354
    Abstract: An image sensor comprises: a pixel unit including a plurality of first blocks each of which includes a plurality of first pixels shielded from light and a plurality of second blocks each of which includes a plurality of second pixels that are not shielded from light; and a controller that controls a plurality of readout operations for processing, in parallel, pixel signals read out from the plurality of first blocks and the plurality of second blocks in the pixel unit. The controller performs control so as to end readout of pixel signals from at least a predetermined portion of the first pixels included in each of the plurality of first blocks, before readout of pixel signals from the plurality of second blocks is started.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: February 15, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Mie Ishii, Kazuki Ohshitanai
  • Patent number: 11245412
    Abstract: A method of enhancing SAR ADC conversion rate by employing a new value shifted capacitor DAC. The value shifted capacitor DAC decreases largest capacitor to improve the reference voltage settling. The reduction of capacitor is added back onto the smaller capacitor DAC to maintain the same total capacitor value. The binary search outputs are re-combined and processed to produce final binary ADC outputs. The overhead of using value shifted capacitor DAC is the extra latency needed for re-combined logic.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: February 8, 2022
    Inventor: Yuan-Ju Chao
  • Patent number: 11239850
    Abstract: An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: February 1, 2022
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Lars Sundström, Mattias Palm, Fredrik Tillman
  • Patent number: 11239853
    Abstract: An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: February 1, 2022
    Assignee: Digital Analog Integration, Inc.
    Inventors: Fa Dai, Haoyi Zhao, John David Irwin
  • Patent number: 11239852
    Abstract: The present disclosure provides an error compensation correction system and method for an analog-to-digital converter with a time interleaving structure, the system includes an analog-to-digital converter with a time interleaving structure, a master clock module, a packet clock module, an error correction module, an adaptive processing module and an overall MUX circuit. Through the error compensation correction system and method for the analog-to-digital converter with a time interleaving structure according to the present disclosure, lower correction hardware implementation complexity and higher stability are ensured. The system and method according to the present disclosure are particularly suitable for interchannel mismatch error correction of dense channel time interleaving ADC, and the performance of the time interleaving ADC is improved.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 1, 2022
    Assignee: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION
    Inventors: Jie Pu, Gangyi Hu, Jian'an Wang, Guangbing Chen, Liang Li, Ting Li, Daiguo Xu, Xingfa Huang, Xi Chen, Tiehu Li, Youhua Wang
  • Patent number: 11233521
    Abstract: Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: January 25, 2022
    Assignee: UTI Limited Partnership
    Inventors: Leo Belostotski, Eugene Zailer, Ge Wu
  • Patent number: 11233522
    Abstract: An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: January 25, 2022
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Ishwar Chandra Mudegowdar, Tomas Pankrac
  • Patent number: 11223367
    Abstract: An analog-to-digital converting apparatus includes a first stage converter which performs a first analog-to-digital conversion on an input analog signal during a first stage period, a second stage converter which receives a first residue from the first stage converter amplified by a first gain and which performs a second analog-to-digital conversion during a second stage period, and a recombination logic circuit which combines a first output signal from the first stage converter and a second output signal from the second stage converter into an output digital signal that corresponds to the input analog signal. The second stage converter generates a second stage feedback signal obtained by amplifying the second output signal by the first gain during a first sub-cycle in the second stage period, and generates a second output signal of a second sub-cycle subsequent to the first sub-cycle based on the second stage feedback signal.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: January 11, 2022
    Inventors: Il Hoon Jang, Hyung Dong Roh, Seung Yeob Baek, Michael Choi
  • Patent number: 11218160
    Abstract: An analog-to-digital (ADC) circuit is disclosed that includes a first stage, a first amplifier, and a second amplifier. The first stage includes signal processing circuitry, and is configured to receive a differential input signal and generate a differential residue voltage signal on differential output nodes of the first stage. The first amplifier includes first amplifier circuitry. The first amplifier is electrically connected to the differential output nodes of the first stage, and configured to receive the differential residue voltage signal, and generate a first differential voltage signal from the differential residue voltage signal. The second amplifier includes second amplifier circuitry. The second amplifier is electrically connected to differential output nodes of the first amplifier, and configured to receive the first differential voltage signal, and generate a second differential voltage signal from the first differential voltage signal.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: January 4, 2022
    Assignee: XILINX, INC.
    Inventors: Bruno Miguel Vaz, Vipul Bajaj
  • Patent number: 11218178
    Abstract: In one embodiment an apparatus includes: a mixer to downconvert a radio frequency (RF) spectrum including at least a first RF signal of a first channel of interest and a second RF signal of a second channel of interest to at least a first second frequency signal and a second second frequency signal; a first digitizer to digitize the first second frequency signal to a first digitized signal, the first digitizer configured to operate as a low-pass analog-to-digital converter (ADC); a second digitizer to digitize the second second frequency signal to a second digitized signal, the second digitizer configured to operate as a band-pass ADC; and a digital processor to digitally process the first digitized signal and the second digitized signal.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: January 4, 2022
    Assignee: Silicon Laboratories Inc.
    Inventors: Jacob Pihl, Peter Østergaard Nielsen
  • Patent number: 11218162
    Abstract: The invention provides a signal processing system, for transferring analog signals from a probe to a remote processing unit. The system comprises a first ASIC at a probe, which is adapted to receive an analog probe signal. The first ASIC comprises an asynchronous sigma-delta modulator, wherein the asynchronous sigma-delta modulator is adapted to: receive the analog probe signal; and output a binary bit-stream. The system further comprises a second ASIC at the remote processing unit, adapted to receive the binary bit-stream. The asynchronous may further include a time gain function circuit, the first ASIC may further comprise a multiplexer, the second ASIC may further comprise a time-to-digital converter. The time to digital converter may be a pipelined time-to-digital converter.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: January 4, 2022
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Sotir Filipov Ouzounov, Emil Dimitrov Totev
  • Patent number: 11211870
    Abstract: Apparatus and methods for sequencing outputs in a multi-output power converter system are disclosed herein. During start-up multiple CC/CV outputs may be sequenced so that energy is first provided to a highest voltage secondary output and subsequently provided to a lowest voltage secondary output. Additionally, control may be exerted so as to concurrently and monotonically increase voltages during at least part of the start-up transient; and concurrent control may be further implemented using control circuitry and a variable reference generator. In some embodiments a variable reference may be generated from a capacitor voltage.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: December 28, 2021
    Assignee: POWER INTEGRATIONS, INC.
    Inventors: Karl Moore, Matthew David Waterson, Antonius Jacobus Johannes Werner
  • Patent number: 11211904
    Abstract: A switched-capacitor amplifier circuit includes multiple switched-capacitor networks, an amplifier, and multiple reset circuits. The switched-capacitor networks are configured to receive respective input voltages during a sampling phase, and generate sampled voltages. During an amplification phase, the amplifier is coupled with the switched-capacitor networks, and is configured to receive the sampled voltages. The amplifier is further configured to generate output voltages. During the sampling phase, the amplifier is coupled with the reset circuits, and is further configured to receive divided voltages such that the amplifier is reset. The reset circuits are configured to receive and provide a common-mode voltage and the output voltages to the amplifier. The divided voltages are generated based on the common-mode voltage and the output voltages. Each reset circuit includes at least one of a resistor and a capacitor.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: December 28, 2021
    Assignee: NXP B.V.
    Inventor: Sushil Kumar Gupta
  • Patent number: 11206039
    Abstract: A comparator includes a second stage coupled between a first stage and a third stage. The second stage includes a first transistor coupled to be switched in response to a first output signal coupled to be received from the first stage. The first transistor is coupled generate a second output signal coupled to be received by the third stage. A second transistor is coupled to the first transistor. The first and second transistors are coupled between a first supply voltage and a reference voltage. A second stage current of the second stage is conducted through the first transistor and the second transistor. The second transistor is coupled to be switched in response to a third output signal coupled to be received from the third stage in response to the second output signal.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: December 21, 2021
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventor: Hiroaki Ebihara
  • Patent number: 11206037
    Abstract: The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: December 21, 2021
    Assignee: CHENGDU HUAWEI ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Qiang Yu, Yuanjun Cen, Jinda Yang
  • Patent number: 11206368
    Abstract: A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: December 21, 2021
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Chun-Hsiang Chang, Zejian Wang, Chao-Fang Tsai, Jingwei Lai
  • Patent number: 11196438
    Abstract: Described are apparatus and methods for analog to digital converter (ADC) with factoring and background clock calibration. An apparatus includes an ADC configured to sample and convert differential input signals using a reference clock to obtain a defined number of samples during a first state in an acquisition clock cycle, and a finite state machine circuit configured to obtain the defined number of samples from the ADC using a clock based on the reference clock, factor the defined number of samples based on at least a common mode offset associated with the ADC, and send offset factored output to a controller.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: December 7, 2021
    Assignee: Ciena Corporation
    Inventors: Soheyl Ziabakhsh Shalmani, Hazem Beshara, Mohammad Honarparvar, Sadok Aouini, Christopher Kurowski, Naim Ben-Hamida
  • Patent number: 11190202
    Abstract: An analog-to-digital converter includes: a voltage-current converter receiving an analog input voltage, generating a first digital signal from the analog input voltage, and outputting a residual current remaining after the first digital signal; a current-time converter converting the residual current into a current time in a time domain; and a time-digital converter receiving the residual time, and generating a second digital signal from the residual time, wherein the first digital signal and the second digital signal are sequences of digital codes representing respective signal levels of the analog input voltage.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 30, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoungjun Moon, Dongryeol Oh, Youngjae Cho, Michael Choi
  • Patent number: 11184571
    Abstract: Provided are a solid-state imaging device, a method for driving the same and an electronic apparatus where a comparator in an AD converter in a digital pixel is characterized by low power consumption and low peak current and that are capable of operating at low voltage and achieving high linearity across the entire input range. A comparator is constituted by two stages of preamplifiers with a clamp diode and two serial current-controlling inverters, and every branch is current-controlled. The two stages of the preamplifiers and the following two consecutive inverters are all current-controlled such that low power consumption and low peak current are realized. A trade-off can be made between the noise and the comparator speed by controlling the bandwidth of the comparator using the bias current. This is beneficial to more than one comparator operation mode.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: November 23, 2021
    Assignee: BRILLNICS SINGAPORE PTE. LTD.
    Inventor: Toshinori Otaka
  • Patent number: 11184017
    Abstract: An analog-to-digital (A/D) conversion system includes a track-and-hold circuit, a comparison circuit, a control circuit, a digital-to-analog (D/A) conversion circuit, a switched buffer and a loop filter. The track-and-hold circuit is configured to output a first signal based on an input signal or a first timing signal. The comparison circuit is configured to generate a comparison result based on the first signal and a filtered residue signal. The control circuit is coupled to the comparison circuit, and is configured to generate an N-bit logical signal according to N comparison results from the comparison circuit. The D/A circuit is configured to generate a feedback signal based on the N-bit logical signal. The switched buffer is configured to generate a first error signal based on a second timing signal and a second error signal. The loop filter is configured to generate the filtered residue signal based on the first error signal.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: November 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Martin Kinyua
  • Patent number: 11165430
    Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The sequential circuit includes a 3-input majority gate having first, second, and third inputs, and a first output. The sequential circuit includes a driver coupled to the first output, wherein the driver is to generate a second output. The sequential circuit further includes an exclusive-OR (XOR) gate to receive a clock and the second output, wherein the XOR gate is to generate a third output which couples to the second input, where the first input is to receive a data, and wherein the third input is to receive the second output.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: November 2, 2021
    Assignee: Kepler Computing Inc.
    Inventors: Sasikanth Manipatruni, Yuan-Sheng Fang, Robert Menezes, Rajeev Kumar Dokania, Gaurav Thareja, Ramamoorthy Ramesh, Amrita Mathuriya
  • Patent number: 11150292
    Abstract: Technologies and methods for detecting voltage spikes on a semiconductor device include detecting a voltage spike in a first analog signal from a semiconductor device based on a comparison of the first analog signal and a first voltage threshold, and converting the first analog signal to a digital signal with a first pulse representing the voltage spike, and transforming the first pulse to a stretched pulse defining a greater width than the first pulse. More specific embodiments include receiving a second analog signal from a first pin on the semiconductor device during a capture time period, receiving a reference analog signal from a reference pin on the semiconductor device during the capture time period, and prior to detecting the voltage spike, generating the first analog signal by computing a difference between the second analog signal and the reference analog signal.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 19, 2021
    Assignee: Anora, LLC
    Inventors: Pramodchandran Variyam, Sasikumar P. Cherubal
  • Patent number: 11146753
    Abstract: An imaging apparatus includes: a plurality of analog-digital conversion units that performs parallel processing on a signal of each pixel output in units of a plurality of pixel rows from a pixel array unit in which pixels including photoelectric conversion units are arranged, and converts the signal into a digital signal; a plurality of reference voltage generation units that is provided corresponding to the plurality of analog-digital conversion units and generates a reference voltage used for AD conversion; a voltage setting unit that sets a plurality of pixel voltage levels and outputs the plurality of pixel voltage levels through each of the plurality of analog-digital conversion units; and a computing unit that calculates a correction amount for performing correction on a result of the AD conversion of the signal of each pixel of the pixel array unit.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: October 12, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Masahiro Shimura, Seijiro Sakane
  • Patent number: 11146279
    Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.
    Type: Grant
    Filed: October 7, 2020
    Date of Patent: October 12, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Rajashekar Benjaram, Maheedhar Suryadevara
  • Patent number: 11132955
    Abstract: A display apparatus is disclosed, which comprises a demultiplexing circuit portion for sequentially supplying data signals supplied from a data driving circuit to at least two data lines, the demultiplexing circuit portion including a switching portion for sequentially supplying the data signals to at least two data lines based on a voltage of a control line, a voltage controller for controlling the voltage of the control line in response to a time-division control signal and an auxiliary signal partially overlapped with the time-division control signal, and a voltage discharge portion for discharging the voltage of the control line in response to the time-division control signal. Therefore, an off current capable of being transferred to an organic light emitting diode may be prevented from occurring, a bezel area may be minimized, and an image of high resolution of a display panel may be embodied.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: September 28, 2021
    Assignee: LG Display Co., Ltd.
    Inventors: JungHyun Lee, Yewon Hong, TaeWoong Moon
  • Patent number: 11133838
    Abstract: Under one aspect, a method is provided for processing a received signal, the received signal including a desired signal and an interference signal that spectrally overlaps the desired signal. The method can include obtaining an amplitude of the received signal. The method also can include obtaining an average amplitude of the received signal based on at least one prior amplitude of the received signal. The method also can include subtracting the amplitude from the average amplitude to obtain an amplitude residual. The method also can include, based upon an absolute value of the amplitude residual being less than or equal to a first threshold, inputting the received signal into an interference suppression algorithm so as to generate a first output including the desired signal with reduced contribution from the interference signal.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: September 28, 2021
    Assignee: The Aerospace Corporation
    Inventors: Philip Dafesh, Phillip Brian Hess
  • Patent number: 11133812
    Abstract: Systems and circuits for an asynchronous SAR ADC are described. The SAR ADC includes a two-stage comparator with a preamplifier first stage and a latch second stage. The preamplifier first stage is activated by an active pulse of a first clock signal and the latch second stage is activated by an active pulse of a second clock signal. The Done signal from a done detector is fed back as the active pulse of the first clock signal. The leading edge of the active pulse of the second clock signal is driven by the leading edge of the active pulse of the first clock signal via an RS latch. The Done signal is further fed back through the RS latch to drive a trailing edge of the active pulse of the second clock signal.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: September 28, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Semyon Lebedev, Babak Zamanlooy, Marc-Andre Lacroix
  • Patent number: 11121720
    Abstract: The present invention provides an ADC including a first switched capacitor array, a second switched capacitor array, a third switched capacitor array, an integrator and a quantizer. The first switched capacitor array is configured to sample the input signal to generate a first sampled signal. The second switched capacitor array is configured to sample the input signal to generate a second sampled signal and generate a first quantization error. The third switched capacitor array is configured to sample the input signal to generate a third sampled signal and generate a second quantization error. The integrator is configured to receive the first quantization error and the second quantization error in a time-interleaving manner, and integrate the first/second quantization error to generate an integrated quantization error. The quantizer is configured to quantize the first sampled signal by using the integrated quantization error as a reference voltage to generate a digital output signal.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: September 14, 2021
    Assignee: MEDIATEK INC.
    Inventors: Chan-Hsiang Weng, Hung-Yi Hsieh, Tzu-An Wei, Ting-Yang Wang
  • Patent number: 11112812
    Abstract: A low-dropout voltage regulation device includes a power stage having an output terminal coupled to a load circuit, the load circuit being operable in a plurality of operating modes. The load circuit is configured to receive a different respective output current when in each of the plurality of operating modes. An error amplifier has an output coupled to an input terminal of the power stage. A compensation circuit is coupled to the input terminal of the power stage and is operable in a plurality of selectable configurations that are respectively tailored to the plurality of operating modes. The plurality of selectable configurations are selectable in response to a control signal representative of a current operating mode of the load circuit.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: September 7, 2021
    Assignee: STMicroelectronics SA
    Inventors: Lionel Vogt, Eoin Padraig O Hannaidh
  • Patent number: 11115040
    Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: September 7, 2021
    Assignee: eTopus Technology Inc.
    Inventor: Danfeng Xu
  • Patent number: 11101807
    Abstract: One example includes a phase-locked loop (PLL) circuit. The circuit includes a frequency divider and phase detector configured to generate a plurality of non-overlapping switching signals based on an input signal and a PLL output signal. The circuit also includes a linear frequency-to-current (F2I) converter configured to generate a control current having an amplitude that is based on the plurality of non-overlapping switching signals. The circuit further includes a linear current-controlled oscillator configured to generate the PLL output signal to have a frequency and phase to be approximately equal to the input signal based on the amplitude of the control current.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Erhan Ozalevli, Mustapha El Markhi, Tuli Dake
  • Patent number: 11099539
    Abstract: Apparatus, methods, and systems implementing multi-sensor agent devices are described herein. The agent devices can each include a plurality of sensors for measuring parameters of interest to an entity such as an electric power utility. The sensors can be organized in individually-IP-addressable sensor clusters, with each sensor cluster including an associated microcontroller. The agent devices can be controlled by a control center of the entity to operate in a coordinated manner, such as to gather and transmit data regarding parameters of interest. The agent devices can be transported to desired areas for data collection by unmanned aerial systems such as drones, and the collected data can be stored in a distributed blockchain ledger.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: August 24, 2021
    Assignee: UT-Battelle, LLC
    Inventors: Peter L. Fuhr, Marissa E. Morales-Rodriguez, Sterling S. Rooke