Abstract: Disclosed is an interface circuit including a first parallel-to-serial conversion circuit suitable for converting inverted parallel data in a parallel-to-serial manner to generate first output data in a test mode; a second parallel-to-serial conversion circuit suitable for converting non-inverted parallel data in the parallel-to-serial manner to generate second output data in the test mode; a third parallel-to-serial conversion circuit suitable for converting the non-inverted parallel data in the parallel-to-serial manner to generate third output data in the test mode; a fourth parallel-to-serial conversion circuit suitable for converting the inverted parallel data in the parallel-to-serial manner to generate fourth output data in the test mode; a first driver circuit suitable for receiving the first and second output data in the test mode; and a second driver circuit suitable for receiving the third and fourth output data in the test mode.

Abstract: Techniques and apparatus for alias rejection in analog-to-digital converters (ADCs), in which only a portion of the ADC is operated at a higher sampling rate than other portions of the ADC, thereby preventing aliasing, but saving power. One example ADC circuit generally includes a first circuit portion configured to operate at a first clock rate equal to a sampling rate of the ADC circuit; and a second circuit portion configured to operate at a second clock rate higher than the sampling rate of the ADC circuit.

Abstract: In a display driver circuit, a push-pull circuit is coupled to an internal circuit, a first external power terminal, a second external power terminal and a target node respectively, and can control the on-off of the first external power terminal, the second external power terminal and the target node in response to a target control signal transmitted by the internal circuit. The switching circuit is coupled to the target node and the I/O interface of the display driver circuit respectively, and can transmit an electric potential of the target node to the I/O interface of the display driver circuit, that is, a first power signal transmitted from the first external power terminal to the target node or a second power signal transmitted from the second external power terminal to the target node is further output to the I/O interface.

Abstract: An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal with an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into multiple pulses in response to a reset command. The compensation circuit generates, responsive to the reset command, compensation pulses to compensate the multiple pulses.

Abstract: Methods for operating two or more analog-to-digital converters (ADCs) are presented herein. The method may be implemented in an integrated circuit. The integrated circuit may include a first ADC and a second ADC disposed on a single semiconductor die. The integrated circuit may also include logic circuitry operably coupled to the first and second ADCs. For a digital value obtained by conversion, by the first ADC, of a first analog signal sampled by the first ADC during a period of time overlapping with another period of time during which a second analog signal is being converted by the second ADC, the logic circuitry may be configured to cause the digital value to be marked as noisy.

Abstract: An analog-to-digital converter circuit incorporating includes a multi-bit input buffer having a differential input and configured to generate, at a plurality of differential outputs, a plurality of residues of a differential input sample relative to a corresponding plurality of zero-crossing references. Chopping stages chop the residues, for example with a pseudo-random binary sequence. The circuit further includes zero-crossing comparators, each with differential inputs coupled to receive one of the chopped residues. The zero-crossing comparators are in an ordered sequence of zone thresholds within the input range of the circuit. Folding logic circuitry has inputs coupled to outputs of the comparators, and outputs a delay domain signal indicating a magnitude of the one of the residues relative to a nearest zone threshold. Digital stage circuitry generates a digital output word representing the received input sample responsive to the comparator outputs and the delay domain signal.

Abstract: An integrated circuit includes a set of N unit analog-to-digital converters (ADCs) having a common architecture, and which provide an aggregate data rate. Moreover, the integrated circuit includes control logic that selects subsets of the set of N unit ADCs in order to realize sub-ADCs of different data rates that can each be an arbitrary integer multiple of an inverse of N times the aggregate data rate of the N unit ADCs. Furthermore, the control logic may dynamically select the subsets on the fly or on a frame-by-frame basis. This dynamically selection may occur at boot time and/or a runtime. Additionally, the given different data rate may correspond to one or more phases of a multi-phase clock in the integrated circuit, where the multiphase clock may include a number of phases corresponding to a number of possible subsets, and given selected subsets may not use all of the available phases.

Abstract: N (n is a natural number) power converters operate in accordance with a drive signal to generate a power to be supplied to a load. Multi-redundant A/D converters convert an analog detection value from the power converters into digital values. First and second controllers operate in parallel and each generate a drive signal of the power converters using the digital values from the A/D converters. A system selector selects one controller in accordance with an abnormality detection result of the first and second controllers. Each of n output selectors receives the drive signals from both of the first and second controllers and outputs the drive signal from the one controller selected by the system selector to the power converters.

Abstract: A method for execution by an input/output (IO) control module of an integrated circuit (IC) includes determining whether a programmable IO interface module is for dynamic or static use. The programmable IO interface module includes a configurable front-end module and a configurable back-end module. When the programmable IO interface module is for the dynamic use, determining to configure the programmable IO interface module as the dynamic use of a configuration of a plurality of configurations. The plurality of configurations includes a bidirectional interface, an input, an output, a concurrent drive and sense interface, and a concurrent transmit-receive interface. The method further includes configuring the front-end module in accordance with the configuration, configuring the back-end module in accordance with the configuration, and determining whether to change the configuration to another configuration of the plurality of configurations.

Abstract: An image forming apparatus (100) includes a photoelectric conversion portion (24) that receives light reflected by a document sheet and outputs an electric signal based on the light, a posture adjustment portion (400) having an operation shaft (34) rotatable about a first axis (AX1) and that adjusts a posture of the photoelectric conversion portion (24) according to rotation of the operation shaft (34), and a stimulus output portion (402) that outputs a stimulus perceivable by an operator of the operation shaft (34) each time the operation shaft (34) is rotated by a predetermined specific angle.

Abstract: A calibration unit and method therein for calibrating a TDC comprised in a digital PLL are disclosed. The TDC receives a signal from a free-running DCO and a reference signal, and measures the time difference between the DCO and reference signals. The calibration unit receives and processes data samples output from the TDC and generates a calibration lookup table in which each TDC output value has a calibration value. The calibration lookup table may be used for post-distortion. For each TDC output level the corresponding calibration value from the lookup table may be added to the output of the TDC for correction.

Abstract: An interleaved analog-to-digital conversion (ADC) system may have timing errors in a time domain that is corrected using phase compensation in a phase domain. The ADC system may include sub-ADCs, each receiving a clock signal, which is associated with a representation of a timing skew value, reflecting an undesired timing error. A mixer may have sub-mixers, each receiving a sub-ADC output signal and a compensated numerically controlled oscillator (NCO) value. A combiner may combine the sub-mixer output signals. A decimator may decimate the output of the combiner. Each timing skew value is in a time domain. A compensated NCO value is determined using a respective phase skew value. Each phase skew value is an offset value in phase and is not a value in time. Each phase skew value in a phase domain compensates the respective timing skew value in a time domain. Multiple ADC systems and methods are described.

Abstract: Embodiments of multi-mode sigma-delta analog-to-digital converter (ADC) circuits and a microphone circuit are disclosed. In an embodiment, a multi-mode sigma-delta ADC circuit includes a pair of operational transconductance amplifiers (OTAs), a filter connected to the pair of OTAs, a quantizer connected to the filter, a differential digital-to-analog converter (DAC) connected to the quantizer, and a controller configured to switch the multi-mode sigma-delta ADC circuit between a single-ended operational mode, a pseudo differential operational mode, and a full differential operational mode to improve common mode rejection (CMR) performance by controlling the pair of OTAs. An output of a microphone and a differential output of the differential DAC are inputted into input terminals of the pair of OTAs.

Abstract: The present invention discloses an analog-to-digital conversion circuit having remained time measuring mechanism is provided. A digital-to-analog conversion (DAC) circuit samples input voltages to generate output voltages. A comparator compares the output voltages to generate a comparison result. A control circuit switches a configuration of the DAC circuit by using a digital code according to the comparison result. A comparison determining circuit sets a stage indication signal at a finished state after the comparison result is generated. A comparison stage counting circuit accumulates a termination number according to the stage indication signal to set a conversion indication signal at the finished state when the termination number reaches a predetermined number. A time accumulating circuit starts to accumulate a remained time when the conversion indication signal is at the finished state and finishes accumulation when a sampling indication signal is at a sampling state.

Abstract: The disclosure provides a data acquisition device. The data acquisition device includes a sensor that detects a physical quantity as analog data; a digital storage circuit that stores the physical quantity as digital data; a difference circuit that calculates a difference between a previous value of the physical quantity stored in the digital storage circuit and a current value of the physical quantity detected as analog data; and a comparison circuit that compares the difference with a predetermined threshold value; and a control unit. The control unit stores a value calculated by adding or subtracting a predetermined change amount to a previous value of the physical quantity stored in the digital storage circuit as the current value, when the difference exceeds or falls below the threshold value. Since the physical quantity is updated without executing A/D conversion, a decrease in the sampling frequency is suppressed.

Abstract: An analog-to-digital converter of one embodiment in the present disclosure may comprise a first conversion unit generating an internal clock signal, generating a first digital code and a residual signal by converting an input signal in a successive approximation register (SAR) method in response to the internal clock signal and generating a flash clock signal in response to an external clock signal, a second conversion unit generating a second digital code by converting the residual signal in a flash method in response to the flash clock signal, and an output circuit generating an output digital signal in response to the first digital code and the second digital code.

Abstract: A sampling capacitor structure, which includes a Faraday Shield that can be switched between various nodes. In a switched capacitor circuit, this sampling capacitor structure allows for differential charging of the sampling capacitor while minimizing the effects of any parasitic stray capacitor. Furthermore, with appropriate switching of the Faraday Shield, once the differential charge sampling circuit samples the differential signal, this sampled differential charge can then be transferred to a downstream single-ended circuit, such as an integrator, without any loss of signal.

Abstract: A tracking ADC with a feed-forward loop is disclosed. The tracking ADC includes a feedback circuit configured to generate a feedback signal using an input voltage and a comparison circuit configured to sample, using a plurality of threshold values, the feedback signal to generate a plurality of samples. A counter circuit is configured to update a count value using a subset of the plurality of samples. A digital-to-analog converter (DAC) circuit configured to generate a control signal using the count value. The feedback circuit is further configured to modify the feedback signal using the control signal and at least one of the plurality of samples. By modifying the feedback voltage, the settling time may be reduced, allowing the ADC to be run at a higher clock speed.

Abstract: A method of operating a wind converter is provided. The method includes receiving a plurality of forecasted datasets. The forecasted datasets include event signals for the wind converter during fast transient operating conditions (OCs) and operational data for the wind converter having a low sampling rate. The method further includes estimating a converter life consumption during normal OCs and a converter life consumption during the fast transient OCs. Further, the method includes computing a total converter life consumption of the wind converter. Moreover, the method includes predicting, using a remaining useful life (RUL) prediction module, an RUL for the wind converter based on the total converter life consumption. The method further includes adjusting operation of the wind converter by adjusting operating variables of the wind converter.

Abstract: Digital post-processing of time-to-digital converter (TDC) output data can be used to map each TDC code to the ideal one, but this requires knowing the TDC input-output mapping. Therefore, a calibration system and method are provided for characterizing operation of a TDC to compensate for non-idealities. Input signals having a known time difference are provided to the TDC, and a mapping between the TDC output and the known time difference is stored in a mapping table. With the described method, it is possible to input an input ramp of very low slope to construct this mapping to a desired resolution during a background calibration procedure. This characterizing and mapping can be performed across a range of input signals having different known time differences. After calibration, a mapping table can be used by a mapping circuit of the TDC or by a digital post-processing function to provide a compensated TDC output.

Abstract: An analog-to-digital converter includes a primary converter and a secondary converter. The primary converter executes conversion processing to convert an analog input signal to a first digital signal through delta-sigma modulation. The secondary converter outputs a second digital signal by converting amplified analog output of a quantization error in the primary converter to the second digital signal.

Abstract: A photodetection device according to the present disclosure includes: a first pixel that is configured to generate a first pixel signal; a reference signal generator that is configured to generate a reference signal; and a first comparator including a first power supply circuit and a first comparison circuit, the first power supply circuit configured to generate a first power supply voltage on the basis of a power supply voltage supplied from a first power supply node and a bias voltage and configured to output the first power supply voltage from an output terminal, and the first comparison circuit configured to operate on the basis of the first power supply voltage and configured to perform a comparison operation on the basis of the first pixel signal and the reference signal.

Abstract: A time-interleaved analog-to-digital converter (TIADC) operates in a first mode or a second mode and includes M analog-to-digital converters (ADCs), a reference ADC, a digital correction circuit, and a control circuit. The M ADCs sample an input signal according to M enable signals to generate M digital output codes. The reference ADC samples the input signal according to a reference enable signal to generate a reference digital output code. The digital correction circuit corrects the M digital output codes to generate M corrected digital output codes. The control circuit generates the M enable signals and the reference enable signal according to a clock. The control circuit outputs the M corrected digital output codes in turn but does not output the reference digital output code in the first mode and randomly outputs the M corrected digital output codes and the reference digital output code in the second mode.

Abstract: This specification discloses a brain electrode device. The brain electrode device includes a set of contact points and a set of sub-circuits. The sub-circuits include sensor ports configured to connect to the contact to the respective ones of the contact points. The device can further include an intelligent multiplexer that aggregates signals from the set of sub-circuits and generates an aggregate signal. The aggregate signal is transmitted to a signal acquisition device.

Abstract: Devices and methods for determining the cumulative distribution of a polymer property in a reactor without physical separation of reaction subcomponents. The device includes a means of measuring an instantaneous property of the polymers being produced in a reaction vessel a plurality of times during a polymerization reaction as well as a means of determining the corresponding change in polymer concentration in the reaction vessel between measurements of the instantaneous polymer property. The device also includes a means of computing a statistical distribution appropriate to the polymer characteristic and applying the statistical distribution to a recently measured instantaneous value of the polymer property so as to have an instantaneous distribution of the polymer property and a means of adding together the instantaneous distributions of the polymer property in order to obtain the cumulative distribution of the polymer property in the reactor.

Abstract: Some embodiments provide a Quanta Image Sensor (QIS) comprising 3D vertically-stacked photosensor array and readout circuitry. In some embodiments, an imaging array comprises a plurality of single-bit or multi-bit jots, and readout circuitry in electrical communication with the imaging array and configured to quantize, for each jot, an analog signal corresponding to the electrical signal of the jot, wherein the imaging system is configured as a 3D vertically integrated circuit with the imaging array stacked vertically above the readout circuitry. The imaging array may be configured as an array of clusters with respect to the readout circuitry, each cluster configured as an array of n by m jots. The imaging array may include a further image processing circuitry layer disposed below the readout circuitry layer. Neighboring layers may be implemented on separate substrates and/or in a common substrate.

Abstract: A confined data communication system includes a reference generation circuit operable to produce one or more analog reference signals, an analog to digital converter circuit operable to process an analog signal to produce a digital representative signal, a digital filtering circuit operable to filter the digital representative signal to produce an affect value, a data processing module operable to interpret the affect value to produce processed output data, and a processing module operable to set frequency and waveform for each of the one or more analog reference signals, set digital filtering parameters for the digital filtering circuit, set a sampling rate for the analog to digital converter circuit, and set data interpretation parameters for the data processing module.

Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

Abstract: A method of calibrating an analog front end (AFE) filter of a radio frequency integrated circuit (RFIC) includes: making a first measurement of the RFIC at a first measuring frequency while the AFE filter is bypassed; generating a first amplitude estimate and a first phase estimate at the first measuring frequency using the first measurement; making a second measurement of the RFIC at the first measuring frequency while the AFE filter is turned on; generating a second amplitude estimate and a second phase estimate at the first measuring frequency using the second measurement; and calculating a frequency response of the AFE filter at the first measuring frequency, which includes calculating an amplitude response of the AFE filter based on the second amplitude estimate and the first amplitude estimate; and calculating a phase response of the filter based on the first phase estimate and the second phase estimate.

Abstract: The present disclosure discloses a touch sensing signal processing circuit which senses a change in capacitance of a sensing node for touch sensing and provides a logic signal corresponding to the touch sensing. The touch sensing signal processing circuit of the present disclosure is configured using a delta-sigma analog to digital converter. Auto-tuning may be performed by delta-sigma analog conversion.

Abstract: A digital-to-analog converter comprising: a plurality of capacitances and a plurality of switches. A capacitance among the plurality of capacitances, of which the number corresponds to the resolution of the analog signal to be output, is used as a voltage value generation capacitance, so as to generate a voltage value based on the reference voltage to be added or subtracted, by switching a node to which the second terminal is connected by a corresponding switch. A remaining capacitance, which is not used as the voltage value generation capacitance among the plurality of capacitances, is used as a gain adjustment capacitance, so as to adjust gain of a voltage value based on the reference voltage to be added or subtracted, by holding a node to which the second terminal is connected by a corresponding switch.

Abstract: Disclosed is an image sensing device including a plurality of current cells whose total number to be used is adjusted based on a plurality of enable signals, and which are sequentially controlled based on a reset signal and a plurality of selection signals; a current-voltage conversion circuit suitable for converting a plurality of unit currents, which are supplied from current cells used among the plurality of current cells, into a ramp signal; and a first control circuit suitable for generating the plurality of enable signals based on a maximum conversion code value corresponding to a slope of the ramp signal.

Abstract: Clock and other cyclical signals are driven onto respective capacitively-loaded segments of a distribution path via inverting buffer stages that self-correct for stage-to-stage duty cycle error, yielding a balanced signal duty cycle over the length of the distribution path.

Abstract: A multiply-and-accumulate (MAC) circuit having a plurality of compute-in-memory bitcells is configured to multiply a plurality of stored weight bits with a plurality of input bits to provide a MAC output voltage. A successive approximation analog-to-digital converter includes a capacitive-digital-to-analog-converter (CDAC) configured to subtract a bias voltage from the MAC output voltage to provide a CDAC output voltage. A comparator compares the CDAC output voltage to a fixed reference voltage.

Abstract: A method for execution by an input/output (IO) control module of an integrated circuit (IC) includes determining whether a programmable IO interface module is for dynamic or static use. The programmable IO interface module includes a configurable front-end module and a configurable back-end module. When the programmable IO interface module is for the dynamic use, determining to configure the programmable IO interface module as the dynamic use of a configuration of a plurality of configurations. The plurality of configurations includes a bidirectional interface, an input, an output, a concurrent drive and sense interface, and a concurrent transmit-receive interface. The method further includes configuring the front-end module in accordance with the configuration, configuring the back-end module in accordance with the configuration, and determining whether to change the configuration to another configuration of the plurality of configurations.

Abstract: An electronic device may include wireless circuitry having analog-to-digital converter (ADC) circuitry. The ADC circuitry may include a sampling switch coupled to a bootstrap circuit. The bootstrap circuit may include a bootstrap capacitor, a first transistor coupled between an input of the sampling switch and a bottom plate terminal of the bootstrap capacitor, a second transistor coupled between the bottom plate terminal of the bootstrap capacitor and ground, and a resistor or transistor that is disposed between the first transistor and the bottom plate terminal of the bootstrap capacitor and that is configured to boost the input impedance of the bootstrap circuit.

Abstract: An analog-to-digital converter includes a first converter stage, a second converter stage coupled to the first converter stage to quantize a residue signal of the first converter stage, and an inter-stage converter disposed between the first and second converter stages. The inter-stage converter is configured to convert between a first domain and a second domain. The inter-stage converter is configured to process the residue signal of the first converter stage such that a range of the residue signal matches a full scale of the second converter stage.

Abstract: Systems and methods for processing and storing digital information are described. One embodiment includes a method for linearizing digital-to-analog conversion including: receiving an input digital signal; segmenting the input digital signal into several segments, each segment being thermometer-coded; generating a redundant representation of each of the several segments, defining several redundant segments; performing a redundancy mapping for the several segments, defining redundantly mapped segments; assigning a probabilistic assignment for redundantly mapped segments; converting each redundantly mapped segment into an analog signal by a sub-digital-to-analog converter (DAC); and combining the analog signals to define an output analog signal.

Abstract: A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

Abstract: A device for providing side-channel protection to a data processing circuit is provided and includes a chaotic oscillator and a counter. The data processing circuit has an input for receiving an input signal, a power supply terminal, and an output for providing an output signal. The chaotic oscillator circuit has an input coupled to receive a control signal, and an output coupled to provide an output signal for controlling a voltage level of a power supply voltage of the data processing circuit. The counter has an input coupled to receive a clock signal, and an output coupled to control a variable parameter of the chaotic oscillator in response to the clock signal. In another embodiment, a method is provided providing the side-channel protection to the device.

Abstract: One example discloses a differential-signal-detection circuit, comprising: an input stage configured to receive a differential input signal and to output a first differential output signal and a second differential output signal; a first comparator coupled to receive the first differential output signal and generate a first comparator output signal; a second comparator coupled to receive the second differential output signal and generate a second comparator output signal; and an output stage configured to receive the first and second comparator output signals and generate a differential-signal-detection signal.

Abstract: A digital-to-analog conversion, including: converting signal Y using word X=M+???N having length ?=?+? digits, where M is high order digits of ? long control word X, ???N is low order digits of ? long control word X, wherein ???; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z1 is proportional to M? long high order digits of X, and to reference signal Y1, where Z1=Y1×M, in the second and third conversions, signals Z2 and Z3 are proportional to N? long low order digits of X and to signals Y1 and Y2, respectively, where Z2=Y1×N, and Z3=Y2×N, wherein, before the conversions, ???N low order digits of X are multiplied by ??; and adding Z1, Z2, Z3 to generate output signal Z0, wherein Y1 and Y2 relate by Y2=Y1(1±???), wherein ? is the base of the numbering system, ? is the number of digits, by which ???N is shifted.

Abstract: Sensors, including time-of-flight sensors, may be used to detect objects in an environment. In an example, a vehicle may include a time-of-flight sensor that images objects around the vehicle, e.g., so the vehicle can navigate relative to the objects. Sensor data generated by the time-of-flight sensor can return pixels subject to over-exposure or saturation, which may be from stray light. In some examples, multiple exposures captured at different exposure times can be used to determine a saturation value for sensor data. The saturation value may be used to determine a threshold intensity against which intensity values of a primary exposure are compared. A filtered data set can be obtained based on the comparison.

Abstract: Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

Abstract: An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.

Abstract: An imaging system according to the present disclosure includes: an imaging device that is mounted in a vehicle, and captures and generates an image of a peripheral region of the vehicle; and a processing device that is mounted in the vehicle, and executes processing related to a function of controlling the vehicle on the basis of the image. The imaging device includes: a first control line, a first voltage generator that applies a first voltage to the first control line, a first signal line, a plurality of pixels that applies a pixel voltage to the first signal line, a first dummy pixel that applies a voltage corresponding to the first voltage of the first control line to the first signal line in a first period, a converter including a first converter that performs AD conversion on the basis of a voltage of the first signal line in the first period to generate a first digital code, and a diagnosis section that performs diagnosis processing on the basis of the first digital code.

Abstract: The present application discloses a successive approximation register analog-to-digital converter with passive noise shaping, which comprises: switch capacitor arrays for acquiring analog input signals; a noise shaping circuit which is a passive integral network, the network has input ends connected respectively with output ends of the two switch capacitor arrays and for acquiring output signals of the two switch capacitor arrays, is composed of a plurality of sub passive integrators, and reconfigures the plurality of sub passive integrators to different circuit forms; a comparator which has two input ends connected respectively with output ends of the passive integral network and an output end connected with an input end of a logic circuit, and is configured to compare magnitudes of the output signals of the noise shaping circuit.

Abstract: An analog to digital conversion circuit includes an analog to digital converter (ADC) circuit operable to convert an analog signal having an oscillation frequency into a first digital signal having a first data rate frequency. The analog signal includes a set of pure tone components. The first digital signal includes n 1-bit channels. The analog to digital conversion circuit further includes a digital decimation filtering circuit including n anti-aliasing filters operable to sample and filter the n 1-bit channels of the first digital signal to produce n second digital signals and n decimator circuits operable to decimate the n second digital signals to produce n third digital signals at a second data rate frequency. The analog to digital conversion circuit further includes a multiplexor operable to output the n third digital signals at the second data rate frequency on a single bus.

Abstract: A receiver having analog-to-digital converters (ADC) is disclosed. The ADCs may be reconfigured based on the insertion loss mode of the receiver. For example, different portions of a plurality of time-interleaved successive approximation (SAR) ADC slices included in at least one sub-ADC of each time-interleaved ADC may be enabled depending on which of a plurality of insertion loss modes is selected for operation of the receiver.

Abstract: There is provided an imaging device including a pixel array section including pixel units two-dimensionally arranged in a matrix pattern, each pixel unit including a photoelectric converter, and a plurality of column signal lines disposed according to a first column of the pixel units. The imaging device further includes an analog to digital converter that is shared by the plurality of column signal lines.