Analog To Digital Conversion Patents (Class 341/155)
  • Patent number: 10725489
    Abstract: A semiconductor device including a resistance section that includes a first terminal and a second terminal disposed in contact with an outer periphery, and a serial resistance section in which plural resistance elements are connected in series, wherein one end of the serial resistance section is connected to the first terminal, and another end of the serial resistance section is connected to the second terminal; and a current adjustment section that includes a current source that supplies current to the serial resistance section, and disposed adjacent to the resistance section such that a distance between the first terminal and the current adjustment section along the outer periphery of the resistance section and a distance between the second terminal and the current adjustment section along the outer periphery of the resistance section are equal.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: July 28, 2020
    Assignee: LAPIS SEMICONDUCTOR CO., LTD.
    Inventor: Hiroyuki Kikuta
  • Patent number: 10725433
    Abstract: Time-to-digital conversion circuitry converts a time between a start time point and a stop time point, which are state-change time points of digital signals, into digital. The time-to-digital conversion circuitry comprises oscillation circuitry that outputs a plurality of phase signals having different phases, and outputs a digital value of the time based on the plurality of phase signals. The oscillation circuitry performs free-running oscillation and outputs the phase signals that do not synchronize with the start time point and the stop time point.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: July 28, 2020
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Yoshihisa Fujimoto
  • Patent number: 10720934
    Abstract: Time-interleaved analog-to-digital converters (ADCs) and related methods are disclosed that are based upon multiplying digital-to-analog converters (MDACs). For one ADC embodiment, a sample-and-hold circuit receives an input signal and outputs a voltage that represents the input signal. An MDAC receives the voltage, outputs an N-bit digital value, and outputs a current that represents the voltage. A phased current generator receives the current and outputs time-interleaved currents that are based upon the current. An array of sub-ADCs receive the time-interleaved currents, and each sub-ADC outputs a digital value. The digital values from the array of sub-ADCs are then combined and to output an M-bit digital value. The N-bit digital value and the M-bit digital value provide a digital conversion output for the ADC.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 21, 2020
    Assignee: NXP USA, Inc.
    Inventors: Brandt Braswell, George Kunnen, Mark Lancaster
  • Patent number: 10715167
    Abstract: This invention discloses a control circuit and a control method of a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC includes a comparator and a switched-capacitor digital-to-analog converter (DAC). The control circuit includes a memory, an inverter and a data path. The memory is configured to store an output value of the comparator. The inverter has an output coupled to a first end of a capacitor of the switched-capacitor DAC. A second end of the capacitor is coupled to an input of the comparator. The data path, coupled between an output of the comparator and an input of the inverter, temporarily causes a voltage at the first end of the capacitor to be controlled by the output value of the comparator. The data path does not contain any memory.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: July 14, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Sheng Hsiung Lin, Shih-Hsiung Huang
  • Patent number: 10707889
    Abstract: An electronic circuit comprises multiple analog-to-digital converter (ADC) circuits and control logic circuitry. The control logic circuitry advances the multiple ADC circuits through multiple time-interleaved conversions that include time-interleaved acquisition phases, conversion phases, and tracking phases. An acquisition phase of a first ADC circuit samples the analog signal, a conversion phase of the first ADC circuit converts the sampled analog signal to a digital value, and the control logic circuitry is configured to update the first ADC circuit with most recent A/D conversion information by a different ADC circuit during a tracking phase of the first ADC circuit before the acquisition phase of the first ADC circuit.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: July 7, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: Rares Andrei Bodnar, Christopher Peter Hurrell, Asif Ahmad
  • Patent number: 10708529
    Abstract: An image sensor may include an array of pixels, and analog and digital circuitry. The pixels in the array may generate image signals in response to incident light. The image sensor may also include power supply circuitry and corresponding voltage rail structures that provide voltage levels to operate the pixel array, the analog circuitry, and the digital circuitry. The power supply circuitry may provide a low voltage, a high voltage, and an intermediate voltage power rail. The analog circuitry may operate in a voltage level domain defined by voltages between an intermediate voltage level and a high voltage level. The digital circuitry may operate in a voltage level domain defined by voltages between a low voltage level and the intermediate voltage level. In such a configured, analog and digital circuitry may both be provided with low-voltage transistors that are more area and power efficient and that are more scalable.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: July 7, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Raminda Madurawe
  • Patent number: 10702183
    Abstract: A biopotential monitoring device and use of such device. The device includes a configurable receiver circuit having a plurality of channels for receiving a plurality of biopotential signals from a biological tissue via a plurality of inputs coupled with the electrodes, and each channel substantially removes a DC (direct current) offset from a corresponding one of the biopotential signals and then band-pass amplifies such corresponding biopotential signal at a configurable gain and particular frequency range based on frequency control signals. The device further includes a controller circuit for receiving commands for configuring frequency characteristics of each biopotential signal. The controller automatically generates the frequency control signals based on such commands and outputs such frequency control signals to the configurable receiver circuit. The controller outputs a representation of each biopotential signal to an analyzer device that is configured to analyze such biopotential signal.
    Type: Grant
    Filed: May 12, 2016
    Date of Patent: July 7, 2020
    Assignee: Intan Technologies, LLC
    Inventor: Reid R. Harrison
  • Patent number: 10700692
    Abstract: Processing circuitry comprising: a reference node for connection to a reference voltage source so as to establish a local reference voltage signal at the reference node; a signal processing unit connected to the reference node and operable to process an input signal using the local reference voltage signal, wherein the signal processing unit is configured to draw a current from the reference node at least a portion of which is dependent on the input signal; and a current-compensation unit connected to the reference node and operable to apply a compensation current to the reference node, wherein the current-compensation unit is configured, based on an indicator signal indicative of the input signal and/or of the operation of the signal processing unit, to control the compensation current to at least partly compensate for changes in the current drawn from the reference node by the signal processing unit due to the input signal.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: June 30, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Niklas Linkewitsch, Guido Dröge, Charles Joseph Dedic
  • Patent number: 10692549
    Abstract: A memory array structure that includes memory columns having first bit lines and second bit lines is introduced. Each of the memory columns includes a bit line pair, a pre-charge switch pair and a first switch pair. Output voltages from the first bit lines and the second bit lines are used to generated a first average voltage and a second average voltage, respectively. One of the first average voltage and the second average voltage is a lower average voltage and another one of the first average voltage and the second average voltage is a higher average voltage. The pre-charge switch pair and the first switch pair of a selected memory column among the plurality of memory columns are controlled to repeatedly perform an incremental step to increment the lower average voltage by a step voltage until the lower average voltage is greater than the higher average voltage.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yung-Chow Peng, Chin-Ho Chang, Jaw-Juinn Horng
  • Patent number: 10687005
    Abstract: Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: June 16, 2020
    Assignee: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
    Inventors: Daniel Peter Canniff, Edward C. Guthrie, Jonathan Ephraim David Hurwitz
  • Patent number: 10686464
    Abstract: A latched comparator comprises a pre-amplifier stage with a positive input (Vin,p), a negative input (Vin,n); and a differential output (?Vout) comprising a first output (Vout,1) and a second output (Vout,2), the pre-amplifier stage comprising a first cascode pair, comprising a first amplifying transistor (MN2) and a first cascode transistor (MN4) connected at a first cascode node, the first amplifying transistor (MN2) being controlled by the positive input (Vin,p) and the first cascode transistor (MN4) being connected, opposite to the first cascode node, to the first output (Vout,1); a second cascode pair, comprising a second amplifying transistor (MN3) and a second cascode transistor (MN5) connected at a second cascode node, the second amplifying transistor (MN3) being controlled by the negative input (Vin,n) and the second cascode transistor (MN5) being connected, opposite to the second cascode node, to the second output (Vout,2); a first gain-boosting transistor (MN6) connected between the first output (V
    Type: Grant
    Filed: July 10, 2019
    Date of Patent: June 16, 2020
    Assignee: STICHTING IMEC NEDERLAND
    Inventor: Roland Van Wegberg
  • Patent number: 10680632
    Abstract: A TI ADC circuit (30) comprises a plurality of L analog inputs (32-1, 32-2, 32-3) and a plurality of L digital outputs (34-1, 34-2, 34-3). The i:th analog input (32-i) is for receiving an i:th analog input signal. The i:th digital output (34-i) is for outputting an i:th digital output signal, which is a digital representation of the i:th analog input signal. TI ADC circuit (30) comprises a set (90) of sub ADCs (100-1—100-K). The TI ADC circuit (30) is configured to generate one sample of each of the L digital output signals per conversion cycle. Each sub ADC (100-1—100-K) is configured to generate a digital output sample in M conversion cycles, wherein M is an integer >1. The number K of sub ADCs in the set (90) of sub ADCs (100-1—100-K) exceeds L·M.
    Type: Grant
    Filed: July 8, 2016
    Date of Patent: June 9, 2020
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventors: Lars Sundström, Martin Anderson
  • Patent number: 10681297
    Abstract: A comparison device includes an offset generation circuit that includes an input port to receive an offset control signal and is structured to generate an offset based on the received offset control signal; a comparison circuit comprising a first input port coupled to the offset generation circuit to receive a first input signal and a second input port coupled to receive a second input signal that is offset by the offset generated by the offset generation circuit and operable to compare the first input signal with the second input signal to produce a comparison signal; and a control circuit coupled to the comparison circuit to receive the comparison signal and operable to detect a crossing of the first input signal and the second input signal according to the comparison signal circuit and to output the offset control signal to the offset generation circuit.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 9, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyeon-June Kim, Min-Kyu Kim
  • Patent number: 10673456
    Abstract: A conversion and folding circuit includes a voltage-to-delay converter block, including preamplifiers, for converting a voltage signal into delay signals, and a folding block, including logic gates coupled to the preamplifiers, for selecting earlier-arriving and later-arriving ones of the delay signals. If desired, the logic gates may include odd and even chains for outputting delay signals to first and second analog-to-digital converters. If desired, the conversion and folding circuit may include first and second chains, and a chain selection circuit for selectively outputting a delay signal from a desired one of the first and second chains.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shagun Dusad, Chirag Chandrahas Shetty, Visvesvaraya Appala Pentakota
  • Patent number: 10666283
    Abstract: The present invention relates to analogue-to-digital converter (ADC) circuitry. In particular, the present invention relates to ADC circuitry configured to use successive approximation to arrive at a multi-bit digital value representative of an analogue input value.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: May 26, 2020
    Assignee: SOCIONEXT INC.
    Inventors: Niklas Linkewitsch, Charles Joseph Dedic
  • Patent number: 10666281
    Abstract: In accordance with an embodiment, a method for calibrating at least two analog-to-digital converters includes feeding an analog predefined signal to the at least two analog-to-digital converters; converting the analog predefined signal into at least two converter-associated digital values using the at least two analog-to-digital converters, wherein the converting is based on a received clock signal; and adapting a converter-specific time delay based on the at least two converter-associated digital values.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: May 26, 2020
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Martin Pernull, Peter Bogner
  • Patent number: 10659022
    Abstract: In a comparator of an analog-to-digital converter, an input signal is input to a control terminal of each of a plurality of signal input transistors. A signal input transistor selection section selects any one of the plurality of signal input transistors, and generates a current in response to a difference between the input signal and a reference signal to flow in the differential pair configured with the selected signal input transistor and a reference input transistor. A load section converts, at a time of a change of a current flowing in any one of the plurality of signal input transistors and the reference input transistor in response to the difference, the change of the current into a change of a voltage, and outputs the change of the voltage as a result of comparison between the input signal and the reference signal.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: May 19, 2020
    Assignee: Sony Corporation
    Inventor: Masaki Sakakibara
  • Patent number: 10659078
    Abstract: A integrated circuit (IC) chip can include a root timer that generates a frame pulse based on a start trigger signal. The IC chip can also include a hardware clock control that provides a clock signal based on a selected one of the frame pulse and the synchronization signal provided from one of the root timer and another IC chip. The IC chip can further include a plurality of analog to digital converters (ADCs). Each of the plurality of ADCs being configured to sample an output of a respective one of a plurality of radio frequency (RF) receivers based on the clock signal.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: May 19, 2020
    Assignee: TEXAS INTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Brian Ginsburg, Karthik Subburaj
  • Patent number: 10659150
    Abstract: Data isolators for providing isolation between two ports that enable dynamic communication are described. The dynamic communication may be achieved by varying a ratio of the data rate relative to a clock frequency of a clock signal. The data isolator may include a first circuit that transmits data across an isolation barrier when the clock signal is in a first state and a second circuit that transmits data across the isolation barrier when the clock signal is in a second state. The clock frequency may be variable and, as a result, change the duration of data transmissions in a given clock cycle. For example, the clock frequency may be reduced to increase the number of bits transmitted per clock cycle and, conversely, increased to reduce the number of bits transmitted per clock cycle. Thus, the number of bits transmitted per clock cycle may be adjusted to suit the situation.
    Type: Grant
    Filed: August 5, 2019
    Date of Patent: May 19, 2020
    Assignee: Analog Devices, Inc.
    Inventor: Lawrence Getzin
  • Patent number: 10651811
    Abstract: A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: May 12, 2020
    Assignee: NXP USA, Inc.
    Inventors: Douglas A. Garrity, Mariam Hoseini, Mohammad N. Kabir, Brandt Braswell
  • Patent number: 10652498
    Abstract: A photoelectric conversion device includes a pixel block including a plurality of pixels, a signal generating block, and a signal processing block. Each of the plurality of pixels includes a photoelectric conversion element to photoelectrically convert light striking the photoelectric conversion element into pixel data and output the pixel data; and a reset unit to reset electrical charge of the photoelectrically converted pixel data light and output a reset signal. The signal generating block includes a reference signal generator to generate a reference signal. The signal processing block performs correlated double sampling (CDS) on the reference signal to obtain correction data, and perform CDS on the pixel data and the reset signal to generate an output signal to correct the output signal with the correction data.
    Type: Grant
    Filed: July 9, 2018
    Date of Patent: May 12, 2020
    Assignee: RICOH COMPANY, LTD.
    Inventors: Yuuya Miyoshi, Tohru Kanno
  • Patent number: 10649012
    Abstract: A transmission interface module includes a receiving unit, a transmitting unit, a multiplexer, and a processing unit. An output terminal and a control terminal of the receiving unit are electrically connected to the processing unit. The input terminal and the control terminal of the transmitting unit are electrically connected to the processing unit, and the control terminal of the multiplexer is electrically connected to the processing unit. The transmission interface module respectively adjusts a turn-on state or a turn-off state of the analog power terminal, the digital power terminal, the processing unit, the receiving unit, the transmitting unit, and the multiplexer through a plurality of operation modes to transmit the detecting signals.
    Type: Grant
    Filed: July 19, 2019
    Date of Patent: May 12, 2020
    Assignee: ALTEK SEMICONDUCTOR CORPORATION
    Inventor: Ching-yen Chang
  • Patent number: 10637495
    Abstract: A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily. Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated).
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: April 28, 2020
    Assignee: ANALOG DEVICES, INC.
    Inventors: Junhua Shen, Mark D. Maddox, Ronald Alan Kapusta
  • Patent number: 10630305
    Abstract: A self-calibrating analog-to-digital converter includes a reference signal circuit configured to provide a reference signal, an analog-to-digital converter configured to generate a first digital representation of the reference signal, a dual-slope analog-to-digital converter configured to generate a second digital representation of the reference signal, and a digital engine configured to compare the first digital representation with the second digital representation to obtain a difference and output a calibration signal to the analog-to-digital converter in response to the difference. The reference signal circuit, the analog-to-digital converter, the dual-slop analog-to-digital converter, and digital engine are integrated in an integrated circuit.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: April 21, 2020
    Assignee: SHENZHEN GOODIX TECHNOLOGY CO., LTD.
    Inventors: Ali Farid, Ahmed Emira, Hassan Elwan
  • Patent number: 10623670
    Abstract: An integration circuit having multiple wells that allow for the simultaneous storage of charge during an integration interval and techniques for using the same provide benefits in dynamic range that enhance the performance of pixels. The circuit and techniques described herein could also be used in many different infrared focal plane array applications where higher dynamic range is desired and multiple gain state outputs are allowed.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: April 14, 2020
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventor: Allen W. Hairston
  • Patent number: 10615814
    Abstract: The present invention discloses a pipelined analog-to-digital converter (ADC) including a sub-ADC, a multiplying digital-to-analog converter (MDAC) and a decoder. The decoder provides a ground signal for the MDAC. The sub-ADC is electrically connected to a ground pad via a first metal trace, and the decoder is electrically connected to the ground pad via a second metal trace.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: April 7, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Chien-Ming Wu, Liang-Huan Lei, Shih-Hsiung Huang
  • Patent number: 10608659
    Abstract: An A/D converter includes an A/D conversion circuit for converting an analog output signal into a digital signal, and a control circuit for controlling the A/D conversion circuit. The control circuit acquires a digital signal of a first bit indicating which level regions the voltage level of the analog output signal corresponds to in accordance with a first conversion operation by the A/D conversion circuit, sets a reference voltage corresponding to the level region based on the first bit, amplifies the difference voltage between the analog output signal and the reference voltage to correspond to the A/D conversion input range of the A/D conversion circuit, outputs an amplified analog signal, acquires a digital signal of a second bit indicating the voltage level of the amplified analog signal in accordance with a second conversion operation by the A/D conversion circuit, and synthesizes the first bit and the second bit.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: March 31, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuyuki Tanaka, Masaaki Tanimura
  • Patent number: 10587832
    Abstract: An analog to digital converting circuit includes a correlated double sampling circuit (CDS) that compares a pixel signal with a ramp signal, and outputs a comparison signal, a timing amplifier that increases an active time of the comparison signal “N” times, and outputs an extended signal, wherein the “N” is a positive integer, and a counter that outputs a digital signal corresponding to the pixel signal in response to the extended signal and a first clock signal.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: March 10, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yunhong Kim, Kyung-Min Kim, Heesung Chae
  • Patent number: 10575799
    Abstract: An apparatus for collecting data is provided. According to an example, the apparatus for collection data may include: n number of detector arrays, n number of DAS circuits and a back-end processor. Each of the DAS circuits may include an analog-to-digital converter and a front-end processor coupled with the analog-to-digital converter. Each of front-end processors is coupled with the back-end processor via an independent transmission line. For each of the detector arrays, the detector array may be configured to output analog signals based on detected scanning rays penetrating through a subject. The analog-to-digital converter may be configured to perform an analog-to-digital conversion on the analog signals to generate raw data. The front-end processor may be configured to logarithmically compress the raw data and transmit the logarithmically-compressed raw data to the back-end processor via the transmission line.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: March 3, 2020
    Assignee: Shenyang Neusoft Medical Systems Co., Ltd.
    Inventor: Xiaoqing Hu
  • Patent number: 10581452
    Abstract: An A/D converter includes: an integrator circuit executing ?? modulation to an analog signal to be converted; an adder outputting an addition result of at least an output signal of the integrator circuit and a first reference signal as a reference signal of ?? modulation; a quantizer receives an output signal of the integrator circuit, an output signal of the adder, and a second reference signal as a reference signal in cyclic A/D conversion to generate a result of quantization of the output signal of the integrator circuit and the output signal of the adder; and a controller is configured to switch between a ?? modulation mode and a cyclic mode.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: March 3, 2020
    Assignee: DENSO CORPORATION
    Inventor: Tomohiro Nezuka
  • Patent number: 10582412
    Abstract: A network platform manages the provisioning of a UE with a dominant identity profile and a recessive identity profile. The dominant profile is associated with a user's existing wireless data plan and the recessive profile corresponds to a data plan of a provider of device, or machine-to-machine, services to the UE. The UE uses the two profiles to transmit separate data contexts on separate respective bearers. When managing two separate bearers, the UE always uses the dominant profile first for managing a handoff to a stronger cell. The UE reports that the new cell that now serves the dominant context is the only cell that has enough strength to support the recessive context, even if other cells near the UE have signals strong enough. This necessarily causes the recessive context to always be handed off to the same cell to which the dominant context has already been handed off.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: March 3, 2020
    Assignee: M2MD TECHNOLOGIES, INC.
    Inventor: Charles M. Link, II
  • Patent number: 10574248
    Abstract: A SAR ADC includes a first capacitor array, a first comparator, a second capacitor array, a second comparator, an arbiter and a control circuit. The first capacitor array is arranged for receiving an input signal to generate a first signal. The first comparator is arranged for comparing the first signal with a first reference signal to generate a first comparison result. The second capacitor array is arranged for receiving the input signal to generate a second signal. The second comparator is arranged for comparing the second signal with a second reference signal to generate a second comparison result. The arbiter is arranged for generating an arbitration result according to the first comparison result and the second comparison result. The control circuit is arranged for generating an output signal according to the first comparison result, the second comparison result and the arbitration result.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: February 25, 2020
    Assignee: MEDIATEK INC.
    Inventor: Hsin-Wei Chen
  • Patent number: 10574254
    Abstract: The disclosure includes a mechanism for mitigating electrical current leakage in a Successive Approximation Register (SAR) Analog to Digital Converter (ADC) by using a Flash ADC in conjunction with the SAR ADC. A sequence controller in the SAR ADC uses the output of the Flash ADC to control a switch array. Depending on the output of the Flash ADC, the sequence controller can control the switch array to couple at least one capacitor in the capacitor network of the SAR ADC to a voltage that reduces charge leakage in the SAR ADC. The voltage may be a pre-defined positive or negative reference voltage.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: February 25, 2020
    Assignee: Avnera Corporation
    Inventors: Wai Lee, Jianping Wen, Garry N. Link
  • Patent number: 10554984
    Abstract: Systems and methods for improving computer technology related to the rendering and encoding of images are disclosed, preferably for use in a video-game environment. In certain embodiments, a codec is used to encode one or more reference images for a partial range of encoder settings and a renderer is used to generate one or more rendering quality-settings profiles, generate one or more reference images, calculate perceived qualities for each of the one or more reference images, re-render the one or more reference images for each of the one or more rendering quality-setting profiles, and calculate perceived qualities for each of the one or more re-rendered reference images. The renderer compares the perceived qualities of the reference images to the perceived qualities of the re-rendered images and matches them. Those matches result in an association of one or more encoder settings with their matching rendering quality-settings profiles into a look-up table.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: February 4, 2020
    Assignee: ZeniMax Media Inc.
    Inventor: Michael Kopietz
  • Patent number: 10547308
    Abstract: A sampling circuit comprises a switch circuit and a gate bootstrapping circuit. The switch circuit includes a switch input to receive an input voltage, a gate input, and a switch output. The gate bootstrapping circuit provides a boosted clock signal to the gate input of the switch circuit. The boosted voltage of the boosted clock signal tracks the input voltage by a voltage offset. The gate bootstrapping circuit includes a single boost capacitance coupled between a first circuit node and a second circuit node. A high supply voltage is applied to the first circuit node and the input voltage is applied the second circuit node to generate the boosted voltage on the single boost capacitance.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: January 28, 2020
    Assignee: Analog Devices, Inc.
    Inventor: Junhua Shen
  • Patent number: 10541698
    Abstract: Multiplying digital-to-analog converter (MDACs) are implemented in pipelined ADCs to generate an analog output being fed to a subsequent stage. A switched capacitor MDAC can be implemented by integrating a capacitor digital-to-analog converter (DAC) with charge pump gain circuitry. The capacitor DAC can implement the DAC functionality while the charge pump gain circuitry can implement subtraction and amplification. The resulting switched capacitor MDAC can leverage strengths of nanometer process technologies, i.e., very good switches and highly linear capacitors, to achieve practical pipelined ADCs. Moreover, the switched capacitor MDAC has many benefits over other approaches for implementing the MDAC.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: January 21, 2020
    Assignee: Analog Devices, Inc.
    Inventor: Ralph D. Moore
  • Patent number: 10530382
    Abstract: An SAR ADC and a conversion method, which include an SAR control logic circuit configured to control A/D conversion by: 1) sampling analog input signal for first time; 2) subjecting the sampled signal to conversions; 3) sampling analog input signal for another time; 4) subjecting the sampled signal in step 3) to conversion including: i) determining whether the lowest M bits of previous N-bit digital output signal are 1's or 0's, if so, looping back to step 2), otherwise, proceeding to step ii); ii) performing conversions on lowest M bits of new N-bit digital output signal, directly taking N-th to (M+1)-th bits of previous N-bit digital output signal as N-th to (M+1)-th bits of new N-bit digital output signal, and repeating steps 3) and 4) until the analog input signal is fully sampled and converted. Required cycles can be reduced resulting in higher conversion rate and lower power consumption.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: January 7, 2020
    Assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corporation
    Inventors: Weiran Kong, Bin Zhang
  • Patent number: 10524744
    Abstract: An apparatus for collecting data is provided. According to an example, the apparatus for collection data may include: n number of detector arrays, n number of DAS circuits and a back-end processor. Each of the DAS circuits may include an analog-to-digital converter and a front-end processor coupled with the analog-to-digital converter. Each of front-end processors is coupled with the back-end processor via an independent transmission line. For each of the detector arrays, the detector array may be configured to output analog signals based on detected scanning rays penetrating through a subject. The analog-to-digital converter may be configured to perform an analog-to-digital conversion on the analog signals to generate raw data. The front-end processor may be configured to logarithmically compress the raw data and transmit the logarithmically-compressed raw data to the back-end processor via the transmission line.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: January 7, 2020
    Assignee: Shenyang Neusoft Medical Systems Co., Ltd.
    Inventor: Xiaoqing Hu
  • Patent number: 10520590
    Abstract: An active receiver having a digital-pixel focal plane array (DFPA) ranges a target when observing return pulses from a pulsed laser beam synced with the receiver. The DFPA establishes a time when the pulsed laser beam contacts a target and the range can then be established because the speed at which the laser beam travels is known. Various basis functions may be implemented with the DFPA data to establish when the laser beam contacts the target. Some exemplary basis functions are binary basis functions, and other exemplary basis functions are Fourier basis functions.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: December 31, 2019
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Jeffrey L. Jew, Paul R. Moffitt, Leonard A. Pomeranz, Hermanus S. Pretorius
  • Patent number: 10511320
    Abstract: An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventor: Mei-Chen Chuang
  • Patent number: 10505560
    Abstract: An analog-to-digital converter with noise elimination is disclosed. The analog-to-digital converter converts a single-ended analog input into digital representation, and comprises an input buffer and an analog-to-digital conversion module. The input buffer outputs a positive differential signal and a negative differential signal based on the single-ended analog input. The analog-to-digital conversion module receives the positive differential signal and the negative differential signal to generate the digital representation. The input buffer further transmits a noise compensation signal to the analog-to-digital conversion module. The noise compensation signal contains noise information about noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: December 10, 2019
    Assignee: MEDIATEK INC.
    Inventor: Fong-Wen Lee
  • Patent number: 10498322
    Abstract: An output circuit for use with a comparator includes a first transistor having a control terminal coupled to receive an output signal from a first stage of the comparator. A second transistor is coupled between the first transistor and a reference voltage. The second transistor has a control terminal coupled to receive a first reset signal. The second transistor is coupled to precharge a first output node of the first transistor between the first and second transistors to the reference voltage prior to a comparison operation of the comparator. An output stage has an input node coupled to the first output node. The output stage is coupled to generate an output voltage of the output circuit at an output node of the output stage in response to the first output node.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: December 3, 2019
    Assignee: OmniVision Technologies, Inc.
    Inventor: Hiroaki Ebihara
  • Patent number: 10498994
    Abstract: Disclosed herein is a solid-state imaging element including a pixel unit configured to include a plurality of pixels arranged in a matrix and a pixel signal readout unit configured to include an analog-digital conversion unit that carries out analog-digital conversion of a pixel signal read out from the pixel unit. Each one of the pixels in the pixel unit includes a plurality of divided pixels arising from division into regions different from each other in optical sensitivity or a charge accumulation amount. The pixel signal readout unit reads out divided-pixel signals of the divided pixels in the pixel. The analog-digital conversion unit carries out analog-digital conversion of the divided-pixel signals that are read out and adds the divided-pixel signals to each other to obtain a pixel signal of one pixel.
    Type: Grant
    Filed: February 7, 2017
    Date of Patent: December 3, 2019
    Assignee: Sony Corporation
    Inventor: Hiroki Ui
  • Patent number: 10491236
    Abstract: An offset compensation circuit comprises an error signal generation block arranged for receiving an input phase and an output phase, and for generating an error signal indicative of an error between the input phase and the output phase. Means are provided for combining the error signal with an offset compensation signal, yielding an offset compensated signal. A loop filter is arranged for receiving the offset compensated signal and for outputting the output phase. An offset compensation block is arranged for receiving the output phase and for determining the offset compensation signal. The offset compensation signal comprises at least a contribution proportional to a periodic function of the output phase.
    Type: Grant
    Filed: February 15, 2019
    Date of Patent: November 26, 2019
    Assignee: MELEXIS TECHNOLOGIES SA
    Inventors: Johan Raman, Pieter Rombouts
  • Patent number: 10488520
    Abstract: A time-of-flight (TOF) sensor includes a set of optical converters; each optical converter is configured to convert a reflection of the optical pulse from an object in the scene into an analog signal indicative of a time-of-flight of the optical pulse to the object. To that end, the set of optical converters produces a set of analog signals. The TOF sensor also includes at least one modulator to uniquely modulate each analog signal from the set of analog signals to produce a set of modulated signals, a mixer to mix the modulated signals to produce a mixed signal, and an analog to digital converter to sample the mixed signal to produce a set of data samples indicative of the TOF to the scene.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: November 26, 2019
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Petros T Boufounos, Achuta Kadambi
  • Patent number: 10483993
    Abstract: A pipelined analog-to-digital converter (ADC) and a residue amplifier used in the ADC. An ADC includes a capacitive digital-to-analog converter (CDAC), a residue amplifier, and a switched capacitor circuit. The residue amplifier is coupled to the CDAC. The residue amplifier includes a first complementary transistor pair and a first tail current circuit. The first complementary transistor pair is coupled to a first output of the CDAC, and includes a high-side transistor and a low-side transistor. The first tail current circuit is coupled to the high side transistor. The switched capacitor circuit is coupled to inputs of the CDAC and to the first tail current circuit. The switched capacitor circuit is configured to generate a voltage to bias the first tail current circuit with compensation for common mode voltage at the inputs of the CDAC.
    Type: Grant
    Filed: December 28, 2018
    Date of Patent: November 19, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Nandan Srinivasa, Srinivas Bangalore Seshadri, Sabu Paul
  • Patent number: 10484003
    Abstract: An A/D converter includes an integrator having an operational amplifier, a first feedback capacitor, and a second feedback capacitor, a quantizer outputting a quantization result of an output signal of the operational amplifier, and a D/A converter having a D/A converter capacitor. The D/A converter capacitor has a first terminal connected to an input terminal of the operational amplifier and a second terminal connected to an output terminal of the operational amplifier. The D/A converter performs a subtraction operation by repeating subtraction of charges accumulated in the first and second feedback capacitors based on the quantization result, and performs a cyclic operation by sequentially repeating subtraction and amplification of the charges accumulated in one of the first and second feedback capacitors based on the quantization result.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: November 19, 2019
    Assignee: DENSO CORPORATION
    Inventor: Tomohiro Nezuka
  • Patent number: 10473493
    Abstract: An oscillator-based sensor interface circuit comprises at least two oscillators, at least one of which is arranged for receiving an electrical signal representative of an electrical quantity being a converted physical quantity, phase detection means arranged to compare output signals of the at least two oscillators and for outputting a digital phase detection output signal in accordance with the outcome of the comparing, a feedback element arranged for converting a representation of the digital phase detection output signal into a feedback signal used directly or indirectly to maintain a given relation between oscillator frequencies of the at least two oscillators, detection means for detecting a difference between the at least two oscillators; and at least one tuning element arranged for receiving the detected difference and for tuning at least one characteristic of the oscillator-based sensor interface circuit.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: November 12, 2019
    Assignee: Melexis Technologies NV
    Inventor: Johan Vergauwen
  • Patent number: 10464387
    Abstract: An active suspension system that interfaces a sprung mass and an unsprung mass is disclosed. The active suspension system includes a suspension comprising one or more actuators capable of exerting a force on the sprung mass to at least partially isolate motion of the sprung mass from motion of the unsprung mass. A user interface allows a user to indicate a desired degree of motion isolation.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: November 5, 2019
    Assignee: ClearMotion Acquisition I LLC
    Inventors: Brian Alexander Selden, James A. Parison
  • Patent number: 10469095
    Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: an analog input signal (410); an ADC core (414) configured to receive the analog input signal (410) and comprising: a digital to analog converter, DAC (430) located in a feedback path; and a SAR controller (418) configured to control an operation of the DAC (430), wherein the DAC (430) comprises a number of DAC cells, arranged to convert a digital code from the SAR controller (418) to an analog form; a digital signal reconstruction circuit (450) configured to convert the digital codes from the SAR controller (418) to a binary form; and an output coupled to the digital signal reconstruction circuit (450) and configured to provide a digital data output (460).
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: November 5, 2019
    Assignee: NXP B.V.
    Inventors: Yu Lin, Erwin Janssen, Vladislav Dyachenko