Analog To Digital Conversion Patents (Class 341/155)
  • Patent number: 11041884
    Abstract: A test and measurement instrument includes a coefficient storage facility coupled to a programmable filter. The coefficient storage facility is configured to store at least two pre-determined filter coefficient sets, and configured to pass a selected one of the at least two pre-determined filter coefficient sets to the filter based on a measurement derived using a compensation oscillator. The measurement may include clock delay and clock skew. In some examples the test and measurement instrument may additionally adjust clock delay and/or clock skew in addition to selecting appropriate filter coefficients.
    Type: Grant
    Filed: June 24, 2019
    Date of Patent: June 22, 2021
    Assignee: Tektronix, Inc.
    Inventors: Daniel G. Knierim, Barton T. Hickman
  • Patent number: 11043957
    Abstract: Signal quality is improved in a circuit for amplifying and sampling an analog signal. An input signal is input to one end of an input-side resistor. An operational amplifier amplifies the input signal, and outputs the input signal from an output terminal as an amplified signal. One end of a filter capacitor is connected to an input terminal of the operational amplifier. A predetermined frequency component of the input signal passes through the filter capacitor. A sampling capacitor imports the amplified signal during a predetermined sampling period, and holds the amplified signal during a predetermined hold period. A sampling switch connects the output terminal of the operational amplifier to one end of the sampling capacitor during the sampling period, and disconnects the output terminal of the operational amplifier from one end of the sampling capacitor during the hold period.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: June 22, 2021
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Eiichi Nakamoto
  • Patent number: 11044434
    Abstract: An image sensor having a plurality of pixels each of which comprises: a photoelectric converter that repeatedly generates charge corresponding to an amount of incident light; an A/D converter that A/D converts a voltage corresponding to the charge generated by the photoelectric converter into a digital signal by comparing the voltage with a reference voltage that changes with lapse of time; a capacitor that holds a threshold voltage based on the voltage corresponding to the charge; and a switching circuit that switches whether to perform A/D conversion on a voltage that corresponds to newly generated charge by the photoelectric converter based on a comparison result between the voltage that corresponds to the newly generated charge and the threshold voltage held in the capacitor.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 22, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hirokazu Kobayashi
  • Patent number: 11038515
    Abstract: Disclosed herein are some examples of algorithmic analog-to-digital converters (AADCs) that perform noise shaping. In particular, an AADC disclosed herein includes circuitry that can store residue(s) of one or more conversion cycles produced by the AADC and apply a value corresponding to the residue(s) to a subsequent conversion cycle. The AADC may perform a filtering procedure with the residue(s) to produce the value applied to the subsequent conversion. Applying the value to the subsequent conversion cycle can increase a signal-to-noise ratio of the signal that the AADC is converting in the subsequent conversion cycle.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: June 15, 2021
    Assignee: ANALOG DEVICES, INC.
    Inventor: Abhishek Bandyopadhyay
  • Patent number: 11038527
    Abstract: An electronic device for compressing sampled data comprises a memory element and a processing element. The memory element is configured to store sampled data points and sampled times. The processing element is in electronic communication with the memory element and is configured to receive a plurality of sampled data points, a slope for each sampled data point in succession, the slope being a value of a change between the sampled data point and its successive sampled data point, and store the sampled data point in the memory element when the slope changes in value from a previous sampled data point.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 15, 2021
    Assignee: Honeywell Federal Manufacturing & Technologies, LLC
    Inventors: Mitchell Hedges Morrow, Michael Aaron Tohlen, William Oliver Craig, John Savage
  • Patent number: 11031537
    Abstract: Apparatus and methods enable active compensation for unwanted discrepancies in the superconducting elements of a quantum processor. A qubit may include a primary compound Josephson junction (CJJ) structure, which may include at least a first secondary CJJ structure to enable compensation for Josephson junction asymmetry in the primary CJJ structure. A qubit may include a series LC-circuit coupled in parallel with a first CJJ structure to provide a tunable capacitance. A qubit control system may include means for tuning inductance of a qubit loop, for instance a tunable coupler inductively coupled to the qubit loop and controlled by a programming interface, or a CJJ structure coupled in series with the qubit loop and controlled by a programming interface.
    Type: Grant
    Filed: April 10, 2019
    Date of Patent: June 8, 2021
    Assignee: D-WAVE SYSTEMS INC.
    Inventors: Richard G. Harris, Andrew J. Berkley, Jan Johansson, Mark Johnson, Mohammad Amin, Paul I. Bunyk
  • Patent number: 11025264
    Abstract: An ultra-wideband distributed ADC can be cascaded to build high performance radio frequency (RF) analog electronics integrated with advanced digital complementary metal-oxide-semiconductor (CMOS) electronics on the same wafer. Advantages can include wide spectral coverage, high resolution, large dynamic range, and high information processing bandwidth. Part of an overall system includes a precise, programmable, real-time delay circuit that can achieve picosecond accuracy.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: June 1, 2021
    Assignee: Analog Devices, Inc.
    Inventors: Ed Balboni, Frank Murden, Peter Delos
  • Patent number: 11005491
    Abstract: The disclosed systems, structures, and methods are directed to a wireless receiver. The configurations presented herein employ a signal encoder configured to encode a plurality of received analog signals into a single encoded analog composite signal, in accordance with a variable leading bit orthogonal coding scheme, an analog-to-digital converter (ADC) configured to convert the single encoded analog composite signal into a single encoded digital composite signal containing constituent digital signals, a synchronization module configured to provide the variable leading bit orthogonal coding scheme to the signal encoder, and a signal decoder configured to decode the single encoded digital composite signal in accordance with the variable leading bit orthogonal coding scheme, to output a plurality of digital signals containing the desired information content of the received plurality of analog signals.
    Type: Grant
    Filed: May 27, 2020
    Date of Patent: May 11, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Lan Hu, Sai Mohan Kilambi
  • Patent number: 11005488
    Abstract: Apparatus, circuits and methods for calibrating time to digital converters (TDCs) are disclosed herein. In some embodiments, a circuit for calibrating a TDC is disclosed. The circuit includes a multi-bit delay circuit, a counter, and a register. The multi-bit delay circuit is configured for delaying a clock signal by a total delay time. The counter is configured for counting rising edges of the clock signal within the total delay time to generate a counted output. The register is configured for controlling the total delay time of the multi-bit delay circuit based on the counted output.
    Type: Grant
    Filed: August 26, 2020
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yu-Tso Lin
  • Patent number: 10992501
    Abstract: An illustrative integrated receiver circuit embodiment includes: a set of analog-to-digital converters that sample a receive signal in response to staggered clock signals to provide a parallel set of sampled receive signals; an equalizer that converts the parallel set of sampled receive signals into a parallel set of equalized signals; one or more quantizers that derives symbol decisions from the parallel set of equalized signals; a digital timing circuit that generates the staggered clock signals based on the parallel set of equalized signals; and a clock skew adjustment circuit that provides a controllable skew of at least one of said staggered clock signals relative to at least one other of the staggered clock signals. A monitor circuit is included to provide a reliability indicator for the symbol decisions, as is a controller that determines a dependence of the reliability indicator on the controllable skew.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: April 27, 2021
    Assignee: CREDO TECHNOLOGY GROUP LIMITED
    Inventors: Junqing Sun, Haoli Qian
  • Patent number: 10983324
    Abstract: Provided is a light detecting apparatus including: a phase locked loop portion that generates a sampling clock based on a synchronization signal output from a light source that emits pulsed laser light; an A/D convertor that performs sampling of signal light output from a sample as a result of radiating the laser light thereon in accordance with the sampling clock; and a received-data processing portion that accommodates, every time N items of the sampling data are continuously acquired, the N items of data in a single data sequence. The phase locked loop portion is provided with a clock generating portion that generates a clock that has a frequency that is N times a pulse frequency of the laser light and that is synchronized with a phase of the laser light, and a delay adjusting portion that generates the sampling clock by adjusting a delay amount of the generated clock.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: April 20, 2021
    Assignee: OLYMPUS CORPORATION
    Inventors: Hiroyuki Yabugaki, Ryusuke Tanaka
  • Patent number: 10985771
    Abstract: A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2M?1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors Cu(n/2)*, Cu(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR ADC.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: April 20, 2021
    Assignee: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA
    Inventors: Hua Fan, Chen Wang, Peng Lei, Dainan Zhang, Quanyuan Feng, Lang Feng, Xiaopeng Diao, Dagang Li, Kelin Zhang, Daqian Hu, Yuanjun Cen
  • Patent number: 10979062
    Abstract: This disclosure describes techniques to perform analog signal conditioning (including filtering and amplification) and analog-to-digital conversion (ADC) on a System-in-package (SIP) assembly technology. In particular, the disclosure combines a programmable gain amplifier (PGA), one or more filter circuits, and an ADC circuit onto the same SIP. These devices are coupled together on the SIP using high-accuracy and precise integrated-passive components. The SIP receives an analog signal, amplifies the analog signal with the PGA on the SIP, filters the amplified analog signal with the filter circuit(s) on the SIP, and then performs analog-to-digital conversion on the filtered amplified analog signal with the ADC circuit on the SIP. The SIP can be configured for various applications based on a variety of inputs and control mechanisms.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: April 13, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: John P. Healy, Michael Hennessy, Naiqian Ren, Patrick Martin McGuinness, Robert A. Bombara
  • Patent number: 10972121
    Abstract: An instrument configured to process signal data is disclosed. The instrument is operable to control and or change the sampling rate of the signal data from a first sample rate to a second sample rate different than the first sample rate.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: April 6, 2021
    Assignee: Viavi Solutions Inc.
    Inventor: Sean Hamlin
  • Patent number: 10965306
    Abstract: A successive approximation register analog-to-digital converter includes a comparator circuit, a capacitor group, an additional capacitor and a control circuit. The comparator circuit compares voltages at first and second input terminals thereof to generate a comparison result. The capacitor group and the additional capacitor are coupled to the first input terminal. The control circuit controls voltages of capacitors of the capacitor group according to the comparison result. In a first period, the control circuit provides a first voltage to the first input terminal and the additional capacitor, and provides an analog signal to the capacitors. In a second period, the control circuit stops providing the first voltage and controls a specific capacitor of the capacitor group to enter into a floating state. In a third period, the control circuit provides a second voltage to the additional capacitor. The second voltage is lower than the first voltage.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: March 30, 2021
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventors: Che-Hao Chiang, Szu-Wei Chang
  • Patent number: 10965305
    Abstract: Certain aspects are directed to a time-to-digital converter (TDC) that allows for a more accurate jitter measurement. The TDC generally includes a ring oscillator (RO) having a plurality of taps and configured to generate a plurality of RO signals at the plurality of taps, a counter having an input coupled to an oscillating node, and at least two sampling circuits, each having an input coupled to an output of the counter. In certain aspects, the at least two sampling circuits are configured to sample a count signal at the output of the counter based on at least two of the plurality of RO signals at the plurality of taps.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: March 30, 2021
    Assignee: QUALCOMM INCORPORATED
    Inventors: Ravindraraj Ramaraju, Elhossin Abdelmonem Elshafey, Masoud Zamani, Elham Zamanidoost
  • Patent number: 10931292
    Abstract: Described are apparatus and methods for successive approximation register (SAR) analog to digital converter (ADC) (SAR ADC) with factoring and background clock calibration. An apparatus includes a SAR ADC configured to, in response to receiving an enable flag based on detection of an acquisition clock with a first logic state sent by a controller, sample and convert a pair of differential input signals using a sampling clock to obtain a defined number of samples in an acquisition clock cycle and a factoring circuit configured to obtain the defined number of samples from the SAR ADC using a capturing clock based on the sampling clock, factor the defined number of samples, and send a factored samples ready flag to the controller.
    Type: Grant
    Filed: May 13, 2020
    Date of Patent: February 23, 2021
    Assignee: Ciena Corporation
    Inventors: Soheyl Ziabakhsh Shalmani, Hazem Beshara, Mohammad Honarparvar, Sadok Aouini, Christopher Kurowski, Naim Ben-Hamida
  • Patent number: 10903843
    Abstract: A successive approximation register analog-to-digital converter (SAR ADC) circuit comprises N weighted bit capacitors, wherein N is a positive integer greater than one; a sampling circuit configured to sample an input voltage onto the N weighted bit capacitors; and logic circuitry. The logic circuitry is configured to enable sampling of the input voltage onto the N weighted bit capacitors in a high-resolution mode; enable sampling of the input voltage onto N?M of the weighted bit capacitors in a low-resolution mode and sampling a common mode voltage onto the most significant M weighted bit capacitors, wherein M is a positive integer greater than zero and less than N; and initiate successive bit trials using the weighted bit capacitors to convert the sampled input voltage to a digital value.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 26, 2021
    Assignee: Analog Devices International Unlimited Company
    Inventors: Sandeep Monangi, Michael C. W. Coln, Archana Patil
  • Patent number: 10892914
    Abstract: For example, a wireless communication receiver may be configured to switch one or more RF components of the receiver between an on-state and an off-state based on at least one detection criterion for preamble detection of a frame preamble by a preamble detector of the receiver, switching the one or more RF components between the on-state and the off-state including switching the one or more RF components from the on-state to the off-state based on determination that the at least one detection criterion is not met, and switching the one or more RF components from the off-state to the on-state after an off-state period, wherein a duration of the off-state period is based at least on a preamble duration of the frame preamble; and to repeat switching the one or more RF components between the on-state and the off-state until the frame preamble is detected by the preamble detector.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: January 12, 2021
    Assignee: INTEL CORPORATION
    Inventors: Assaf Gurevitz, Oren Kaidar, Rafi Ben-Tal, Elad Meir, Hagay Barel
  • Patent number: 10886902
    Abstract: Superconducting circuits and methods for detecting a rising edge of an input signal are described. An example superconducting circuit includes an input terminal for receiving an input signal comprising both positive pulses and negative pulses. The superconducting circuit further includes a first stage, coupled to the input terminal and a first node, configured to suppress both any backward propagating negative pulses and any forward propagating negative pulses, and allow propagation of any forward propagating positive pulses. The superconducting circuit further includes a second stage, coupled to the first node, configured to store a forward propagating positive pulse and reflect a stored positive pulse back to the first node as a negative pulse such that in response to each rising edge of the input signal a return-to-zero signal comprising both a rising edge and a falling edge is provided as an output at the first node.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: January 5, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventor: Alexander L. Braun
  • Patent number: 10880646
    Abstract: A microphone assembly includes a transducer element and a processing circuit. The processing circuit includes an analog-to-digital converter (ADC) configured to receive, sample and quantize a microphone signal generated by the transducer element to generate a corresponding digital microphone signal. The processing circuit includes a feedback path including a digital loop filter configured to receive and filter the digital microphone signal to provide a first digital feedback signal and a digital-to-analog converter (DAC) configured to convert the first digital feedback signal into a corresponding analog feedback signal. The processing circuit additionally includes a summing node at the transducer output configured to combine the microphone signal and the analog feedback signal.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: December 29, 2020
    Assignee: Knowles Electronics, LLC
    Inventors: Mohammad Shajaan, Claus Erdmann Fürst, Per Flemming Høvesten, Kim Spetzler Berthelsen, Henrik Thomsen
  • Patent number: 10880128
    Abstract: A decision-feedback equalizer (DFE) samples an analog input signal against M references during the same symbol time to produce M speculative samples. Select logic in the DFE, then decodes N bits resolved previously for previous symbol times to select one of the M speculative samples as the present resolved bit. The present resolved bit is then stored as the most recent previously resolved bit in preparation for the next symbol time. The select logic can be can be programmable to accommodate process, environmental, and systematic variations.
    Type: Grant
    Filed: July 11, 2019
    Date of Patent: December 29, 2020
    Assignee: Rambus Inc.
    Inventors: Brian S. Leibowitz, Jaeha Kim
  • Patent number: 10873340
    Abstract: According to one aspect of the invention, a method for making relatively high resolution measurements using relatively low resolution devices includes the steps of: deriving a first anticipated measurement value; using the first anticipated measurement value as an initial feed-forward signal; comparing the initial feed forward signal to a received signal from a sensor, thereby generating a compared signal; scaling the compared signal to full scale of an analog-to-digital converter, thereby generating a scaled signal; delivering the scaled signal in binary form for computation; and iteratively performing the comparing step until the compared signal is below a predetermined threshold value.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: December 22, 2020
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventor: Ray Dixon
  • Patent number: 10868554
    Abstract: Techniques to reduce the on-time of a multi-stage ADC circuit by combining the settling time of a signal conditioning circuit, e.g., buffer circuit, and the setting time of a residue amplifier when cancelling the offset of the signal conditioning circuit. The techniques can allow the signal conditioning circuit and the residue amplifier to settle together.
    Type: Grant
    Filed: December 6, 2019
    Date of Patent: December 15, 2020
    Assignee: Analog Devices International Unlimited Company
    Inventors: George Pieter Reitsma, Raymond Thomas Perry
  • Patent number: 10868559
    Abstract: A readout circuit that includes an amplifier circuitry, an analog-to-digital converter, a feedback circuit and a control logic is introduced. The amplifier circuitry may receive and amplify a differential signal that is obtained according to an input signal and a feedback signal to generate an amplified signal. The analog-to-digital converter is configured to convert the amplified signal to generate a n-bit digital code, wherein n is a positive integer. The feedback circuit is configured to search and generate a m-bit digital code based on a value of the n-bit digital code and convert the m-bit digital code to generate the feedback signal, wherein m is a positive integer. The control logic is coupled to the analog-to-digital converter and the feedback circuit, and configured to control the analog-to-digital converter and the feedback circuit. A multi-bit digital output of the readout circuit is generated according to the n-bit digital code and the m-bit digital code.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Jie Huang, Jui-Cheng Huang
  • Patent number: 10862499
    Abstract: An A/D converter circuit that converts analog information to numerical data is provided with a pulse delay circuit and an output unit. A sampling period is set so that a relationship between the sampling period and a circulation period of a pulse signal passing through a ring delay circuit satisfies a relational expression Trdl×n<Ts ?Trdl×(n+1). In the relational expression, Ts is the sampling period, Trdl is the circulation period in which the pulse signal circulates through the pulse delay circuit, and “n” is an integer equal to or greater than 0.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: December 8, 2020
    Assignee: DENSO CORPORATION
    Inventor: Takamoto Watanabe
  • Patent number: 10862505
    Abstract: An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: December 8, 2020
    Assignee: NXP USA, Inc.
    Inventor: Claudio Gustavo Rey
  • Patent number: 10862498
    Abstract: The invention discloses a calibration circuit and a calibration method for an analog-to-digital converter (ADC). The calibration method of the ADC includes the following steps: (a) resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (b) changing a terminal voltage of at least one capacitor in the first capacitor group; (c) the ADC generating a first digital code; (d) after the first digital code is obtained, resetting the voltage at the first input of the comparator and the voltage at the second input of the comparator; (e) changing a terminal voltage of at least one capacitor in the third capacitor group; and (f) the ADC generating a second digital code. The first digital code and the second digital code are used to correct the output of the ADC.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: December 8, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yu-Chang Chen, Shih-Hsiung Huang, Jian-Ru Lin
  • Patent number: 10855301
    Abstract: A digital-to-analog converter (DAC) device includes a DAC circuitry and a calibration circuitry. The DAC circuitry includes first and second DAC circuits which generate first and second signals according to an input pattern. The input pattern includes at least one of first logic value and at least one of second logic value that have different numbers. The calibration circuitry performs a calibration operation according to first and second comparison results, to generate a control signal for controlling the second DAC circuit. The first comparison results are comparison results of the first and the second signals when the input pattern is a first pattern, the second comparison results are comparison results of the first and the second signals when the input pattern is a second pattern, and the first pattern is inverse to the second pattern.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: December 1, 2020
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventor: Xiao-Bo Zhou
  • Patent number: 10855346
    Abstract: Techniques are disclosed relating to a massive MIMO base station architecture. In some embodiments, a base station is configured to combine signals received by multiple antennas and, for at least a subset of processing elements included in the base station, each processing element is configured to operate on a different portion of the combined signals. In these embodiments, each portion includes signals from multiple antennas. In some embodiments, the portions are different time and/or frequency portions of the combined signals. In some embodiments, this distributed processing may allow the number of antennas of the base station to scale dramatically, provide dynamic re-configurability, facilitate real-time reciprocity-based precoding, etc.
    Type: Grant
    Filed: May 4, 2015
    Date of Patent: December 1, 2020
    Assignee: National Instruments Corporation
    Inventors: Ian C. Wong, Karl F. Nieman, Nikhil U. Kundargi
  • Patent number: 10845837
    Abstract: A semiconductor device includes a voltage generator generating a reference voltage, a first reference current generator receiving the reference voltage and generating a reference current, a non-volatile memory storing a calibration code, a first bias current generator mirroring the reference current to generate a first bias current, and a second bias current generator adjusting the reference current according to the calibration code of the non-volatile memory to generate a second bias current.
    Type: Grant
    Filed: February 11, 2019
    Date of Patent: November 24, 2020
    Inventors: Junhan Bae, Chang-Kyung Seong, Jongshin Shin
  • Patent number: 10847112
    Abstract: A VCOM generator circuit generates a VCOM signal for an electronic display. The VCOM circuit includes an operational amplifier having reduced supply rails. In an implementation, the VCOM circuit has at least three supply rails, AVDD, ground or GND, and VP or VN, or both. VP is less than AVDD and greater than VN. VN is higher than ground and below VP. The VCOM circuit with reduced voltage supply rails for VP and VN reduces power consumption of the VCOM op amps. By reducing power consumption, this also reduces the surface temperature of the integrated circuit.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: November 24, 2020
    Assignee: IML International
    Inventors: Alberto Giovanni Viviani, Dimitry Goder, JunGi Lee, ChinFa Kao, Chun Lu
  • Patent number: 10840934
    Abstract: Various embodiments of the present technology may provide methods and apparatus for a successive approximation register analog-to-digital converter (SAR ADC). The SAR ADC may provide a first digital calibration circuit configured to correct systemic mismatch and a second digital calibration circuit configured to correct random mismatch. Together, the first and second digital calibration circuits resolve missing codes in the SAR ADC output.
    Type: Grant
    Filed: January 30, 2020
    Date of Patent: November 17, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Rajashekar Benjaram, Maheedhar Suryadevara
  • Patent number: 10841525
    Abstract: Apparatuses and methods for data transmission in an image sensor are disclosed herein. An example data transmission circuit may include a plurality of transmission banks coupled in series with a first one of the plurality of transmission banks coupled to function logic, where each of the plurality of transmission banks are coupled to provide image data to a subsequent transmission bank in a direction toward the function logic in response to a clock signal, a plurality of delays coupled in series, wherein each of the plurality of delays is associated with and coupled to a respective transmission bank of the plurality of transmission banks, and wherein the clock signal is received by each of the plurality of transmission banks after being delayed by a respective number of delays of the plurality of delays in relation to the function logic.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: November 17, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chao-Fang Tsai, Chun-Hsiang Chang, Zejian Wang
  • Patent number: 10831159
    Abstract: An apparatus includes a time-to-digital converter (TDC). The TDC includes a fine TDC (F-TDC) to generate a first output signal in a first range in response to a first signal and a second signal, and a coarse TDC (C-TDC) to generate a second output signal in a second range in response to the first signal and a delayed version of the second signal.
    Type: Grant
    Filed: December 14, 2018
    Date of Patent: November 10, 2020
    Assignee: Silicon Laboratories Inc.
    Inventor: John M. Khoury
  • Patent number: 10832014
    Abstract: Analog multipliers circuits can provide signal processing asynchronously and clock free and with low power consumptions, which can be advantageous, including in emerging mobile, portable, and at edge or near sensor artificial intelligence (AI) and machine learning (ML) applications. As such, analog multipliers can process signals memory-free in AI and ML applications, which avoids the power consumption and latency delays attributed to memory read-write cycles in conventional AI and ML digital processors. Based on standard digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of multi-quadrant current-mode analog multiplier (iMULT) circuits that can be utilized in current-mode multiply-accumulate (iMAC) circuits and artificial neural network (ANN) end-applications that require high-volumes, low costs, medium precision, low power consumptions, and clock free asynchronous signal processing.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: November 10, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10834354
    Abstract: An imaging device includes: a plurality of pixels arranged to form rows and columns and each configured to output a signal in accordance with an incident light, a plurality of column signal processing units provided in association with the columns and each having an A/D conversion unit that performs A/D conversion on a signal output from the pixels arranged on a corresponding column, a plurality of memory units provided in association with the columns and each having a memory that holds digital data output from the column signal processing unit of a corresponding column, a transfer unit that sequentially outputs the digital data held in each of the plurality of memory units to a common output line, and a bit value inversion unit that inverts a value of a bit of one of first and second digital data sequentially output to the common output line.
    Type: Grant
    Filed: June 17, 2019
    Date of Patent: November 10, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Daisuke Kobayashi, Yoshikazu Yamazaki, Kazuo Yamazaki, Wataru Endo
  • Patent number: 10834353
    Abstract: An image sensor comprising: a generator that generates a plurality of reference signals having different slopes of potential change; a selector that selects one of the reference signals; and an analog/digital converter that converts an analog signal output from a pixel unit by first or second driving using the selected reference signal into a digital signal. In the first driving, a noise signal is converted into a plurality of first digital signals using the reference signals and a photoelectric conversion signal is converted into a second digital signal using one of the reference signals. In the second driving, the noise signal is converted into the first digital signal using a predetermined one of the reference signals and the photoelectric conversion signal is converted into the second digital signal using one of the reference signals. The first driving is performed intermittently.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: November 10, 2020
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kazuki Ohshitanai
  • Patent number: 10833696
    Abstract: There is provided a successive-approximation type AD converter and a pipeline type AD converter without delay due to sample hold. A successive-approximation type AD converter 1 includes: receiving circuits configured to output the analog input signal according to the received analog input signal; subtractors configured to calculate subtraction signals between the analog input signal in each of n successive conversions and comparison signals obtained by DA-converting the control values by DA converters; comparators configured to determine a high-low relationship between the voltages of the subtraction signals and the reference voltage; a control circuit configured to update the control values so that the comparison signals approach the analog input signal based on the comparison results; and an output register configured to output the digital output signal based on the comparison results of the comparators.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: November 10, 2020
    Assignee: Asahi Kasei Microdevices Corporation
    Inventor: Kazuo Koyama
  • Patent number: 10833692
    Abstract: Single-stage and multiple-stage current-mode Analog-to-Digital converters (iADC)s utilizing apparatuses, circuits, and methods are described in this disclosure. The disclosed iADCs can operate asynchronously and be free from the digital clock noise, which also lowers dynamic power consumption, and reduces circuitry overhead associated with free running clocks. For their pseudo-flash operations, the disclosed iADCs do not require their input current signals to be replicated which saves area, lowers power consumption, and improves accuracy. Moreover, the disclosed methods of multi-staging of iADCs increase their resolutions while keeping current consumption and die size (cost) low. The iADC's asynchronous topology facilitates decoupling analog-computations from digital-computations, which helps reduce glitch, and facilitates gradual degradation (instead of an abrupt drop) of iADC's accuracy with increased input current signal frequency. The iADCs can be arranged with minimal digital circuitry (i.e.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: November 10, 2020
    Inventor: Ali Tasdighi Far
  • Patent number: 10826521
    Abstract: A successive approximation register (SAR) analog to digital converter (ADC) and a method of detecting an offset of a comparator are introduced. The SAR ADC includes a switch circuit, a comparator and a calibration circuit. The switch circuit is configured to perform a swapping operation on a first intermediate analog signal and a second intermediate analog signal to generate a first swapped analog signal and a second swapped analog signal. The comparator is coupled to the switching circuit and is configured to compare the first intermediate analog signal and the second intermediate analog signal before the swapping operation to generate a least-significant-bit value. The comparator is further configured to compare the first swapped analog signal and the second swapped analog signal after the swapping operation to generate a calibration bit value. The calibration circuit is configured to determine whether the comparator has an offset according to the least-significant-bit value and the calibration bit value.
    Type: Grant
    Filed: August 21, 2019
    Date of Patent: November 3, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Po Huang, Liang-Ting Kuo, Yi-Shen Cheng, Chia-Chuan Lee, Soon-Jyh Chang
  • Patent number: 10826470
    Abstract: A ramp generator includes an integrator including a first stage having first and second inputs and first and second outputs, and a second stage including first and second transistors coupled between a power supply rail and ground. A node between the first and second transistors is coupled to the output of the integrator amplifier. A control terminal of the first transistor is coupled to the first output of the first stage, and a control terminal of the second transistor is coupled to the second output of the first stage. A first current flows from the output to ground during a ramp event in the ramp signal generated from the output. Trimming circuitry is coupled to the output of the integrator amplifier to provide a second current to the output of the integrator amplifier in response to trimming inputs. The second current substantially matches the first current.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: November 3, 2020
    Assignee: OmniVision Technologies, Inc.
    Inventors: Liang Zuo, Rui Wang, Hiroaki Ebihara, Nijun Jiang
  • Patent number: 10816652
    Abstract: In a sonar system using a large array multielement sonar detector, the raw phase and intensity data is reduced to less than three bits per channel per slice for each of the detectors in the multielement array before the raw data is transmitted to a beamformer for transforming the data to information about the spatial positions of objects reflecting the sonar signals.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: October 27, 2020
    Assignee: CodaOctopus Group
    Inventor: Martyn Sloss
  • Patent number: 10812741
    Abstract: A pulse generator of an image sensor includes a delay cell including a plurality of transistors arranged in series between a power voltage and a ground, a stabilization capacitor, and a stabilization switch. The power voltage is supplied to a first terminal of a first transistor disposed first among the plurality of transistors, and a gate terminal of the first transistor is connected to a first node. An input voltage is supplied to a gate terminal of an n-th transistor disposed last among the plurality of transistors, and a ground voltage is supplied to a first terminal of the n-th transistor. The stabilization switch is disposed between a reference voltage input terminal providing a reference voltage and the first node. The stabilization switch is turned on by an input bias control signal to supply the reference voltage to the first node.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: October 20, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Tae Kim, Kyung Min Kim, Yun Hwan Jung, Hee Sung Chae
  • Patent number: 10812096
    Abstract: A wireless communication device converts a signal component, which has one of distributed frequency bands in an analog RF signal and passes through one of a plurality of bandpass filters, into digital data with an AD converter that carries out undersampling. A sampling frequency of the AD converter is set so that frequencies which are integral multiples of a Nyquist frequency based on the sampling frequency do not fall within frequency bands of signal components which are of the RF signal and are to pass through the respective plurality of bandpass filters.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: October 20, 2020
    Assignee: Icom Incorporated
    Inventors: Tadamune Birei, Yuta Morishita
  • Patent number: 10804916
    Abstract: In one embodiment an analog-to-digital converter circuit has an input for receiving a first analog signal level and a second analog signal level, a ramp generator adapted to provide a ramp signal, a comparison unit coupled to the input and the ramp generator, a control unit coupled to the comparison unit the control unit having a counter, the control unit being prepared to enable the counter as a function of a comparison of the ramp signal with the first analog signal level and the second analog signal level, and an output for providing an output digital value as a function of a relationship between the first analog signal level and the second analog signal level. Therein the ramp signal has at least one linearly rising and at least one linearly falling portion and an adjustable shift at a reversal point between the rising and the falling portion of the ramp signal, the shift depending on the number of rising and falling portions of the ramp signal.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: October 13, 2020
    Assignee: ams AG
    Inventors: Adi Xhakoni, Koen Ruythooren
  • Patent number: 10805568
    Abstract: A ramp signal generation device may be provided to include a ramp signal generator including a plurality of local ramp signal generators, each local ramp signal generator structured to generate a local ramp signals having a local ramp range based on a control of an external control unit, an AC coupler coupled to the ramp signal generator to receive local ramp signals from the ramp signal generator, the AC couple structured to perform AC coupling on the received local ramp signals and generate AC-coupled ramp signals, and an integrator coupled to the AC coupler to receive the AC-coupled ramp signals and structured to integrate the AC-coupled ramp signals into a ramp signal having a full ramp range.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: October 13, 2020
    Assignee: SK hynix Inc.
    Inventor: Hyeon-June Kim
  • Patent number: 10797594
    Abstract: Power converter circuits, including DC-DC converter circuits, that conserve IC area by utilizing more area-efficient alternatives for measurement circuitry. Various embodiments include a power converter circuit including a charge pump having a plurality of stack-nodes VCXM and at least one multiplexor for coupling selected stack-nodes VCXM to a corresponding comparator circuit configured to output a signal indicative of a difference between a selected input to the multiplexor and a reference signal. The number of comparator circuits is less than (N?1)×M, where N is the conversion gain of the power converter circuit (i.e., the number of charge pump stages X plus one), and M is the number of parallel charge pump legs. Related methods include measuring voltages at stack-nodes VCXM in a charge pump, wherein the stack-nodes VCXM are selected by means of a multiplexor and an input to a comparator.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: October 6, 2020
    Assignee: pSemi Corporation
    Inventors: Brian Zanchi, Aichen Low
  • Patent number: 10798327
    Abstract: A photoelectric conversion apparatus includes a pulse shaping circuit that shapes an output from a diode of avalanche amplification type into a pulse, and a pulse conversion circuit that converts a pulse signal output from the pulse shaping circuit. The pulse conversion circuit converts a pulse signal having a first amplitude and output from the pulse shaping circuit into a pulse signal having a second amplitude smaller than the first amplitude.
    Type: Grant
    Filed: February 5, 2019
    Date of Patent: October 6, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Yukihiro Kuroda
  • Patent number: 10784878
    Abstract: According to an aspect, a tri-level digital to analog converter (DAC) comprises a first set of switches turned on to cause a first analog value with a first error as an output for a first digital value, a second set of switches turned on to cause a second analog value with a second error as the output for a second digital value, wherein, both the first set of switches and the second set of switches are turned on to cause a third analog value, proportional to the first error and the second error, as the output for a digital value equal to zero, and both the first set of switches and the second set of switches are turned off to cause a fourth analog value equal to zero as the output for a fourth digital value representing a reset state.
    Type: Grant
    Filed: December 21, 2019
    Date of Patent: September 22, 2020
    Inventors: Amrith Sukumaran, Gireesh Rajendran, Ashish Lachhwani