Abstract: Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.
Type:
Grant
Filed:
March 29, 2019
Date of Patent:
December 20, 2022
Assignee:
Cypress Semiconductor Corporation
Inventors:
Eashwar Thiagarajan, Andrew Page, Harold Kutz, Kendall Castor-Perry, Rajiv Singh, Erhan Hancioglu, Bert Sullam
Abstract: An input device has a circular arc resistive layer and a metal plate as a conductive layer that is faced to the circular arc resistive layer, and can detect a position operated by partial contact between them. The input device has an element unit where a linear insulating layer as a contact preventing unit for preventing both ends of the circular arc resistive layer from simultaneously coming into contact with the metal plate during operation is disposed on one end of the circular arc resistive layer.
Abstract: A method of determining a factorization permutation for a natural number can include storing a canonical prime factor vector within memory of a system and storing a first basis vector within the memory. The method can include deriving a first count sequence, including a plurality of counts, from the first basis vector, wherein each count of the first count sequence is a child of the first basis vector. For each count of the first count sequence, a second basis vector can be output that is a child of the count, wherein each count of the first count sequence and child second basis vector specifies a factorization permutation of the natural number.
Abstract: Methods and apparatus to export tuning data collected in a receiving device are disclosed. An example method of collecting audience measurement data comprises collecting tuning data within a receiving device, and modulating an LED associated with the receiving device to export the collected tuning data from the receiving device.
Abstract: A semiconductor device includes: a transmitting section; and a receiving section, wherein the transmitting section and the receiving section are connected to each other through a bus, the transmitting section includes an encoding section for encoding data including a plurality of bits to produce bit-position information which indicates a position of at least one bit selected from the plurality of bits included in the data, and an output section for outputting the bit-position information onto the bus, and the receiving section includes an input section for receiving the bit-position information from the bus, and a decoding section for decoding the bit-position information to produce the data.
Abstract: A programmable analog-to-digital converter (ADC) for use in a CMOS imaging system, the CMOS imaging system having an array of pixels, and the ADC configured to provide a enhanced conversion resolution for pixels providing a low analog voltage level and a relatively coarser conversion resolution for pixels providing a relatively higher analog voltage level.
Type:
Application
Filed:
February 8, 2001
Publication date:
June 6, 2002
Applicant:
HYUNDAI ELECTRONICS INDUSTRIES, LTD.
Inventors:
Kang-Jin Lee, Chan-Ki Kim, Jae-Won Eom, Woodward Yang
Abstract: A transmitter pulse circuit produces two-phase pulse trains containing a certain number of pulse edges corresponding to an integral number represented by binary parallel bits of a data value to be transferred. The transmitter responds to a coordinate data value derived from a digitizer. The receiver includes a counter for counting pulse edges contained in the two-phase pulse trains, and a retrieving circuit for retrieving intermittently the counted contents to determine the number of received pulse edges. The counting circuit and the retrieving circuit constitute together a bus mouse interface of a host computer in the receiver. The coordinate data can be transferred to the host computer through the bus mouse interface without using a general RS-232C interface, thereby efficiently improving the host computer multiple terminal processing capacity.