Abstract: A data transmission system which provides differential transmission of a multi-level interface corresponding to a binary interface formed by a plurality of binary input signals. The binary interface is encoded by an encoder into a corresponding multi-level differential interface formed by a plurality of multi-level signals, such correspondence being in accordance with a pre-selected code conversion table, and the respective multi-level signals are transmitted over respective transmission channels. Upon reception at a decoder, the signs of the differences between respective pairs of the multi-level signals are detected, and in accordance with such signs binary values are assigned to respective binary output signals of the decoder in accordance with the inverse of the code conversion table employed for encoding. Differential transmission achieves immunity from common mode noise, and multi-level encoding requires fewer channels than would be necessary for binary differential transmission.

Abstract: A signal having a non-uniform probability density is processed for transmission in pulse code modulated form. The signal is quantized using conventional methods and the quantized signal is then coded using a non-sequential coding scheme in which binary codewords for the quantization levels are chosen in accordance with the probability of the quantization levels and number of ON bits in the codeword. Quantization levels of higher probability are assigned codewords with fewer ON bits. An optical network includes a central station having a master clock source. The central station is connected to a remote station including a signal processor arranged to process a signal for return transmission to the central station using minimum power codeword assignment.

Abstract: A two-level multiplexed encoder/decoder based on a novel technique of code table compression is disclosed. By means of comparing various code conversion tables such as well-known tables for use in NRZ-MRM, NRZ-RLL conversion schemes, separate code word condition sets are obtained. In accordance with the code word condition sets thus obtained, a two-level multiplexed encode and decode logic can be easily constructed. The code word condition sets representing the compressed code relations are sensed in the first level and are used further to set up the operation of a connected network of a multiplexed logic circuit in the second level. The AM generation/check and precompensation circuit necessary for the encoder and decoder are incorporated as an integral part. This method is applicable when more than two code tables are needed to be integrated in a single encoder/decoder.

Abstract: A multi-stage integrated decoder device has a special function which facilitates the simultaneous activation of a plurality and as many as all of its outputs. When it is used as a bit line decoder it is thus possible to activate a plurality and as many as all of the bit lines (including any redundant bit lines) of a block of storage cells of a semiconductor memory.

Abstract: A B8ZS.B6ZS coding circuit commonly used for a B8ZS coding or a B6ZS coding, generating a B8ZS violation signal or a B6ZS violation signal at a same start timing, and formed by a smaller circuit. The B8ZS.

Abstract: An arithmetic processor cable of performing successive multiplication operations at high speeds is described in which the resultant product, internally represented as a carry-save or signed-digit expression, may be directly input in that form as the multiplier for the next successive multiplication operation. Additionally, a multiplier recoder circuit is provided which recodes the binary multiplier, in the form of a carry-save or signed-digit expression into a radix 4 signed-digit number, in order to further increase the operating speed.