Abstract: An efficient data-directed scrambler is provided for processing digital signals having an unequally-weighted code. The data-directed scrambler includes inputs for receiving unequally-weighted bits of an input signal, outputs for supplying N scrambled bits of an output signal, and two or more scrambler columns connected in series between the inputs and the outputs. One or more of the scrambler columns includes a swapper cell and a digital fanout. Least significant bits in the unequally-weighted code are input to a swapper cell, and higher order bits in the unequally-weighted code are input to respective digital fanouts. In the other embodiments, an efficient data-directed scrambler is provided for processing digital signals having an equally-weighted code.

Abstract: A system and a method of suppressing outstanding degradation of decoded audio quality due to a transmission error of audio coded data are provided without feedback information from a receiver, thereby reducing the increase of the number of necessary transmission bands and the arithmetic complexity on the receiving side. A code conversion and transmission apparatus 100 for inputting audio coded data includes first to N-th code conversion and transmission units 102 and 104 to 106 for converting audio data to N pieces of coded data, and transmitting the data at predetermined or adaptively variable time intervals to M transmission lines 130. The second to N-th audio code conversion and transmission units 104 to 106 codes a frame at a compression rate equal to or higher than the rate of input coded data.

Abstract: A communications channel includes a buffer that receives user data symbols including a plurality of M-bit symbols. A seed selector receives the plurality of M-bit symbols, selectively removes symbols from a seed set based on Hamming distances between at least two of the M-bit symbols, and selects a scrambling seed from remaining symbols in the seed set. A scrambling device that communicates with the seed selector and the data buffer generates scrambled user data based on the user data symbols and the scrambling seed. The communications channel is implemented in a data storage system. The seed selector ensures a minimum Hamming weight of 15 percent in the scrambled user data. The seed selector compares first and second user data symbols in the plurality of M-bit symbols.

Abstract: A method for encoding digital data includes the step of: encoding the digital data to a corresponding digital signal sequence by a digital signal encoder (110) according to an encoding rule, which can be transmitted through the single digital circuit (12). The digital signal sequence includes a first digital signal, two second digital signals, and one or more compounding digital signals, each of which includes a third digital signal and the first digital signal. Each digital signal sequence begins with one second digital signal, which is followed by one first digital signal and one or more compounding digital signals, and ends with one second digital signal. A related apparatus is also disclosed.

Abstract: A method and circuit to produce an optimal sampling phase for recovery of a digital signal is achieved. A digital signal is over-sampled by sampling on each phase of a multiple phase clock to generate a sample value per phase. The multiple phase clock may be generated by a DLL. A voted value is determined per phase comprising a majority value of a set of consecutive sample values. Transition phases are sensed. A transition phase is defined as two consecutive voted phases comprising different values. The transition phases are compared to a stored phase state to determine a signal shift direction. The signal shift direction is filtered to generate a state update signal. The stored phase state is updated based on the state update signal. The stored phase state corresponds to an optimal sampling phase for recovery of the digital signal.

Abstract: A variable length coding apparatus and a variable length coding method including a prepacking unit which processes two data items, each of which is formed with a code value and a code length and is received from a variable length code generator at each clock cycle, into one data item and outputs the processed data item to perform bitstream packing. With this structure, a variable length coding apparatus operating at a high speed without idling can be implemented.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: A broad aspect of the invention provides a method of providing mobility support for a mobile node's traffic. The method involves maintaining context information for the mobile node on each of a first plurality of network nodes carrying the traffic; and proactively transferring and maintaining at least a portion of the context information in a plurality of network nodes which are not carrying the traffic, but which are candidates for carrying the traffic due to mobility of the mobile node. The method typically further involves defining and maintaining a definition of the second plurality of network nodes. In one embodiment of the invention, this involves adding a particular network node to the second plurality when the particular network node becomes a candidate for carrying the traffic, removing a particular network node from the second plurality when the particular network node is no longer a candidate for carrying the traffic.

Abstract: A data converter (1) capable of reducing a size of the total implementation in a device is a processing apparatus that performs secret converting processing predetermined to input data with 64 bits, the data converter including a finite field polynomial cubing unit (10), data integrating units (11a) to (11d), (12) and (13), a first converter (14), a second converter (15), a data splitting unit (16), and a data integrating unit (17). The finite field polynomial cubing unit (10) performs cubing, on the 32 bits data, in the polynomial residue class ring with a value in the finite field GF (28) as a coefficient and respectively outputs data with 32 bits.

Abstract: The present invention relates to media data encoding devices. Embodiments of the present invention pertain to devices that receive media data, generate scalable media based on the media data, receive scalable attribute criteria, generate scalable profile data based, at least in part, on the scalable media and the scalable attribute criteria, and output the scalable profile data.

Abstract: A data stream generation apparatus and method for the JPEG etc. for efficiently performing processing for insertion of fill bits and a camera system using the same, wherein when not yet output data coupled at a data coupler reaches 32 bits, 32 bits of data are output from an MSB side of this not yet output data to an output unit and the remaining data is fed back to the data coupler, while when it does not reach 32 bits, the not yet output data is fed back to the data coupler; fill bits having a data length of a difference between a data length obtained by an addition of input data and the data length of a feedback data and the data length of a whole multiple of one byte are generated at a fill bit adder, added to the MSB side of a marker, and output to a data selection unit; and this marker or the variable length data is selected in accordance with a selection signal, coupled to an LSB side of the feedback data at the data coupler, and supplied to the output unit.

Abstract: A data extraction/insertion device in a digital signal processor and a method thereof are provided. The data extraction/insertion method is performed in a digital signal processor including a source register and a destination registr. In this digital signal processor, data is extracted from the source register and inserted into the destination register using a position value, which represents the reference position of data extraction, and an offset value, which represents the size of data to be extracted. Accordingly, a sequence of data packets, the size of which are given in neither byte nor word unit, are effectively extracted or inserted, thus saving the space of a memory.

Abstract: When data detected by an encoder is transmitted/received in predetermined cycles in a measuring device using a sampling control system for controlling a position or a speed at predetermined time intervals, positional data is divided so as to be output with deviation data output each time. The divided positional is reconstituted so as to transmit the positional data within a control cycle.

Abstract: A method of and an apparatus for modulating data to be resistant to channel distortion. A space extending encoder performs a first code transformation to extend a run length of digitized data to a predetermined length and outputs the space-extended data. A multiplexer multiplexes the space-extended data and data transformed by a predetermined second code transformation. A format converter converts the multiplexed data into a predetermined format which is suitable for writing to a recording medium. The apparatus and method enable recorded data to be resistant to channel distortion, enable the data to be recorded with increased recording density, and enable the data written to the recording medium to be reproduced with improved reliability.

Abstract: Data compression and reconstruction methods and apparatuses for a hard copy device are provided. The data compression method of compressing source image data, which is used for hard copying a bilevel screened image and stored in a memory in units of bytes, for a hard copy device, includes the steps of transposing bytes at each column to bytes at each row in the source image data; and entropy encoding sequential chains, which include a current chain to be compressed and a chain or chains succeeding the current chain, or the current chain depending on whether a chain having the same value as that of the current chain exists in a dictionary composed of previous chains compressed before, and determining the result of the entropy encoding as the result of the compression. Neighboring bytes at each row have neighboring memory addresses. The offset of neighboring bytes at each column corresponds to the row width of the source image data.

Abstract: The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register.

Abstract: The invention is a system and method for synchronizing the transmission of compressed headers in data packets between a transmitter and a receiver having a preferred wireless application which is an improvement of RFC2508. In a system having a transmitter transmitting a plurality of packets each containing a header to a receiver, a method of synchronizing the transmission of compressed headers between the transmitter and receiver in accordance with the invention includes transmitting a current packet from the transmitter to the receiver containing information that the transmitter is prepared to send subsequently transmitted packets in which the headers therein are to be compressed in comparison to the header contained in the current packet; and transmitting from the receiver to the transmitter an acknowledgment packet that the receiver has received the current packet.

Abstract: The present invention provides a processor including a bit-shift circuit for inputting pieces of data held sequentially in a main register and an auxiliary register, shifting the piece of data bit after bit in accordance with a pointer and a bit count and outputting the shifted data by execution of an unpacking instruction specifying the bit count; a mask circuit for masking data output by the bit-shift circuit in accordance with the pointer and the bit count in the execution of the unpacking instruction; and a pointer-updating circuit for updating the value of the pointer by the bit count in the execution of the unpacking instruction.

Abstract: A data compression method for executing encode commands for PackBits compression by a processor. The encode commands include a first command to obtain an encode processing state of the PackBits compression and control output of a control code (+1, −2 etc.) based on the encode processing state, a second command to control output of input data (A to F) based on the encode processing state, and a third command to control output of a control command upon completion of the PackBits compression. In this arrangement, the PackBits encode processing can be performed at a high speed by the processor.

Abstract: A system for compressed digital video bitstreams, in which an I-frame may precede a plurality of P-frames slices, wherein the system includes an encoder to encode the bits for each successive P-frame slice. The system also includes a decoder buffer, where the bits enter at a fixed rate and a decoder, which uses the extracted bits to decode each frame and display each frame. The delay is chosen at a fixed rate between 10 msec and 100 msec.

Abstract: An interface includes an encoder to receive a stream of input symbols and, in response, to output a corresponding stream of output symbols of substantially equal weight via multiple signal lines, which can improve noise/speed performance. The encoder outputs the stream of output symbols so that no output symbol is consecutively repeated. A repeat symbol is used to indicate that the current symbol is identical to the immediately preceding symbol. This encoding allows an interface receiving the stream of output symbols can extract a clock signal from the stream.

Abstract: A method and apparatus for encoding a block of bits as integers values. A bit may be parsed from the block of bits. If the bit has a first value, then a first integer value of a data array may be selected to encode the bit. The first integer value may have a predefined characteristic, e.g., be an odd value. Alternatively, if the bit has a second value, then a second integer value of the data array may be selected to encode the bit. The second integer value might not have the predefined characteristic, e.g., not be an odd value, and instead be an even value. A set of integer values resulting from the encoding of the block of bits may define a compressed data block. The compressed data block may then be subsequently decoded to recover the block of bits.

Abstract: The present invention provides a processor including a bit-shift circuit for inputting pieces of data held sequentially in a main register and an auxiliary register, shifting the piece of data bit after bit in accordance with a pointer and a bit count and outputting the shifted data by execution of an unpacking instruction specifying the bit count; a mask circuit for masking data output by the bit-shift circuit in accordance with the pointer and the bit count in the execution of the unpacking instruction; and a pointer-updating circuit for updating the value of the pointer by the bit count in the execution of the unpacking instruction.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: Systems and methods that encode and decode data in a manner that limits error propagation by parsing a data word of length n into a predetermined number of data blocks, individually encoding each data block into a single associated code block, and then combining each of the code blocks to form a resulting code word of length (n+1), resulting in a code rate of n/(n+1). By parsing and encoding the data word in this manner, errors that occur with respect to one or more bits of one code block will not be propagated throughout an entire data word during the decoding process.

Abstract: There are provided: an offset adding section 3 for converting signed digital data to unsigned digital data by adding an offset value to signed digital data to be compressed, a rounding section 5 for reducing the number of bits per word by performing a rounding operation of a lower-order bit on the unsigned digital data, a timing synthesizer 6 and a compressing section 7 for sampling the digital data undergoing a rounding operation at a time interval of a point where a differential value varies in polarity and for obtaining as compressed data a pair of a discrete amplitude data value on each sample point and a timing data value indicative of a time interval between sample points. When a signal is compressed and expanded on a time base, the operation can be performed on the time base without frequency conversion.

Abstract: To generate a data packing solution, there is a data structure to define data, and an encoder to encode a first update of data and a second update of data and to prepare for transmission the second update following the first update without regard to a boundary associated with a predefined number of bits. In one embodiment, the predefined number comprises a byte. There can also be a decoder to receive the first and second updates, to determine where the first update ends and the second update begins and to decode the updates. There can also be a transmitter to stream the first and second updates. In another embodiment, the first and second updates are associated with financial market data. In another embodiment, the data structure comprises an XML file.

Abstract: Embodiments of a variable length coding packing architecture are discussed. In this regard, an example method of packing selected portions of separate bit strings into a buffer is presented. The example method comprises using multiplexers (MUXes) to select the desired portions of the separate bit strings to be packed in the buffer, and using MUXes to order the bits of the selected portions for packing in particular buffer locations.

Abstract: Methods and systems for processing data are disclosed. An exemplary system for parsing and modifying data stored in an array of storage elements includes a parsing system configured to access the data stored in selected storage elements of the array of storage elements and output the data in one of a plurality of register formats and a write system configured to write data to selected storage elements of the array of storage elements, wherein the data is received in one of the plurality of register formats. The plurality of register formats includes a first set of register formats corresponding to a packed representation of the data and a second set of register formats corresponding to an unpacked representation of the data.

Abstract: A system and method for lossless data compression. A mathematical transform equivalent to the content value of the data, and taking fewer bits to represent, is found.

Abstract: An exemplary embodiment of the invention is a method for encoding data into a 48B/50B format for transmission over a serial link. A data stream that includes characters is received and segmented into a six-character block. The block of six characters is translated into a 50-bit byte frame in 48B/50B format. A 48-bit word is created from the block of six characters by encoding the characters contained in the block. The 48-bit word is scrambled and a 2-bit synchronization sequence is appended to the scrambled 48-bit word. The result is the 50-bit byte frame in 48B/50B format. An alternate embodiment of the present invention includes a method for decoding data from the 48B/50B format.

Abstract: An encoder-decoder for processing entropy encoded data. The encoder-decoder provides a bitstream buffer for receiving variable length code words that are extracted from fixed length data words received and stored in a register. Variable length words are loaded into the bitstream buffer until all bits are loaded with data, at which time data is read out of the bitstream register and it is cleared and ready for new data. During decoding, the bitstream buffer receives a fixed length data word that is made up of multiple variable length code words. These code words are individually read out and read into a fixed length register. The contents of the fixed length register are then read out for further processing by a connected system. A controller is provided for coordinating and controlling encoding and decoding operation.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: A robust IP/UDP/RTP header compression mechanism is provided to correctly reconstruct IP/UDP/RTP headers in the presence of packet losses and errors of unreliable networks. The header compression mechanism may include a compressor/de-compressor implemented for operation similarly to RFC 2508 but designed specifically to address robustness when employed in lossy and error-prone networks. The robust header compression scheme requires that, when a second-order difference of a field is non-zero, not only a particular RTP packet whose second-order difference is non-zero is sent with the new first-order difference, but also those following packets are also sent with the new first-order difference as long as: (a) a period pre-determined by factors such as channel characteristics (e.g., link round-trip time RTT/inter-packet separation); or (b) a positive confirmation is received by the compressor that the new first-order difference has been correctly received.

Abstract: A Huffman encoder and a method for Huffman encoding in which a data compression rate can be easily changed and a recording medium having a program for a Huffman encoding process recorded thereon. A quantizer quantizes DCT coefficients output by a DCT device to output quantized DCT coefficients. A comparator judges a quantized DCT coefficient to be an invalid coefficient when the absolute value of the DCT coefficient is equal to or smaller than a threshold and judges the quantized DCT coefficient to be a valid coefficient when the absolute value of the DCT coefficient is greater than the threshold. A run length counter counts the number of consecutive invalid coefficients to output run lengths and outputs valid coefficients. An encoder performs encoding based on the valid coefficients and the run lengths to output encoded data.

Abstract: Encoding tables are accorded with variable-length encoding rules using a variable constraint length. A DSV control bit is periodically inserted into a first input bit stream to generate a second input bit stream. Every m-bit piece of the second input bit stream is encoded into an n-bit output signal forming at least a portion of an output code word by referring to the encoding tables. Thereby, the second input bit stream is converted into a first output bit stream composed of output code words and observing RLL (d, k). A sync word is inserted into the first output bit stream for every frame to generate a second output bit stream. A frame-end output code word is terminated at a position before a next-frame sync word. DSV control of the second output bit stream is implemented in response to the inserted DSV control bits.

Abstract: The invention is a system and method for processing a compressed data stream. The compressed data stream has a first group of source segments and a second group of source segments. For the first group of source segments, it is not necessary to decompress the source segments during the processing, and only status thereof, like timestamps, are needed to be modified. Comparatively, for the second group of source segments, it is necessary to decompress the source segments for successive manipulation. A recompression is then processed on the manipulated data segments. Finally, the resulting first group and second group of segments are combined together to generate a processed compressed data stream. Because of unnecessary decompression and recompression are dispensed with, significant efficiency is obtained and less error propagation occurs during processing the compressed data stream.

Abstract: There are provided: an offset adding section 3 for converting signed digital data to unsigned digital data by adding an offset value to signed digital data to be compressed, a rounding section 5 for reducing the number of bits per word by performing a rounding operation of a lower-order bit on the unsigned digital data, a timing synthesizer 6 and a compressing section 7 for sampling the digital data undergoing a rounding operation at a time interval of a point where a differential value varies in polarity and for obtaining as compressed data a pair of a discrete amplitude data value on each sample point and a timing data value indicative of a time interval between sample points. When a signal is compressed and expanded on a time base, the operation can be performed on the time base without frequency conversion.

Abstract: A method and apparatus for eliminating the inefficient use of network bandwidth cause by numerous acknowledgment transmitted by the receiver to the transmitter by providing sparse feedback from the receiver to the transmitter indicating receipt of packets having headers to be used as reference headers. In the invention, upon receipt in the receiver of a packet having a reference header, a feedback is provided to the transmitter indicating receipt of the packet having the reference header. Thereafter, the receiver waits a predetermined period of time before providing another feedback in response to another packet having a reference header. The predetermined period of time allows time for the feedback to be received by the transmitter and for information from the transmitter indicating receipt of the feedback to be received by the receiver.

Abstract: The present invention pertains to a distance-enhancing coding method that can be applied to digital recording and digital communications. It improves the time-varying maximum transition run method used in a conventional distance-enhancing coding to avoid main error events ±(1,−1) from happening. Under the premise of maintaining a code gain of 1.8 dB, the code rate can be increased from ¾ to ⅘. The invention also provides a method of using an enumeration algorithm and an exhaustive method to search for block codes for distance-enhancing coding, which can find required codes by following specific steps.

Abstract: The present invention is directed to providing a method and apparatus for efficiently compressing and reconstructing a header of a real time communication packet. In a header compressor, a header field value is applied to a modulo X operator which can, for example, divide the header field value by a value X, and output the remainder. Optionally, a checksum may be appended to the remainder. The header field value may be scaled prior to being applied to the modulo X operator. The compressed header field which is output from the header compressor includes the remainder with or without the checksum appended. A header decompressor includes a field reconstructor which reconstructs the received compressed header field in response to the remainder value and range information. The range information represents a range of possible field values which can be reconstructed from the received remainder value.

Abstract: The present invention provides an arithmetic unit comprising an input register for storing externally input digital data as a P-bit digital data, an output register for storing a Q-bit digital data, and an output bit selecting means. The output bit selecting means is operable to receive the P-bit digital data which is output from the input register as a first input data, and the Q-bit digital data which is output from the output register as a second input data. The output big selecting means is further operable to select bits, values of which bits are to be output, among bits of the first input data and bits of the second input data, in accordance with a control data which is input from outside. The output bit selecting means is still further operable to output Q-bit digital data comprising the values of the selected bits to the output register.

Abstract: Embodiments of a variable length coding packing architecture are discussed.

Abstract: A method includes a data encoding scheme that has a run length limit of (1,6) and a 25% duty cycle. With error correction, the method achieves an effective run length limit of (2,9). The method can be used in conjunction with a packetized communication protocol to allow multiple controllers to communicate with multiple peripheral devices in a wireless data network. Peripheral devices include pointing devices, keyboards and game pads.

Abstract: A system and method for compressing and decompressing data in real time begins by taking a character string from an input string, generating a hash value of the character string which is utilized in a look up table to address a chained array or list of previously matching character strings. The array is updated if there is another.matching character string found when compressing the input string. A token generator writes a code to the output string indicating whether or not that there has been a match. The token generator generates an indication of the length of the character string not compressed, the one or more characters string not compressed, the length of a matching character string, and the number of characters processed since the last match. These values generated by the token generator are optimally represented based upon preselected criteria.

Abstract: The present invention is directed to a variable coding of the bit-planes for a particular source signal. This includes first partitioning or grouping the different bit-planes into embedded sub-signals and then coding each sub-signal. This technique enables an encoder according to the present invention to control and achieve a desired trade-off point between scalability and coding-efficiency. Therefore, in cases where bit or bit-plane level granularity is not required, coding efficiency can be improved by combining two or more bit-planes prior to coding. In addition, since the statistical nature of each bit-plane is different, the level of grouping used across the bit-planes can vary.

Abstract: An improved system and method for performing lossless data compression of a data string by parsing the data string and representing the parsed characters of the data string as irreducible grammar that is efficiently updatable. The system and method are each capable of parsing the data string into a least one variable of irreducible grammar, such that each variable represents a respective plurality of data characters of the data string, and formatting each variable of irreducible grammar as a linked list data structure having at least one pointer pointing to a linked list data structure representing another variable. The system and method are each further capable of updating the irreducible grammar based on at least one character to be parsed in the input string by changing at least one pointer of at least one of the linked list data structures to point to a linked list data structure different than that to which the at least one pointer pointed prior to updating.

Abstract: A plurality of data items are received in each frame period, and a digital signal processor (DSP) checks a flag corresponding to each data item in each frame period before the DSP applies processing to the received data. When the checked flag allows the corresponding data item to be processed, the process is performed. When the execution of the process is finished, the flag is reset. When all the flags are reset, the DSP enters a sleep state.

Abstract: A method of converting a stream of databits of a binary information signal into a stream of databits of a constrained binary channel signal, a device for encoding, a signal, a record carrier, a method for decoding, and a device for decoding. The signal is constructed by repetitively or alternately using channel codes C1 and C2. Since two channel words with opposite parities are available in the channel code C2 for each information word, and the same state is established, predetermined properties of the constrained binary channel signal can be influenced. Since the method further comprises the step of substituting, in dependence upon a value of a predetermined property of the binary channel signal, a channel word for a substitute channel word, wherein the substituted channel word and the substitute channel word establish the same state, predetermined properties of the constrained binary channel signal can be further influenced.

Abstract: The present invention describes a system and method for encoding a sequence of 64 bit digital data words into a sequence of 65 bit codewords having constraints of (d=0, G=11/I=10) for recording upon a magnetic medium within a magnetic recording channel are disclosed. The method for encoding a sequence of 64 bit digital data words into a sequence of codewords having 65 bits, comprising the steps of dividing each 64-bit digital data word into 8-bit bytes, encoding two 8-bit bytes to form a 17-bit word, forming five 11-bit intermediate blocks from the 8-bit bytes, encoding the five 11-bit intermediate blocks, and concatenating the five encoded 11-bit intermediate blocks and uncoded and unconstrained bits from the 64 bit digital data word to form a 65 bit codeword. A corresponding decoding method is also described. A byte shuffler may be used in the processing.