Abstract: A block of picture elements is DCT transformed and coded to produce a corresponding data block of variable length codewords having an average length. The data blocks are apportioned among fixed length transport blocks as needed to produce full transport blocks. The transport blocks include a direct (DC) component and alternating components at prescribed locations, as well as an address information flag indicating whether or not block data is longer or shorter than the average length, and an address pointer, to facilitate recovery and synchronization of apportioned data blocks at a decoder.

Abstract: The preferred embodiment includes a method and apparatus for generating a comma code. A data word having a value m is received. A binary storage apparatus receives the data value. A storage apparatus is coupled to the output of the address calculator. The storage apparatus includes a plurality of single bit storage elements that are arranged to provide an M bit output. Each single bit storage element is initialized to a first value. The address calculator calculates the appropriate single bit storage element to be selectively inverted.

Abstract: A variable length coder includes a buffer memory for temporarily storing data, to be coded, a coding table for producing a variable length code and a code length thereof in response to the data supplied from the buffer memory, a shifter for shifting the variable length code according to a shift control signal, registers for storing shifted data supplied from the shifter through a gate, and a multiplexer for selectively feeding high-order or low-order bits of the data stored in the registers to the gate, and a register for accumulating code lengths from the coding table. The buffer memory, the coding table, the shifter, and the multiplexer are controlled by output data from the register.

Abstract: This invention encodes information (such as the field values of a database record, or the words of a text document) so that the original information may be efficiently searched by a computer. An information object is encoded into a small "signature" or codeword using a method. A base or "leaf" signature S1 34 is computed by a known technique such as hashing. The logical intersection (AND) of each possible combination of pairs of bits of the base signature is computed, and the result is stored as one bit of a longer combinatorial signature CS1 42. The bit-wise logical union (bit-OR) of the combinatorial signatures of a group of records produces a second-level combinatorial signature CS2 52 representing particular field values present among those records. Higher-level combinatorial signatures CS3 60, CS4, etc. are computed similarly.

Abstract: The data unpacker receives packed parallel input data words having a fixed width of m bits, and it outputs parallel data words having a variable width of n bits. An input register stores the received words and applies them to a bit shifter. The bit shifter shifts the received data by a number of bit positions indicated by a shift control signal, and the shifted data is output therefrom as a parallel output word having n valid bits. The number n for each output word is received by the unpacker as a binary number. When n.gtoreq.m, a most significant (MSB) bit portion of that number is applied as first MSB control signal. The least significant bit (LSB) portion of n is applied to an adder which adds subsequently received LSB portions to provide a running sum. When the running sum is equal to or greater than m, the adder provides a second MSB control signal, corresponding to the most significant bit of the running sum.

Abstract: A plurality of parallel compression/decompression units can be tied together to sequentially process equal amounts or sets of data from a stream of data. Hardware in the upper level of each device acts as a demultiplexer to control the acceptance of only its set of data to transfer control to permit the next device to accept data and also stores its set for compaction. Essentially identical hardware in the lower half of each device acts as a multiplexer to control the acceptance of its compacted set of data to store the compacted set and to place the compacted set into the original sequence of the stream of data for storage on the tape media. A data integrity system provides a Cyclic Redundancy Check on the data before and after each section of the process. The compacted data is decompacted immediately after compaction as a read back check to verify that the compacted data can be reconstructed when retrieved.

Abstract: A data conversion method and an apparatus for the same which converts undefined-length image signal coded by a MH or MR method for facsimile equipment, etc. into fixed-length data. Coded undefined-length image data is inputted, and, in accordance with a bit length contained in the image data and with the number of the effective bits in the last byte, bits to be outputted from a barrel shifter are shifted. Control is performed to byte pack the bits of the last byte and the shifted bits outputted from the barrel shifter, and coded data is converted into data in byte units, thereby enabling high-speed byte packing.

Abstract: A waveform encoding and decoding apparatus is disclosed which comprises a memory, a coding device, a packing unit, and a storage device. The coding device encodes an analog waveform into digital coded data having digital coded data words each having a predetermined length. The packing device "packs" groups of more than one of the coded data words into packed data words each having a predetermined length. The storage device stores the packed data words into respective segments located in the memory. The segments which are located in the memory each have a bit length equal to the predetermined length of the packed data words. A data transfer device may also be provided for transferring and rearranging data between segments located in the memory.

Abstract: A data repacker utilizing a multiplexer, one intermediate register, two shifters, and a control for these circuits. The multiplexer output is connected to the intermediate register, which has a storage length greater than the size of data words to be repacked. The first shifter receives the output of the register, and its output can be concatenated with an input data word to form one input to the multiplexer. The output of the register is provided as another input to the multiplexer. The second shifter also receives the output of the multiplexer, and has an output which is the repacker output. Information representing the number of bits in and the number of bits out is used to determine the most and least significant bits of the intermediate data which will be stored in the intermediate register, and to control the shifters.

Abstract: A data packing circuit, used in a variable length coder, for receiving code words including variable length codes and code length information of the variable length codes, and packing the variable length codes with no gaps into successive units of bits having predetermined length. The code word is shifted in a first direction by a number of bits equal to a shift number, and in parallel, the code word is shifted in a second direction opposite to the first direction by a number of bits equal to the difference between the predetermined length and the shift number, and zero is filled in each vacant bit which is generated by the above shift operations. The shift number is determined by accumulation of the code lengths by modulo-n addition, n being equal to the predetermined number, and a carry addition of the code lengths whether or not a carry occurs over the above predetermined length in the accumulated value.

Abstract: An improved method of generating a compressed representation of a source data string, each symbol of which is taken from a finite set of m+1 symbols, a.sub.o to a.sub.m. The method is based on an arithmetic coding procedure wherein the source data string is recursively generated as successive subintervals within a predetermined interval. The width of each subinterval is theoretically equal to the width of the previous subinterval multiplied by the probability of the current symbol. The improvement derives from approximating the width of the previous subinterval so that the approximation can be achieved by a single SHIFT and ADD operation using a suitable shift register.

Abstract: A data compression/decompression system employs two stages of data compression. Information and/or character data is first formatted into M-bit width digital data characteristics for input to the first stage of the data compression system which comprises an expanding run length encoder having N-bit width output character where N>M and the number of M-bit width characters is greater than the number of N-bit width characters. The output of the expanding run length encoder is applied directly to a compatible adaptive string matching second stage data compression encoder of the type which is not degraded or affected by the input.When the input data stream to the two stage system is not of a known format or provided with leader or header bit character width information, a bit analyzer and a chopper are provided in a data stream to prepare the data stream in a bit character width format which matches the input of the expanding run length encoder.

Abstract: The data packer receives n-bit wide parallel data words, and it outputs m-bit wide packed parallel data words, where n is a variable and may change during the operation, and m is a fixed integer. The input data words are applied to a bit shifter and therefrom to a data output circuit where they are stored until the necessary m bits are obtained. In the preferred embodiment a control circuit which comprises an adder, receives information indicating the number of valid data bits in each input word, and it provides a running sum of the number of received valid data bits. When the number of bits in an input word is equal to or greater than m, the control circuit provides a first control signal which occurs simultaneously with an m-bit wide packed parallel output word provided by the output circuit. Any number of input bits which is less than m is added to a remainder of a previous sum which is also less than m.

Abstract: In an encoding system responsive to a sequence of coefficient signals which results from a predetermined linear transform and which is divided into a sequence of blocks, anterior processing is carried out prior to quantization about the coefficient signals in each block to determine a significant area of the coefficient signals by comparing each level of the coefficient signals with a threshold level. Only the coefficient signals within the significant area are judged to be valid and produced as a sequence of significant coefficient signals from a classifying circuit (20) to be quantized by a quantizer (15) into a sequence of quantized signals. The quantized signal sequence is subjected to posterior processing to produce a sequence of encoded signals. The significant area may be decided by the use of a selected one of zone detection, zigzag scanning, and adaptive scanning.

Abstract: A data compression/decompression apparatus employs common circuitry and a single string table for compression and decompression. A throttle control is provided to prevent data under-runs and an optimizing start-up control delays the start-up of the recording device until the compression apparatus has compressed sufficient data to effeciently reduce throttling and loss of compression when the output device is started. The decompression apparatus may operate to decompress compressed data when the compressed data is read in either the same direction as it was recorded, or read in the direction reverse to that in which it was recorded. A further feature is the provision of a counter which is incremented by one after a predetermined number of string codes have been written into the string table. The output of the counter is stored in the string table with each string code and prefix code.

Abstract: An analog communication system includes a transmitter and at least one remote receiver for receiving an incoming signal carrying an analog component from a suitable transmitter. The transmitter and receiver are provided with circuitry for transmitting, receiving and recording and for playback of the analog componant of the transmitted signal at different rates. The system is adapted to transmit along messages at a high rate to conserve transmission time and to record and playback the message at a slower audible rate. The system circuitry includes a decoder which may be programmed to recognize an address code specific to a particular receiver or group of receivers or may be activated simply by the incoming signal without an address code, to emit the enable signal. The decoder includes rate memory for storing record and playback rates in memory sectors corresponding to the memory sector of RAM in which the message is stored.