Abstract: When a combination between a plurality of FIFO memories and a variable length coding table is used, a load generated by an increase in number of FIFO memories serving as output destinations of a codeword length output from the variable length coding table when the codeword length is output is reduced.

Abstract: The present invention provides for a method, system, and computer program for the application of data deduplication according to a policy-based strategy of tiered data. The method operates by defining a plurality of data storage policies for data in a deduplication system, policies which may be arranged in tiers. Data objects are classified according to a selected data storage policy and are split into data chunks. If the selected data storage policy for the data object does not allow deduplication, the data chunks are stored in a deduplication pool. If the selected data storage policy for the data object allows deduplication, deduplication is performed. The data storage policy may specify a maximum number of references to data chunks, facilitating storage of new copies of the data chunks when the maximum number of references is met.

Abstract: Several code detectors in parallel simultaneously examine varying overlapping segments of a data stream containing variable length codes, referred to as a data window. The data window segments directly address memory structures within each of the code detectors without any previous logic stages. Each code detector is responsible for a range of code lengths, and ignores data window bits that are not relevant to its code length range. Each code detector outputs a possible result to a layer of logic that selects the possible result of the single code detector which contains result data corresponding to a variable length code in the data window.

Abstract: One embodiment of the invention is directed to a printer that is configured to interleave color plane data. The interleaved data is compressed, thereby forming compressed data having runs, seedrow copies and literals. In the compression process, commands are buffered to enable independent and simultaneous operation of a run module, a seedrow copy module and a literal module used in forming the compressed data.

Abstract: The present invention provides a clock circuit to produce a Reference Clock Signal used to latch data between first bit stream(s) and second bit stream(s), wherein the number and bit rate of the first bit stream(s) and the second bit stream(s) differ. The VCO generates one of a number of inputs to a PLL within the clock circuit. At a minimum, these inputs include a first bit stream data clock. Additionally, these inputs may further include a Loop Timing Clock Signal, an External Reference Clock Signal, and/or a Reverse Clock Signal for the PLL. The input provided by the VCO make up a VCO Output Signal wherein a filtering circuit that circuit includes a capacitor and a resistor reduces noise contained within the VCO Output Signal.

Abstract: A data encoder. The novel encoder includes a first circuit for generating a fundamental sequence coded data stream from an incoming input data stream, a second circuit for generating a k-split data stream from the incoming data stream, and a third circuit for combining the fundamental sequence coded data stream and k-split data stream to form a final encoded output. The first circuit includes a circuit for converting the incoming input data stream into a novel intermediate format comprising a set bit word and a zero word count, and a zero-word expander for converting the intermediate format to the fundamental sequence coded data stream. The first circuit may also include a register adapted to store the intermediate format to provide rate buffering.

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract: The invention relates to a method for the compression of data comprising values to be coded, in particular grey values or prediction errors using a run-length coding. A bit sequence of a bit plane which represents at least one item of partial information of at least one value to be coded is thereby coded coherently. This method is particularly used in connection with medical image data.

Abstract: A debinarizer and a hardware-based method for debinarizing a binary bit stream into symbols comprising predefined binary sequences are disclosed in which predefined binary sequences and their corresponding symbols are represented as tree structures. A binary sequence is debinarized by traversing one of the tree structures to determine a corresponding symbol. Similar tree structures may be combined to form a single tree structure. The tree structures may be implemented as a finite state machine.

Abstract: There is offered a Gray code counter with which a delay time of a critical path is reduced and a fast operation is made possible. A first Gray code bit Q0 is obtained by outputting an output signal Q0o of an RDFF 2 through an RDFF 31 to synchronize with a clock CLK. A second Gray code bit Q1 is obtained by outputting an output signal Q1o of an RDFF 2 through an RDFF 32 to synchronize with the clock CLK. A third Gray code bit Q2 is obtained by delaying an output signal Q2o of an RDFF 4 with a selection circuit 21 and outputting it through an RDFF 33 to synchronize with the clock CLK. A fourth Gray code bit Q3 is obtained by delaying an output signal Q3o of an RDFF 5 with an AND circuit 11 and a selection circuit 22 and outputting it through an RDFF 34 to synchronize with the clock CLK. Higher bits of the Gray code are similarly generated.

Abstract: A system and a method of suppressing outstanding degradation of decoded audio quality due to a transmission error of audio coded data are provided without feedback information from a receiver, thereby reducing the increase of the number of necessary transmission bands and the arithmetic complexity on the receiving side. A code conversion and transmission apparatus 100 for inputting audio coded data includes first to N-th code conversion and transmission units 102 and 104 to 106 for converting audio data to N pieces of coded data, and transmitting the data at predetermined or adaptively variable time intervals to M transmission lines 130. The second to N-th audio code conversion and transmission units 104 to 106 codes a frame at a compression rate equal to or higher than the rate of input coded data.

Abstract: An apparatus and method for lossless run-length data encoding is disclosed. In the first stage of the method, an input data sequence is transformed without increasing its volume in order to obtain long sequences of identical digits. In the second stage, every such sequence is replaced with a unique shorter sequence. The compressed data is decoded performing corresponding inverse operations. The method is very efficient for compression of some classes of digital images with long sequences of the same number, such as graphics, texts, signatures, and fingerprints.

Abstract: Techniques employable to compress and decompress images are presented herein.

Abstract: This data encoding apparatus includes: a predictor for calculating a prediction value of target data; a subtractor for calculating the difference between the target data and the prediction value as a prediction error value; an absolute value calculator for calculating the absolute value of the prediction error value; a flatness detector for detecting the number of the absolute prediction error values continuously equal to or lower than a predetermined threshold for some thresholds, and setting a code length candidate for each threshold by comparing the detected number with a predetermined run length; a k parameter determinator for determining the code length of a fixed length code part on the basis of the code length candidate of each threshold; and a Golomb-Rice encoder for encoding the absolute prediction error value in accordance with the determined code length by dividing it into a variable length and the fixed length code parts.

Abstract: A method of selectively run length encoding data may include removing a trigger value from one or more data elements if the trigger value is present in the one or more data elements and calculating a run length of the one or more data elements. The method may also include encoding the one or more data elements as a command pair when the run length is greater than two. The command pair may include the trigger value. The one or more data elements may be output without encoding the one or more data elements when the run length is not greater than two.

Abstract: To provide an image coding apparatus that can generate a code that can be decoded by a general decoding apparatus while attaining a high coding speed. As a result of processing in a plurality of prediction units 21, a control unit 11 generates a predicted pixel value for a pixel of interest based on a pixel value of a predicting pixel located at a distance from the pixel of interest, the distance being predetermined for each pixel value prediction unit 21, counts, as a run-length for each pixel value prediction unit 21, the number of times that the pixel value of the pixel of interest successively correspond with the predicted pixel value, selects any of pixel value prediction units related to a run-length of one pixel or more, and outputs a code by referring to a predetermined code table with respect to a distance between the pixel of interest and the predicting pixel for the selected pixel value prediction unit 21 and the run-length thereof.

Abstract: A data coding system that compresses data and enables data, e.g., prefix addresses, to be represented with significantly fewer memory cells when compared to conventional coding systems.

Abstract: An improved method is provided for identifying a repeated codeword in an incoming bit stream. The method includes: receiving an incoming bit stream having an expected codeword repeated a number of times; determining whether a group of incoming data bits correlates to the expected codeword, where each of the incoming data bits in the group need not match the corresponding data bit of the expected codeword; and determining whether the expected code word is repeated over a sequence of incoming data bits.

Abstract: Passing input strings through an application programming interface between functions that take null byte terminated strings as arguments, where at least some of said input strings contain null bytes internally. This is accomplished by storing the positions of the null bytes relative to the start of the block and storing the non-null bytes in their relative order to prevent said internal null strings from being treated as terminal null strings.

Abstract: A variable length decoder comprises: a first storage unit that stores encoded data; a variable length decoding unit; a second storage unit that stores coefficient data; a reverse quantizing unit; and a reverse DCT unit. The variable length decoding unit includes a control unit, a decoding unit, and an address generating unit. The second storage unit includes an initializing mechanism and is initialized all at once by the control unit in advance of decoding in a macro block unit. Only non-zero quantized data decoded by the decoding unit is stored in an address of the second storage unit generated by the address generating unit. The reverse quantizing unit reads and performs reverse quantization of the quantized data from the second storage unit, the reverse DCT unit performs reverse DCT, and then decoded data is acquired.

Abstract: A method repacks variable width trace data into a different packet length previous to being stored into memory. In order to conserve bandwidth, the trace data may also be compressed during transmission by eliminating the transmission of packets that have the same value.

Abstract: An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

Abstract: Systems and methods for converting a digital input data stream from a first sample rate to a second, fixed sample rate using a combination of hardware and software components. In one embodiment, a system includes a rate estimator configured to estimate the sample rate of an input data stream, a phase selection unit configured to select a phase for interpolation of a set of polyphase filter coefficients based on the estimated sample rate, a coefficient interpolator configured to interpolate the filter coefficients based on the selected phase, and a convolution unit configured to convolve the interpolated filter coefficients with samples of the input data stream to produce samples of a re-sampled output data stream. One or more hardware or software components are shared between multiple channels that can process data streams having independently variable sample rates.

Abstract: In order to decrease a required memory capacity of a line memory and to efficiently compress an image by coding, even when character information is contained in a high-resolution image, each time the block of an image that is equally divided into M (M: an arbitrary integer greater than 1) blocks in the horizontal direction is updated, difference data between color code data at corresponding pixel positions in the horizontal line and the adjacent immediately-preceding horizontal line with respect to each horizontal line within the block is detected by a line memory and an exclusive-OR circuit.

Abstract: A method and system of lossless compression of integer data using a novel backward-adaptive technique. The adaptive Run-Length and Golomb/Rice (RLGR) encoder and decoder (codec) and method switches between a Golomb/Rice (G/R) encoder mode only and using the G/R encoder combined with a Run-Length encoder. The backward-adaptive technique includes novel adaptation rules that adjust the encoder parameters after each encoded symbol. An encoder mode parameter and a G/R parameter are adapted. The encoding mode parameter controls whether the adaptive RLGR encoder and method uses Run-Length encoding and, if so, it is used. The G/R parameter is used in both modes to encode every input value (in the G/R only mode) or to encode the number or value after an incomplete run of zeros (in the RLGR mode). The adaptive RLGR codec and method also includes a decoder that can be precisely implemented based on the inverse of the encoder rules.

Abstract: A compressor can compress an image by reducing the amount of data while preserving the information. Some compressors use run length coding wherein image data is converted into a series of run length code words. The efficiency of run length coding can be increased with the introduction of differential run length code words. The differential run length code words can augment the original set of run length codes. Differential run length codes vary from current run length codes by encoding runs of differences.

Abstract: A data compression architecture includes a shift register with multiple shift register elements. A data input receives input data characters, and applies each received input data character to the shift register, such that the received input data character is stored in each shift register element of said shift register in turn. Logic circuitry is associated with each shift register element of the shift register, for detecting a match when the comparison circuitry determines that a sequence of two or more received input data characters is equal to a sequence stored in the shift register. A flush input receives a data flush input signal, and applies a received data flush input signal to the logic circuitry associated with each shift register element of the shift register, such that no match is detected by said logic circuitry when the data flush input signal is received.

Abstract: An image coding apparatus provides a run-length encoding unit RLE1 that subjects quantized coefficients which are obtained by quantizing frequency components of an image signal to a variable length coding process by using a run value Run that indicates the number of successive zero coefficients and a level value Lev that indicates a value of a non-zero coefficient following the zero coefficients. The run-length encoding unit RLE1 includes a reordering unit Lreodr for reordering level values Lev; a variable length coder LVLC for coding reordered level values ROLev by using a code table that is selected according to the value of a quantization parameter QP; a reordering unit Rreodr for reordering run values Run from high frequency component of the quantized coefficients to low frequency component; and a variable length coder RVLC for coding reordered run values RORun by using a code table that is selected according to the number of already-processed run values.

Abstract: A variable length coding apparatus and a variable length coding method including a prepacking unit which processes two data items, each of which is formed with a code value and a code length and is received from a variable length code generator at each clock cycle, into one data item and outputs the processed data item to perform bitstream packing. With this structure, a variable length coding apparatus operating at a high speed without idling can be implemented.

Abstract: Methods and apparatus are provided for programmable codeword encoding and decoding. Data blocks are represented as a number of codewords. Data is encoded into one or more full size codewords and at least one truncated codewords. Typically, data is encoded and decoded using one or more full size codewords and one truncated codeword. The truncated codewords are a two-dimensional array having a number of columns (or rows or both) less than the full size codeword. In this manner, the disclosed truncated codewords are adaptable to various system parameters that affect code rate.

Abstract: A variable length decoding device for decoding variable length coding data and run length coding data according to the present invention comprises a variable length decoding unit 3 for serially decoding the variable length coding data and the run length coding data inputted from outside in a state in which “RUN” representing number of “0” and “LEVEL” representing a magnitude of a coefficient value are combined, a data buffer 4 for storing the “LEVEL”, address retainers 5 and 6 for retaining an address of the “LEVEL” corresponding to the “RUN” based on the number of “0” indicated by the “RUN”, a write control unit 7 for writing the “LEVEL” in the data buffer 4 based on the information of the address retainers, and a read control unit 8 for reading the “LEVEL” from the data buffer 4 based on the information of the address retainers.

Abstract: A code processing circuit includes a plurality of coders which encode different kinds of data, respectively, a first buffer which stores the codes outputted from the coders provided corresponding to the plurality of coders, a second buffer which stores the lengths of the codes outputted from the coders provided corresponding to the plurality of coders, a first adder which adds the code lengths stored in the second buffer provided corresponding to the plurality of coders, a second adder which adds all the code lengths added in the first adder, and an adjustment unit which adjusts an output code by the unit of 1 bit based on the codes stored in the first buffer, the code lengths stored in the second buffer and the code lengths added in the second adder.

Abstract: When a zero run, which violating G constraint of a run-length-limited (RLL) code, is detected from the data stored in a first input register 1111 and a second input register 1112, bits before and after the zero run is transferred to a temporary register 1150 via a bus for zero run removal 1130 to be combined to each other. Thus, by effectively using the mechanism of bus transfer, a circuit can be simplified, thereby realizing a small circuit.

Abstract: A bus compression apparatus for compressing data is provided to suppress an EMI signal and to simplify a data bus structure. In the apparatus, the voltage levels of the digital output signals are summed in accordance with the resistance values of the data compression circuit to produce a compressed analog signal. The compressed analog signal is transmitted through a bus lines to a data decompressor which reproduces the digital data in response to the voltage levels of the compressed analog signal.

Abstract: Presented herein is a run-level split FIFO. According to one embodiment of the present invention, there is presented a method for inverse quantizing. The method comprising receiving a data word; detecting whether the data word comprises a command or run-level data; storing the command, if the data word comprises a command; and processing the run-level data, if the data word comprises run-level data.

Abstract: Input signals are electronically watermarked using an uneven or non-uniform sampling rate. The uneven or non-uniform sampling may be pseudo-random. The uneven or non-uniform sampling meets the Nyquist criterion so that aliasing and loss of content are avoided. The resulting sampling pattern in the sampled data is detectable by a comparison with the original source data.

Abstract: A method and associated decoder, system, device and storage means for decoding codewords of variable length from a bit stream, in which minimum and maximum lengths are defined for the codewords, wherein the bit stream is processed in parts, each part being subjected to a search for codewords, and where found codewords are decoded. At least partly overlapping fields are extracted from the bit stream part in such a way that the starting point of at least two fields is a possible starting point of a codeword in that part. In at least one field, the end of the codeword is searched, and the data related to the codeword is determined on the basis of the end point of the codeword. Data relating to at least one codeword is used to determine the occurrence of the codeword intended to be decoded in a field, and the found codeword is decoded.

Abstract: This invention re-encodes encoded data (e.g., PackBits encoded data), which is expressed by a data format of a runlength code part indicating the runlength of the same data and a data part indicating the data, and a runlength code part indicating the runlength of a different data stream and a data part indicating the different data stream, to the same data format without decoding that encoded data, thereby improving a compression ratio. To this end, upon reception of data encoded by a PackBits encoding process, a data division unit separates that data into information indicating the runlength of data, and a data part, and outputs them as num and data. A data processing unit masks a predetermined bit in accordance with an instruction from a monitor unit, and outputs that result to a data combining unit. The data combining unit and a data output unit reconstruct and output data in the PackBits format in accordance with the masked data part and num data.

Abstract: A method of encoding a first stream of digital signal data words is provided. A most recent value of the first stream of digital signal data words is received and memorized. A previous value of the first stream of digital data words is received and memorized. The most recent and the previous values of the stream of digital data words are combined to create a second data stream. The words are converted in the second data stream into a serial representation. The serial representation is transmitted on a single wire interface.

Abstract: The invention relates to a method, a system and a computer program product for bit swapping, wherein periodically I successive bits of a data packet that comprises K bits are mapped onto interleaved bit positions in I different bursts, respectively, according to a predefined interleaving scheme and a selected interleaving depth I, comprising the step of swapping the value of at least one bit that is associated with a respective first bit position m in the data packet with the value of a bit that is associated with a respective second bit position n in the data packet, wherein the respective second bit position n is selected such that n>m holds and that the difference n?m is divisible by I.

Abstract: The present invention provides a method for tuning output drivers to an operating frequency based on settings used to tune other devices within the device such as a VCO. First the VCO within a PLL and clock circuit is tuned to the desired operating frequency. This operating frequency then corresponds to a discrete tuning setting. The discrete setting that causes the VCO to function at the operating frequency are then transferred to scaled amplifiers within output drivers. These drivers are then tuned to the operating frequency with these settings. This process eliminates the need to individually tune each output driver to function properly at the operating frequency.

Abstract: An apparatus accepts randomly arriving blacks of parallel digital data of varying bit lengths termed datum segments that may have been generated by stripping leading zeros from bytes of a fixed size, each having associated therewith a bit count code that expresses the bit length of each datum segment in the form nnnnndddd . . . , the “n” being the bits of the bit count code in such number as to encompass the memory capacity of a receiving device to which the datum segments are to be sent, and the “d” representing the actual datum segment bits. The apparatus concatenates the nnnnndddd . . . expressions to form a continuous bit sequence that is saved so that each nnnnndddd . . . expression is accessible thereafter through the computer address therefor, such use preferably being by a circuit of matching bit length, the format, however, allowing the original form of the data to be recovered if desired.

Abstract: A lossless data compression system comprising a content addressable memory dictionary 30 and a coder 38, characterised by run length encoding means 39 connected to receive the output of the coder 38, said encoding means 39 being arranged to count the number of times a match consecutively occurs at a predetermined dictionary location.

Abstract: This invention re-encodes encoded data (e.g., PackBits encoded data), which is expressed by a data format of a runlength code part indicating the runlength of the same data and a data part indicating the data, and a runlength code part indicating the runlength of a different data stream and a data part indicating the different data stream, to the same data format without decoding that encoded data, thereby improving a compression ratio. To this end, upon reception of data encoded by a PackBits encoding process, a data division unit separates that data into information indicating the runlength of data, and a data part, and outputs them as num and data. A data processing unit masks a predetermined bit in accordance with an instruction from a monitor unit, and outputs that result to a data combining unit. The data combining unit and a data output unit reconstruct and output data in the PackBits format in accordance with the masked data part and num data.

Abstract: A method of encoding a digital data stream which comprises providing a first stream of clock pulses at a first rate; deriving a second stream of clock pulses from the first stream at a second rate which is an integer sub-multiple of the first rate and less than the minimum bit rate in the data stream; monitoring the data stream for changes in level therein; counting pulses in the first stream starting with the occurrence of a pulse in the second stream; capturing the pulse count when a change in level in the data stream is detected or when the next pulse in the second stream of clock pulses occurs; and upon the occurrence of this pulse in the second stream producing a time domain descriptor of the data by combining the count obtained with information as to the direction of the change in level in the data input stream.

Abstract: Methods and apparatuses for run length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor in response to the microprocessor receiving a single instruction includes: receiving a first list of a plurality of elements from a first vector register; generating a plurality of run values respectively for the first list of elements, at least one of the plurality of run values indicating the number of consecutive elements of a first value immediately preceding the corresponding element in the first list; and outputting the plurality of run values into a second vector register; where the above operations are performed in response to the microprocessor receiving the single instruction.

Abstract: A computer implemented method and system for selecting a string for serving as a reference string for a comparison scheme for compressing a set of strings calculates preliminary compression results for every string relative to an initial reference string, and uses the preliminary compression results to find a better reference string without additional compression tests. According to one embodiment, a histogram is calculated showing the number of occurrences of each compressed length for each string in the set plotted against the initial reference string and the better reference string has a length corresponding to an average compression length or center of gravity of the histogram.

Abstract: An encoder suppresses effectively the high-frequency components of data to be transmitted by decreasing the changing points of serial data, thereby suppressing EMI. A changing-point counter counts changing points of n-bit data (n: a positive integer) to generate a counting result, where values of adjoining bits change at each of the changing points The changing-point counter outputting a discrimination bit which is true when the counting result exceeds a predetermined value. A code converter converts the n-bit data in such a way that bits of the n-bit data located at predetermined positions are inverted when the discrimination bit is true. A parallel-to-serial converter converts (n+1)-bit data to a (n+1)-bit serial code, the (n+1)-bit data being generated by adding the discrimination bit to an output of the code converter.

Abstract: A method for run-length encoding two or more data values, the method comprising: loading the data values into storage by forming a first data string, the data string comprising a plurality of data sub-strings and each data sub-string representing at least one of the data values; generating a second data string having a data sub-string corresponding to each data sub-string of the first data string, all the bits of each of the data sub-strings of the second data string having a first predetermined value if all the bits of the corresponding data sub-string of the first data string have a second predetermined value and having a third predetermined value if any of the bits of the corresponding data sub-string of the first data string has other than the second predetermined value; starting from a predetermined end of the second data string, counting the number of consecutive bits of the second data spring having the first predetermined value; and dividing the said number by the number of bits in each data sub-strin

Abstract: A method of compressing pixel information is described. The pixel data is received in a data stream and compressed into a compressed data format by identifying a run of consecutive bytes of the data stream based on the similarity of the consecutive data bytes in the data stream. A mode bit of a compression byte is used to indicate whether a run of consecutive bytes is identified. Count bits of the compression byte are used to indicate the number of times the data bytes are repeated and zero counts may be used to indicate particular types of runs, for example, runs to the end of a scan line and the end of an object. Where a pixel byte is represented by 8 bits, the data stream may be compressed in multiples of four bytes at a time. If a pixel is represent by less than 8 bits, the compression method may look for repetitions of similar bytes one byte at a time.