Abstract: In an LZW data compressor, the occurrence of a character run in the input character stream is determined and the run count is added to the existing code in the compressor code counter to generate a compressor code output representative of the run count. The LZW data decompressor subtracts the existing code in the decompressor code counter from the received compressed code to recover the run count. In accordance with a further feature, large length runs are processed by reducing the run count to less than the system maximum code by subtracting a selected predetermined constant from the run count. The reduced run count is outputted by the compressor preceded by a reserved code representative of the selected predetermined constant. In response to the received reserved code and the reduced count that follows, the decompressor adds the selected predetermined constant corresponding to the received reserved code to the received reduced count to recover the original run count.

Abstract: The disclosed data compressor receives an input stream of data characters and provides a corresponding stream of output codes. The compressor generates a sequence of numerically increasing output codes corresponding to numerically increasing contiguous segments of a detected run of the same data character. Non-run characters of the input stream are transmitted directly in synchronism with incrementing the codes of the code sequence. In one embodiment, the number of characters in the run segments are stored together with the respective codes representing the segments. In later encounters of a previously processed run, the stored data is accessed and the stored codes corresponding to the run segments are output as appropriate.

Abstract: What is disclosed is a method that allows a fixed length (L) codeword and flag to serve as a structure for encoding large run of identical values, a single bit capable of representing 2.sup.L such values. The zero non coding method may be utilized to efficiently encode data sets, such as images or other data files with large consecutive runs of a particular value such as zero. In an entropy encoding scheme, such enhanced zero run coding may be combined with variable length coding for non-zero values.

Abstract: A variable-length coding device includes: a code presence/absence determination table storing information concerning whether a code is allocated or not correspondingly to a prescribed region in a region represented by a combination of run data and level data; a first region determination circuit and a second region determination circuit determining whether a pair of run data and level data is contained in the prescribed region; and a run.

Abstract: The disclosed data compressor receives an input stream of data characters and provides a corresponding stream of output codes. The compressor provides a sequence of numerically increasing output codes corresponding to numerically increasing contiguous segments of a detected run of the same character. The number of characters in the detected run is determined and a mathematical algorithm, using the number of characters in the run, mathematically generates the appropriate sequence of codes. One disclosed embodiment utilizes a mathematical algorithm that iteratively diminishes the number of run characters by an iteratively increasing segment index. Another embodiment utilizes a quadratic equation algorithm that computes the codes from the number of characters in the run utilizing equations derived from the expression for the sum of the first n numbers. In a further embodiment, the number of characters in the run segments are stored together with the respective codes representing the segments.

Abstract: A video data run length decoding apparatus is disclosed.

Abstract: What is disclosed is a method that allows a fixed length codeword and flag to serve as a structure for encoding large run lengths, a sequence of such structures representing the number of zeroes between two non-zero values in a data set to be encoded. Also disclosed is an adaptive encoding technique that determines an encoding method suitable with the entropy characteristics of the data to be encoded. An architecture is disclosed which allows the size of the fixed length to be varied, if needed. This architecture includes a plurality of logic networks coupled to a single counter, each of which may be enabled depending on the desired codeword size.

Abstract: Previously compressed data is re-compressed with a better algorithm. A data analyzer analyses the compressed data to determine whether the data has been compressed with a supported compression format such as GIF, JPG or PNG. A data decompressor decompresses the data, then a data compressor re-compresses the data using the superior compression algorithm. When the data is to be reused, a data decompressor decompresses the data and a data compressor recompresses the data using the original compression algorithm. The invention may be implemented over a path in a data network. Compressed data that is to be sent over path is intercepted and re-compressed with the superior algorithm before being sent over the path. On the other end of the path, the data is converted back to its original compression format.

Abstract: An electronic spreadsheet system of the present invention includes a notebook interface having a plurality of notebook pages, each of which may contain a spread of information cells, or other desired page type (e.g., Graphs page). Methods are provided for rapidly accessing and processing information on the different pages, including displaying a plurality of page identifiers for selecting individual pages, and further including a preferred syntax for referencing information. Additional methods are described for in-memory management and persistent storage of notebooks and their pages.

Abstract: A method for creating a file of compressed data representing trace events produced in a circuit simulation. The method creates first and second arrays of value changes for a facility being monitored, and the time of the changes. The first and second arrays of data are compressed by identifying any data forming a repeating pattern, by the pattern and an iteration count. Each of these arrays have a common index, representing the position data for a facility as changed. Facility names are also compressed using a hashing algorithm which stores an index based on the hash result. The reproduction of the compressed data occurs without expanding the entire data file, by locating stored data by the facility name index which points to the position in the file of the stored facility data. The data is reviewed based on an inquiry which selects particular time intervals, which may be retrieved from the file along with the related values.

Abstract: There is provided a high speed variable length coding system having a small hardware scale.

Abstract: A data encoding method having a prediction setting process that designates a numerically superior symbol as either a "0" or a "1", and the other one is designated as a numerically inferior symbol. Then a binary bit string composed of "0"s and "1"s is input, and the numerically superior symbol is predicted to continuously repeat for n symbols, where n is set as a prediction bit number. A prediction result output process outputs a prediction correct signal that is either a "0" or a "1" when a prediction is correct for the observed series. The process then moves to an operation to perform encoding of a bit series containing the next n symbols, or otherwise outputs the other signal (i.e., that is not used to represent that the prediction is correct) as a prediction failure signal.

Abstract: A digital data slicer which can allow the digital sum value (DSV) of the sliced signal to approach zero is provided. The digital data slicer includes a comparator for comparing the input signal with an analog reference slice level to thereby generate the sliced signal. A DSV calculator is used to obtain the DSV of the sliced signal. A DSV processor is used to compare the DSV with a predefined tolerance window to thereby generate a digital correcting signal. A digital-to-analog (D/A) converter is then used to convert the digital correcting signal into an analog form which either raises or lowers the reference slice level to the comparator. This feedback control goes on until the DSV is within the range defined by the tolerance window.

Abstract: Image data decompression apparatus and method for receiving data words comprising a first sub-word and a second sub-word, at least some possible values of the first sub-word specifying a run of at least m instances of a predetermined data value, corresponding second sub-words specifying a number of instances of the predetermined data value in a range from at least m instances. The apparatus includes a first decoder for decoding the first sub-words to detect whether a current first sub-word specifies a run of at least m instances of the predetermined value, and a second decoder for decoding the second sub-words to generate output decoded data.

Abstract: According to the present invention, there is provided a method for compressing each of a plurality of data packets to form a compressed packet for transmission by a communication device, the data packets being composed of a sequence of data elements and the data packets being stored on a first computer such that the method is performed by the first computer, the method comprising the steps of: (a) receiving one of the plurality of data packets designated as packet P.sub.m ; (b) parsing the packet P.sub.m, such that the sequence of data elements of the packet P.sub.

Abstract: Apparatus and method are provided for enabling unimpeded, clock-to-clock communication between different classes of equipment including converting without queuing of data parallel bytes of digital data having a given number of binary bits to parallel bytes having a different (greater or smaller) number of bits.

Abstract: A decoding apparatus includes a quantized bit count storage, a sound-image data decomposer, a unit frame length calculator, a quantized bit count adder, a quantized bit total value storage, a comparator, and a decoding processor. The comparator compares the value of the unit frame length of an input compressed bit stream with the quantized bit total value of the compressed bit stream, and outputs an error occurrence signal if the quantized bit total value exceeds the value of the unit frame length. If the comparator outputs the error occurrence signal to the decoding processor, the decoding processor performs interpolation processing for a sound-image signal and thereby prevents production of noise which is produced when the quantized bit total value exceeds the value of the unit frame length.

Abstract: The present invention generates a reference signal including identification information based on a first coding method and generates data signals by a second coding method different from the first coding method. Next, it time division multiplexes signals by allocating the reference signal to a reference time slot and allocating data signals to time slots of which phase difference between the reference time slot is predetermined, and sends a multiplexed signal. In a receiver side, the reference time slot is detected based on identification information in a transmitted signal.

Abstract: For the transmission of variable length coded data blocks, a threshold arithmetic calculation circuit (9) obtains a threshold from an average of the bit lengths of the variable length coded data blocks for each group of such block, and the judgment circuit (10) makes a judgment as to whether or not those variable length coded data blocks have bit lengths exceeding the threshold of the block group to which such data blocks belong. Then, a block divider circuit 11 divides the variable length coded data blocks having bit lengths exceeding the threshold into blocks having small bit lengths. Each block thus obtained is fixedly equalized in bit length to an average length level and transmitted in that condition.

Abstract: A method for providing improved data compression efficiency to a data compressor unit is disclosed. Before sending the uncompressed data stream to the data compressor unit, an incoming data byte from the uncompressed data stream is first compared with a preceding data byte from the uncompressed data stream. A first counter value is incremented in response to a match between the incoming data byte and the preceding data byte. A second counter value is then incremented in response to subsequent matches between an incoming data byte and its preceding data byte after the first counter value has reached a preset value. The second counter value is finally sent to the data compressor unit at the completion of a run of the incoming data byte in substitution of a portion of the run, such that the data compressor unit can quickly resume its optimal compression ratio after an occurrence of the run within the uncompressed data stream.

Abstract: A data compression and decompression apparatus and method providing a high compression ratio. The data compressing apparatus includes, for example, an obtaining section, a first coding section, a first controlling section, a judging section, a second coding section, and a second controlling section. Characters are obtained one after another from a compression target. A code is then output corresponding to the character when the character and a predetermined number of characters are not identical. Subsequently, the number of characters obtained are counted when the character and the predetermined number of characters are identical, and a code corresponding to the number of characters counted is output when the character obtained is not identical with the predetermined number of characters.

Abstract: A method for compression of digital data in a computer having a processor and a memory, wherein a group of consecutive bits having the same binary value is represented by a result number corresponding to the number of the consecutive bits. The method involves the following steps. A block of digital data to be compressed is provided. A bit detect selection parameter determines a bit value to be counted for counting consecutive bits. The processor is instructed to count from a first end of the block of digital data toward a second end of the block of digital data the number of consecutive bits having the bit value determined by the bit detect selection parameter. The number of bits so counted is stored, and the bit detect selection parameter is toggled. The processor is then instructed to count from the last bit counted toward the second end of the block of digital data the number of bits having the bit value determined by the current bit detect selection parameter.

Abstract: A decoding apparatus includes a first decoder for performing decoding by dividing first coded data consisting of a bit sequence into divided data each having a bit length of 1 bit or more, and a second decoder which performs decoding on the basis of the "1" or "0" run length and the remaining bit string of second coded data consisting of a bit sequence, and shares at least a circuit portion with the first decoder.

Abstract: In a method for transmitting digital data of images, etc., under the condition of n>m and k<n-m, when the synchronous data are not transmitted, the image data of "m" bits for the respective pixels are translated into the n-bit codes, of which identical logical bits do not continue more than or equal to "k" even if they are sequentially time-division multiplexed and transmitted with any combination, and then time-division multiplexed and transmitted. On the other hand, when the synchronous data are transmitted, the m-bit image data of the pixel is directly time-division multiplexed, and to this data, a serial code which is composed of "n-m" bits and including the specific bit string which is the continuous "k" bits of the identical logic is added. Thereby, making it possible to perform transmission and reception of the digital data and the synchronous data through one transmission line without a break of transmission or reception of the image data.

Abstract: A data compression method utilizing a series of rules which are chosen for best compressing selected data. Rules are provided for converting each datum into a binary value, and encoding this binary value into a variable-width bit field. Rules are provided for automatically increasing or decreasing the binary field width which encodes the next data value, based on the current field width and encoded data value. An escape code is used to increase the field width for the next encoded value. A rule for efficient run-length encoding of repeated values or codes may also be included.

Abstract: A runlength coding apparatus converts an input data stream including a plurality of zeros and non-zero values to a runlength coded signal. The apparatus has an input buffer, a runlength detector, and a level detector. First, the input buffer generates a first and a second sequences of the input data stream. The runlength detector provides runlengths based on the first and the second sequences, and generates indicating signals by checking whether each of elements in the first and the second sequences is zero. Meanwhile, the level detector supplies levels based on the indicating signals and the first and the second sequences. The detected runlengths and levels are combined a multiplicity of run-level pairs and provided as the runlength coded signal.

Abstract: Data items associated with different locations in a spatial field of locations are written in a memory. The memory comprises a length memory in which for each location there is stored a length code which indicates the memory length required for the data item. For the reading of a data item associated with a location, the address of the data item is calculated by reading the length codes for the data items of preceding locations from the memory and by summing the lengths indicated.

Abstract: A variable-length code decoder includes plural barrel shifters, each of which executes shift processing on inputted variable-length code data bit by bit from the 0 bit to (the bit number of a maximum length codeword -1). The barrel shifters, which are in number equal to the bit number of the maximum length codeword, are arranged in parallel connection. Plural storing devices are provided, each of which stores a pair of a decoded symbol and codeword length thereof corresponding to code data. Plural fetching devices are provided, each of which fetches the pair of the decoded symbol and the codeword length thereof in accordance with the code data outputted from each of the barrel shifters. Each of the fetching devices is connected to a respective barrel shifter and storing devices. A selecting device is provided for selecting a predetermined pair from plural pairs of the decoded symbol and the codeword length fetched by the plural fetching devices in an initial decoding process.

Abstract: In system and method for data compression and decompression, runs of the same bit value are identified within the data to be compressed and decompressed into a series of groups of bits wherein the number of bits in each group progressively increases as compared to the preceding groups until all of the bits of the run can be represented.

Abstract: A runlength coding method converts an input data stream including a multiplicity of zeros and non-zero values to a runlength coded signal. A first sequence and a second sequence are generated based on the input data stream, and then first and second count control information and also add control information are produced based on the data in the first and the second sequences. In response to the first count control information, the number of zeros in the first sequence is calculated to thereby provide a first counted value and the number of zeros in the second sequence is computed responsive to the second count control information so as to supply a second counted value. The determined counted values are summed and provided as a runlength in response to the add control information, wherein the runlength represents the number of zeros in a run of continuous zeros preceding a non-zero value in the input data stream.

Abstract: A high-efficiency encoding apparatus having a data division circuit which applies 1-dimensional scanning to the orthogonal-transformed data obtained by applying orthogonal transformation to blocked digital data in the unit of block and divides the data into run-length data and coefficient data, an encoding circuit which applies run-length encoding to the divided run-length data by employing data of the highest probability of occurrence (for example 0), and an encoding circuit which applies run-length encoding to the divided coefficient data by employing data of the highest probability of occurrence (for example 1), thereby reduces the amount of the digital data.

Abstract: A zero-run developing circuit for performing a zero-run developing process for placing zeros represented by a run between first non-zero data and second non-zero data of a block of a predetermined number of run-length signals, each of which is composed of the level of the value of non-zero data and the run that is the number of zero-data followed by the non-zero data is disclosed, that comprises a latch circuit for latching the levels of the predetermined number of the non-zero data, a first write position generating circuit for generating a first latch position of the latch circuit at which the first non-zero data is written corresponding to a first run length signal, and a second write position generating circuit for generating a second latch position of the latch circuit at which the second non-zero data is written corresponding to the first run-length signal and a second run-length signal.

Abstract: A method and apparatus for losslessly compressing binary data using a technique referred to as Double Run-Length Encoding (DRLE). DRLE has particular application to the compression of gray-scale data as it is being processed for printing by a laser printer or other continuous raster scan device. DRLE records repeating patterns of ones and zeros with little computational complexity. Compression ratios that may be an order of magnitude or more are obtained frequently on data that may not compress well using traditional Run-Length Encoding (RLE). DRLE uses a sequential history of order-pairs that denote variable-length patterns of zeros and ones, and then encodes these patterns as they repeat themselves.

Abstract: A run-length decoding apparatus, for use in a video signal decoding system, for decoding a run level coded video signal to provide decoded video signal comprises an address generator, receiving the run data, for generating a write address denoting a memory location for storing the level data, a counter, responsive to a clock signal, for generating a read address for sequentially addressing the memory locations from an upper most memory location to a lower most memory location, and memory, having a number of memory locations, for storing the level data based on the write address, and for generating the decoded data stored in the memory locations based on the read addresses to thereby provide the decoded video signal.

Abstract: A method used preferably with LZSS-based compression methods for compressing a stream of digital data. The method uses a run-length encoding scheme especially suited for data strings of identical data bytes having large run-lengths, such as data representing scanned images. The method reads an input data stream to determine the length of the data strings. Longer data strings are then encoded in one of two ways depending on the length of the string. For data strings having run-lengths less than 18 bytes, a cleared offset and the actual run-length are written to an output buffer and then a run byte is written to the output buffer. For data strings of 18 bytes or longer, a set offset and an encoded run-length are written to the output buffer and then a run byte is written to the output buffer. The encoded run-length is written in two parts obtained by dividing the run length by a factor of 255. The first of two parts of the encoded run-length is the quotient; the second part is the remainder.

Abstract: An input data sequence is divided into fixed-length source segments, and each source segment is predicted from preceding data. The data are coded as a sequence of coded segments, each designating a non-negative number of correctly predicted segments and a non-negative number of literal segments. The literal segments are inserted into the coded data among the coded segments. The coded data are decoded by decoding each coded segment, predicting the designated number of correctly predicted segments from previously decoded data, and copying the literal segments. The length of the coded segments may vary according to the number of consecutive correctly predicted segments. The prediction rule, or the original data, may be modified under certain conditions, in order to increase the predictability of the source segments.

Abstract: Image data such as text or half-tone images is compressed and decompressed. A compressor has three phases: a bit-run length phase that counts the length of each run of consecutive identical pixels; a pairs-repetition phase that compresses repeated pairs of pixel run values to one copy of the repeated pair and a repeat count; and an optional dictionary-based micro-table encoder. The micro-table, which may be used in any application calling for a least recently used (LRU) mechanism, has multiple qualification layers, with elements within a qualification layer being promoted to the next higher qualification layer upon the occurrence of a table hit for that element, and being demoted to the next lower qualification layer by being bumped by elements promoted up from below. The result is a table that is weighted both by frequency and recency of hits.

Abstract: An apparatus and a method for controlling a mode of operation of a data converter is based on a length of an input word signal to the data converter. The apparatus includes a bit counter that counts the number of bits in the word received by the data converter and provides a word length signal corresponding to the number of bits in the word, and a mode selector that receives the word length signal and selects an operational mode of the data converter based on the word length signal. The method includes steps of counting the number of bits in the word, and selecting a mode of operation of the data converter based on the number of bits in the word.

Abstract: A runlength coding apparatus for encoding an input data stream to provide a runlength coded signal comprises a first memory for temporarily storing the zeros and non-zero values included in the input data stream, a run-level detection block for detecting a plurality of run-level pairs from the input data values, each of the run-level pairs including a runlength and a corresponding level, a repetition index detection block for detecting the number of runlengths having an identical value, a buffer control block for generating a first read signal and M number of second read signals based on the runlength repetition index, a second memory connected to the run-level detection means for sequentially storing the level data and for generating the level data stored therein based on the M number of second read signals, a third memory connected to the run-level detection means for sequentially storing the runlength data and for generating the runlength data stored therein based on the first read signal, and a formatting

Abstract: A high performance variable length decoder which includes a tagging circuit that tags the boundaries of code words in an incoming bit stream, providing a tag stream output and a bussed bit stream output that coincides in time with the tag stream output. The bussed tag stream output is connected to an input of a high speed parallel word length computation circuit, and the bussed bit stream output is connected to an input of a parallel value decoder circuit. The parallel word length computation circuit (word length decoding loop) receives the bussed tag stream and computes (decodes) the length of a singular code word in a singular mode of operation, or the lengths of one or more contiguous code words in a contiguous mode of operation.

Abstract: A variable-length decoder arrangement having enhanced speed capacity, in which an input bit stream is tagged with the codeword boundary information by a tree-searching state machine. In order to reduce the memory requirements of the tag buffer, run-length encoding techniques are used to compress the tag information. This compressed tag information is used in a closed-loop parsing loop wherein a compressed tag stream length conversion table decoder is used to determine the length of the compressed tag codewords which are used to control the barrel shifter in the closed-loop parsing loop, while the compressed tag codewords are decoded into actual word-lengths in a word-length conversion table decoder. These actual word-lengths are then accumulated and used to control a barrel shifter for decoding the variable-length bit stream.

Abstract: A variable length decoder with adaptive acceleration in processing of an encoded input bit stream which includes an input circuit for receiving the input bit stream and for providing a decoding window that includes a sequence of bits which include one or more code words to be decoded at an output thereof, a code word length decoding circuit for determining the combined length of a combination of two or more code words received from the input circuit in response to a first value of a control signal and for generating a combined length signal representative of the determined combined length, and for determining the length of an individual code word received from the input circuit in response to a second value of the control signal and for generating an individual word length signal representative of the determined length of the individual code word, a computation loop circuit for receiving the combined length signal or the individual word length signal from the code word length decoding circuit and, in response

Abstract: A Huffman code decoding circuit including a leading bit position determination unit for determining a leading bit position of a Huffman code to be taken out of a Huffman code data sequence to take in a predetermined number of bits from the leading bit position of the Huffman code data sequence, a first decoding table for inputting a first data sequence composed of a predetermined number of bits staring with the leading bit of the Huffman code data sequence output from the leading bit position determination unit to output a first decoded word and a first code length corresponding to the first data sequence input as an address, a plurality of 2nd to n-th decoding tables for inputting 2nd to n-th data sequences composed of a predetermined number of bits starting at a different bit position of the Huffman code data sequence output from the leading bit position determination unit to output a decoded word and a code length corresponding to the 2nd to n-th data sequences input as addresses, and a selector for select

Abstract: A system for compressing digital data at one byte-per-cycle throughput by removing redundancy before storage or transmission. The system includes an improved Ziv-Lempel LZ1 process that uses a history buffer to save the most recent source string symbols for use in encoding the source symbols as "match-length" and "match-offset" tokens. The match-length code symbols are selected from two groups of buckets that are assigned variable-length prefixes for the shorter, more probable match-lengths and a fixed-length prefix code for the longer, less probable match-lengths. This exploits a transition from Laplacian match-length probability distribution to Uniform match-length probability distribution for longer match-lengths. The offset code field length is reduced during start-up to improve start-up compression efficiency during filling of the history buffer. The match-length code book is limited to a maximum value T<256 to limit latency and simplify the process.

Abstract: A method and apparatus for compressing a data vector of a predetermined number of data points. The apparatus includes a memory for storing the compressed data vector, a first comparator for determining a largest and smallest data point of the data vector and a second comparator for comparing the largest and smallest data point and when they are equal, causing a first data point of the data vector to be stored in the memory as the compressed data vector. The apparatus also includes a first processor for determining a data field width necessary to uniquely describe a largest relative magnitude data point and a second processor for storing the data points of the data vector as the compressed vector in data fields of memory of the data field width.

Abstract: A method of utilizing compression in programming programmable logic devices is disclosed. The present invention compresses the configuration file to be used in programming a programmable logic device. The compression step reduces the size of the configuration file. The reduction in the size of the compression file results in the reduction in the size of the memory device used to store the configuration file before it is used to program the programmable logic device.

Abstract: A variable-length code table, which is used for producing a variable-length code from data formed of one set of first and second equal-length components, stores at an address uniquely assigned by the one set of the equal-length components a corresponding variable-length code and a code length of the variable-length code. Combination of the first and second equal-length components is preselected such that the maximum value of the absolute value of the first equal-length component increases as the absolute value of the second equal-length component combined therewith decreases. The second equal-length components are classified into a plurality of classes in accordance with the magnitude of the absolute value.

Abstract: A pixel data encoder for use in a facsimile apparatus features a first in first out memory for storing one-dimensional binary pixel data sequences in synchronism with a data acquisition clock; a run length determiner coupled to receive the one-dimensional binary pixel data sequences stored in the first in first out memory, the run length determiner calculating a run length for each of the one-dimensinal binary pixel data sequences received; and an encoding section which issues a one-bit address signal for indicating raw data will be issued and N-bit raw data in the event that the run length is less than a predetermined run length N, the encoding section issuing an address code and a remainder code in the event that the run length exceeds N, the address code consisting of consecutive binary level "1"s with a bit length (M-2) and a binary level "0", and the remainder code consisting of a binary sequence representing the run length wherein the most significant bit of the binary sequence is omitted, M representin

Abstract: Reconfiguring data in a manner that increases bit redundancy, and compressing the reconfigured data in an iterative or recursive manner until the desired compression ratio is obtained. The data are divided into one or more packets and the bits of the data in each packet are redistributed between two blocks. In one block the number of occurrences of adjacent bits of the "1" state is, on average, greater than the number of occurrences of adjacent bits of the "0" state and adjacent bits of differing states. In the other block the number of occurrences of adjacent bits of the "0" state is, on average, greater than the number of occurrences of adjacent bits of the "1" state and adjacent bits of differing states. The blocks are thus conducive to compression algorithms that exploit bit redundancy.

Abstract: A serial data decoding system is described in which a state machine (FIG. 5) is provided having a plurality of branching hierarchies of states, each branching hierarchy of states corresponding to a different decoding table. The state machine incorporates a memory 72 storing control data words (FIG. 7). A latch 74 stores the most recent control data word to be output from the memory. The memory 72 is addressed with a read address formed from a concatenation of the latched value 84, a table selecting word 86, Y/C and a received bit of serial data. When the state machine enters a state 88 corresponding to valid code, the current control data word is output as an identifier of that valid code.