Abstract: A method of modulating a series of input digital symbols of a first modulation scheme is provided. The method is implemented by a transmitter and includes receiving a sequential series of samples of the digital symbols in a first domain of the first modulation scheme. The first domain is one of the time domain and the frequency domain. The method further includes determining a dual of the first modulation scheme. The dual has a second modulation scheme in a second domain that is different from the first domain the second domain is the other of the time domain and the frequency domain. The method further includes applying a 90 degree rotational operation to the second modulation scheme to generate a rotational modulation format, modulating the series of digital symbols with the generated rotational modulation format, and outputting the modulated series of digital symbols to a receiver.

Abstract: Example implementations relate data communication cables. As an example, a data communication cable includes a first electrical connector implementing a first data communication protocol. The first electrical connector includes a set of power pins and a set of data pins. The data communication cable also includes a header connector physically coupled to the set of data pins to route data from a header of a computing device to the set of data pins via the first communication protocol. The data communication cable further includes a second electrical connector implementing a second data communication protocol. The second electrical connector is physically coupled to the set of power pins to provide power from a data communication port of the computing device to the set of power pins via the second data communication protocol.

Abstract: A signal transmission device, includes a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute: irradiating incoming light, which includes one or more symbols with which the incoming light has been varied in response to a signal to be transmitted, on an arbitrary object with a first intensity; and controlling an amplitude of the first intensity on a basis of a reflectance of the incoming light irradiated on the object.

Abstract: To set an optimum offset voltage and detect an NRZ signal with a very small amplitude. An NRZ signal amplifying device 2 includes: input-side voltage detection means 13 for detecting a high-level voltage and a low-level voltage of an input signal to the main amplifier 12; output-side voltage detection means 14 for detecting the two signals inverted relative to each other; and offset voltage control means 15 for calculating a center voltage between the detected high-level voltage and low-level voltage, setting an offset voltage at which the center voltage is the center of an appropriate input range of the main amplifier 12 to the offset circuit 11, and finely adjusting the offset voltage, such that a voltage difference between the detected two signals inverted relative to each other and a polarity change point is close to 0.

Abstract: In a data carrier (1) which includes receiving means (5) for receiving a modulated carrier signal (MTS) which contains a data signal (DS1) encoded in conformity with an encoding method (MA, PW, MI, RTZ, FSK, PSK), demodulation means (9) for demodulating the received modulated carrier signal (MTS) and for outputting the encoded data signal (DS1) contained therein, decoding means (10, 20) for decoding the encoded data signal (DS1) and for outputting data (D1, D2), and data processing means (11) for processing the data (D1, D2) output by the decoding means (10, 20), the decoding means (10, 20) are provided with at least a first decoding stage (12) and a second decoding stage (13), the first decoding stage (12) being arranged to decode a data signal (DS1) encoded in conformity with a first method (RTZ) whereas the second decoding stage (13) is arranged to decode a data signal (DS1) encoded in conformity with a second method (MI).

Abstract: An embodiment may include circuitry to generate and/or receive, at least in part, a signal that may include at least one waveform. The at least one waveform may include at least one portion followed by at least one other portion. The at least one portion may include a plurality of levels to be compared to data encoding levels to determine whether the plurality of levels satisfy ratios determined based at least in part upon the plurality of levels and the data encoding levels. The at least one other portion may include maximum and minimum data encoding levels to facilitate emphasis measurement. Many alternatives, variations, and modifications are possible.

Abstract: In one aspect, methods and systems for variable-block length encoding of data, such as an inverted index for a file are disclosed. These methods and systems provide for relatively fast encoding and decoding, while also providing for compact storage. Other aspects include a nearly 1:1 inverted index comprising a position vector and a data store, wherein values that have a unique location mapping are represented directly in the position vector, while for 1:n values (n>1), the position vector can include a pointer, and potentially some portion of information that would typically be stored in the data area, in order to fully use fixed width portions of the position vector (where a maximum pointer size is smaller than a maximum location identifier size).

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: A two-phase return-to-zero asynchronous transceiver is provided. The two-phase return-to-zero asynchronous transceiver is designed for on-chip interconnects. The transceiver includes a multi-stage transceiver arranged in a dual rail configuration, along with a weak keeper for each stage, a data driver for each stage, and an enable control circuit for selectively enabling the data driver, such that the data driver outputs data to a subsequent stage of the multi-stage transceiver. The enable control circuit further utilizes a handshaking protocol, which may be implemented at 0.13 ?m and 1.2 Volts. The transceiver circuit achieves a throughput of approximately 3 Gb/s with wire lengths of approximately 100 ?m.

Abstract: An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion.

Abstract: A high speed serial interface is provided. In one aspect, the high speed serial interface uses three phase modulation for jointly encoding data and clock information. Accordingly, the need for de-skewing circuitry at the receiving end of the interface is eliminated, resulting in reduced link start-up time and improved link efficiency and power consumption. In one embodiment, the high speed serial interface uses fewer signal conductors than conventional systems having separate conductors for data and clock information. In another embodiment, the serial interface allows for data to be transmitted at any speed without the receiving end having prior knowledge of the transmission data rate. In another aspect, the high speed serial interface uses polarity encoded three phase modulation for jointly encoding data and clock information. This further increases the link capacity of the serial interface by allowing for more than one bit to be transmitted in any single baud interval.

Abstract: An encoding apparatus that converts input digital data and an input clock into three-bit six-state transition encode outputs and outputs them is disclosed. The encoding apparatus has a first state transition control section, second state transition control section, and an output selection section. The first state transition control section changes a state of first data at a positive edge of the input clock. The second state transition control section changes a state of second data at a negative edge of the input clock. The output selection section alternately selects the state of the first state transition control section and the second state transition control section.

Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

Abstract: A coder is fed with pre-coded data such that the absolute value of the RDS of the code words as produced by the coder is limited. This is achieved by ensuring that in a group of 2 code words the RDS of the first code word is compensated by the RDS of the second conde word. The RDS at the end of the second code word is then zero and the excursions of the RDS from the start of the first code word until the end of the second code word are limited because there are only a limited number of bits that can contribute to an increase of the absolute value of the RDS. This principle can easily be applied to the 17PP coder.

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for inverter based return-to-zero (RZ)+non-RZ (NRZ) signaling. The interface circuit contains multiple ganged drivers (some or all of them are turned on at one point of time) and edge detection circuitry (to configure/modulate edges of the input data signal). These two circuits together generate weighted return-to-zero (RZ)+non-RZ (NRZ) signal.

Abstract: A run-length limited (RLL) encoder includes a block detection module that receives a data block that includes N portions and generates N?1 coding bits indicating whether corresponding ones of N?1 of the N portions of the data block include one of all ones and all zeros, where N is an integer greater than two. A mapping module generates an RLL codeword including N portions comprising bits that are determined by a first mapping table, a second mapping table, bits of the data block and the N?1 coding bits.

Abstract: A demodulation table for converting variable length code (d, k; m, n; r) is provided. The variable length code has a maximum constraint length r>1, has a minimum run of d (d>0), has a maximum run of k, and a basic codeword length of n bits into data having a basic data length of m bits. The demodulation table includes: a basic table for converting code patterns composed of basic codes having a basic codeword length of n bits into data patterns composed of basic data having a basic data length of m bits; and a substitution table for converting code patterns of a plurality of different minimum run successive occurrence limiting patterns determined so as to limit successive occurrences of the minimum run to a maximum of N (N>1) times into a corresponding identical data pattern.

Abstract: A physical layer device comprises a mode selector that selects a mode. A clock selects a clock frequency from T clock frequencies based on the mode. A converter module selects one of N mapping functions based on the mode and converts an n-bit input to an m-bit output based on the selected one of the N mapping functions. A scrambler module scrambles the m-bit output or passes the m-bit output unchanged based on the mode. An encoding module modulates the m-bit output based on the selected clock frequency and one of M modulation modes selected based on the mode, where T, n, m, N and M are integers greater than one and n is not equal to m.

Abstract: A run-length limited (RLL) encoder includes a problematic-block detection module that receives a data block and that generates coding bits that indicate whether at least one of N portions of the data block include one of all ones and all zeros, where N is an integer greater than one. A mapping module generates an RLL codeword based on the data block and the coding bits. The RLL codeword includes N portions. One of the N portions of the RLL codeword is populated with the coding bits. At least another one of the remaining portions of the RLL codeword is populated with at least part of the data from one of the N portions of the data block that corresponds with the one of the N portions of the RLL codeword.

Abstract: A method of generating codewords that conform to a run length limited (RLL) constraint represented by (d, k, a, b), where d is a minimum run length of a codeword, k is a maximum run length of the codeword, a is a length of source data, and b is a length of the codeword. The method includes generating codewords conforming to the RLL(d, k) constraint, and removing codewords in which a relatively long T and a relatively short T are placed adjacent to each other from the generated codewords.

Abstract: A digital modulation apparatus capable of generating a modulated code so that binary slice is correctly performed when reproducing is provided. To achieve this, in a digital modulation apparatus (10A), a DSV change amount calculator (15) calculates change amounts (?DSVa, ?DSVb) in DSVs of candidate modulated codes (CODEa, CODEb) generated by a modulated code generator (11). A modulated code determinator (13) compares the change amounts (?DSVa, ?DSVb), and determines that the candidate modulated code having a smaller absolute value should be selected as a modulated code (CODE). A modulated code selector (14) selects one of the candidate modulated codes (CODEa, CODEb) which is determined by the modulated code determinator (13), and outputs the selected code as a modulated code (CODE) for source data (DATA).

Abstract: The present invention facilitates data recovery without requiring selection of a sample phase. The data is recovered by sampling a received signal to obtain a number of samples at a number of phases over a given time period referred to as a bit time. The samples are analyzed to determine if a transition has occurred in one or more consecutive phases. Such a transition is also referred to as a data toggle. Generally, one or more toggles in a single bit time indicate one data value (e.g., a zero) whereas no transitions indicate another data value (e.g., a one).

Abstract: A method and apparatus for data coding for high-density recording channels exhibiting low frequency contents is disclosed. Coding is used that satisfies both Running Digital Sum (RDS) and Maximum Transition Run (MTR) properties, which are desirable for achieving high-density recording for recording channels exhibiting low frequency components such as perpendicular magnetic recording channel.

Abstract: An encoding method of recording media is used to speed up the encoding procedure in a recording media. Different conditions of states and paths set in advance during the encoding procedure to simply the actual operation loading for possible paths in the look-ahead calculation, thereby achieving fast encoding. Using the method, the operation of the look-ahead calculation of an exponential growth is greatly reduced to a linear growth.

Abstract: When recording data on a record carrier of the DC content of the data recorded is important in order to allow accurate reproduction of the data. The Digital Sum Value represents the DC content; the Digital Sum Value can be controlled by replacing code words at the output of an encoder by code words that can never occur during encoding. The replacement code word has different parity than the code word it replaces. The resulting stream of code words is subsequent encoded using an NRZI coder, so that the change in parity resulting from replacement code word results in a change of polarity of the NRZI output. The replacement code word can thus be used to change the polarity of the NRZI output to keep the Digital Sum Value low.

Abstract: A scaled input current is produced that substantially matches the full scale input of a CT??ADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.

Abstract: Method and apparatus for time aligning first and second signals. The second signal is modulated by the first signal to provide a third signal. Frequency components of the third signal are then determined, the frequency components being indicative of time alignment between the first and second signals. The method and apparatus is particularly suitable for converting a Non-Return-to-Zero data signal to a Return-to-Zero data signal by modulating the Non-Return-to-Zero data signal with a Return-to-Zero pulse signal. The method and apparatus provides for the Non-Return-to-Zero data signal and the Return-to-Zero pulse signal being correctly time aligned in an automated manner without human intervention.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. The generated output code words are sequentially connected into a sequence which follows run length limiting rules. The run length limiting rules are changed between RLL(1, 7) and RLL(1, 8) in response to auxiliary information to superimpose the auxiliary information on the sequence of the generated output code words.

Abstract: A conversion method for converting a unipolar voltage data stream into a carrier-suppressed return-to-zero (CSRZ) optical data stream includes modulating a continuous optical wave with an encoded nonreturn-to-zero (NRZ) voltage data stream for providing a CSRZ optical data stream of full-width at half-maximum (FWHM) pulse width less than one-half of the transition time of the encoded nonreturn-to-zero (NRZ) voltage data stream between logical states for a reduced pulse width. The modulating circuit is either a duobinary modulator driven with a swing of ±2V? or an optical time domain multiplexed plurality of nonreturn-to-zero (NRZ) modulators with phase shifting and differential encoding.

Abstract: A conversion method for converting a unipolar voltage data stream into a carrier-suppressed return-to-zero (CSRZ) optical data stream includes modulating a continuous optical wave with an encoded nonreturn-to-zero (NRZ) voltage data stream for providing a CSRZ optical data stream of full-width at half-maximum (FWHM) pulse width less than one-half of the transition time of the encoded nonreturn-to-zero (NRZ) voltage data stream between logical states for a reduced pulse-width. The modulating circuit is either a duobinary modulator driven with a swing of ±2V&pgr; or an optical time domain multiplexed plurality of nonreturn-to-zero (NRZ) modulators with phase shifting and differential encoding.

Abstract: An EFM/EFM+ encoding system is adapted to modulate a source symbol sequence into a modulated bit sequence that is further converted to a channel bit sequence, which is to be recorded on a recording medium and which has a cumulative Digital Sum Value (DSV), through NRZI conversion. An apparatus for performing DSV protection in the EFM/EFM+ encoding system includes a DSV calculation unit for calculating the DSV associated with the EFM/EFM+ modulated bit sequence, and a decision unit for adjusting at least a bit in the modulated bit sequence according to the result calculated by the DSV calculation unit such that the channel bit sequence from the NRZI conversion of the adjusted modulated bit sequence accumulates a relatively small DSV. A method of using the EFM/EFM+ encoding system to inhibit disc copying is also disclosed.

Abstract: The present invention relates to a data conversion method for providing efficient conversion between data of different unit lengths, a method for obtaining waveform information from a square wave using the same, and a method for generating the square wave from the waveform information using the same. According to the data conversion method of the present invention, there is an advantage in that data compression and data decompression can be readily and efficiently performed. Further, according to the method of obtaining the waveform information and the method of generating the square wave using the data conversion method of the present invention, there are advantages in that the waveform information can be efficiently generated from the square wave signal and the square wave signal can be efficiently generated from data on the waveform information of the square wave.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. Two redundant bits are added to every prescribed number of the successive generated output code words for digital-sum-variation control. The generated output code words and the added redundant bits are sequentially connected into a redundant-bit-added output-code-word sequence which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number equal to 9.

Abstract: A method and apparatus for electrically converting a NRZ signal into a RZ signal. A NRZ signal is summed with a phase-aligned clock signal. The resultant summed signal is then passed through a biased PHEMT transistor which has highly non-linear characteristics. The transistor is biased such that portions of the summed signal below a predetermined level are clipped resulting in an inverted RZ format signal equivalent to the received NRZ signal.

Abstract: An EFM/EFM+ encoding system is adapted to modulate a source symbol sequence into a modulated bit sequence that is further converted to a channel bit sequence, which is to be recorded on a recording medium and which has a cumulative Digital Sum Value (DSV), through NRZI conversion. An apparatus for performing DSV protection in the EFM/EFM+ encoding system includes a DSV calculation unit for calculating the DSV associated with the EFM/EFM+ modulated bit sequence, and a decision unit for adjusting at least a bit in the modulated bit sequence according to the result calculated by the DSV calculation unit such that the channel bit sequence from the NRZI conversion of the adjusted modulated bit sequence accumulates a relatively small DSV. A method of using the EFM/EFM+ encoding system to inhibit disc copying is also disclosed.

Abstract: The present invention is a device for converting an RZ signal into a NRZ signal which contains an optical bistable device (5), where an output level of this device passing from a low level to a high level when an input power level crosses in an upward direction a first threshold, and returning to a low level when an input level crosses in a downward direction a second threshold below the first, the output (7) of the bistable (5) carrying the NRZ signal, and a device (2) for converting the RZ signal into a control signal of an output logic level of the optical bistable device (5) receiving the RZ signal, and delivering the control signal of the optical bistable device (5), this signal having a level above the first threshold when the RZ signal passes to 1 and which becomes lower at the second threshold only if the RZ signal passes to 0 and stays there for more than one bit time.

Abstract: An auto-zeroed quantizer that has a unit delay characteristic employs switched capacitor techniques to adjust the input common-mode voltage to a proper common-mode voltage for the quantizer. A feed-forward auto-zero scheme is used to initialize the apparatus during an initialization phase. After the initialization phase, a differential input signal is amplified to provide a differential amplified signal. A positive feedback circuit is subsequently activated to increase the difference in the differential amplified signal until the difference saturates at a logic level. The logic level decision is stored in a memory circuit such as a latch. The unit delay quantizer may be utilized in a converter circuit such as a &Dgr;&Sgr; modulator.

Abstract: Return-to-zero (RZ) formatted data is recovered and transmitted using non-return-to-zero (NRZ) devices. A NRZ clock and data recovery device (CDR) interprets the clock rate of a RZ formatted signal as twice its actual clock rate. Due to this interpretation, extra zeroes will be inserted in the data stream. The extra zeroes introduced by the NRZ interpretation of the data are discarded, and the interpreted clock rate is divided resulting in preserving the values of the original data stream of the RZ formatted signal. A NRZ encoded data stream at a specific clock rate is processed so that when the data stream is transmitted to a recipient expecting RZ formatted data, the recipient interprets the correct data.

Abstract: A method and apparatus for electrically converting a NRZ signal into a RZ signal. A NRZ signal is summed with a phase-aligned clock signal. The resultant summed signal is then passed through a biased PHEMT transistor which has highly non-linear characteristics. The transistor is biased such that portions of the summed signal below a predetermined level are clipped resulting in an inverted RZ format signal equivalent to the received NRZ signal.

Abstract: A look-up table scheme for performing non-return-to-zero inverted (NRZI) encoding on input data bytes. Also disclosed is a look-up table scheme for performing zero-insertion in data streams that so require. An address is formed from an input data byte and is then used to look-up the corresponding encoded/translated byte.

Abstract: A data-decoding apparatus having bit-detecting section 4. In the apparatus, an RF signal is reproduced from a recording medium and converted to digital data. If the RF signal has a level (amplitude) equal to a comparator level, the bit-detecting section 4 outputs channel-bit data having logic level “0” or “1” in accordance with whether the sum of the amplitudes of the two RF signals respectively preceding and following that RF signal is higher or lower than the comparator level.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. Two redundant bits are added to every prescribed number of the successive generated output code words for digital-sum-variation control. The generated output code words and the added redundant bits are sequentially connected into a redundant-bit-added output-code-word sequence which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number equal to 9.

Abstract: A method and apparatus for recording and reproducing information to and from an optical disk. If the size of a shortest mark is made small, a signal amplitude lowers and errors are likely to occur. In order to overcome this problem, when data of asymmetric codes is written, the length of a write mark is compensated so that the shortest mark and gap have the same length.

Abstract: This invention relates generally to methods and apparatuses for implementing cyclic return to zero techniques for digital to analog (D/A) conversion. Generally, embodiments of the invention disclose techniques for generating low-distortion continuous-time output waveforms in digital-to-analog converters (DACs) wherein the transient errors are not correlated with the DAC input signal, thereby resulting in DACs with significantly reduced nonlinear distortion. In one embodiment, a cyclic return to zero (CRTZ) digital to analog converter (DAC) includes at least two return to zero (RTZ) signal generating circuits, e.g. RTZ sub-DACs, to perform D/A conversion and a cycler, e.g. an RTZ sub-DAC cycler, to cycle between the two RTZ sub-DACs. The RTZ sub-DAC cycler cycles between the two RTZ sub-DACs such that one of the RTZ sub-DACs is active to perform D/A conversion for at least an entire sample period while the other RTZ sub-DAC is inactive.

Abstract: A continuous time delta-sigma analog to digital converter is disclosed. A summing junction receives an input analog signal to be digitized and a feedback signal. A loop filter receives the combined signals from the summing junction, and a course analog to digital converter converts the combined signal to a multi-bit digital number. A sin DAC provides a feedback signal to the summing junction, by reconverting the multi-bit digital signal to an analog signal. The sin DAC produces a linear output signal having a reduced phase jitter, resulting in a lower noise floor for the multi-digital signal. The sin DAC may be an NRZ sin DAC which avoids stringent linearity requirements on the summing junction.

Abstract: A method encodes an input data block with a block encoder. The block encoder is capable of processing consecutive coding blocks whose size has an upper limit which is smaller than the size of the input data block. The method comprises: determining the length of the input data block before encoding any of its data with the block encoder; dividing the input data block to a plurality of segments wherein all segments are of substantially equal size and no segment is larger than the upper limit; and processing each segment with the block encoder. If the last segment is shorter than the remaining segments, fill bits can be added to the last segment such that its length equals that of the remaining segments.

Abstract: An invention for use in electrical or optical communications for generating UNRZ data from URZ data is disclosed. The method of the invention transmits URZ data at the transmitter and receives UNRZ data at the receiver. The invention takes advantage of transmitting URZ data and eliminates the drawbacks of receiving URZ data. The invention also takes advantage of receiving UNRZ data and eliminates the drawbacks of transmitting UNRZ data. The net bandwidth requirement of a communications system implemented according to the method of the invention, with URZ and URZd data transmitted via a transmission medium and converted to UNRZ coding at a receiver location, is the same as that of a system that transmits and receives UNRZ data.

Abstract: A look-up table scheme for performing non-return-to-zero inverted (NRZI) encoding on input data bytes. Also disclosed is a look-up table scheme for performing zero-insertion in data streams that so require. An address is formed from an input data byte and is then used to look-up the corresponding encoded/translated byte.

Abstract: Return-to-zero (RZ) formatted data is recovered and transmitted using non-return-to-zero (NRZ) devices. A NRZ clock and data recovery device (CDR) interprets the clock rate of a RZ formatted signal as twice its actual clock rate. Due to this interpretation, extra zeroes will be inserted in the data stream. The extra zeroes introduced by the NRZ interpretation of the data are discarded, and the interpreted clock rate is divided resulting in preserving the values of the original data stream of the RZ formatted signal. A NRZ encoded data stream at a specific clock rate is processed so that when the data stream is transmitted to a recipient expecting RZ formatted data, the recipient interprets the correct data.