Abstract: Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.

Abstract: A digital-to-analog converter and a digital-to-analog conversion method thereof are provided. The digital-to-analog conversion method includes: converting a digital data signal into an analog data signal in a first cycle according to a clock signal, resetting the analog data signal in a second cycle according to the clock signal and a reset signal corresponding to a first reset level, and compensating for a voltage level of the reset analog data signal in the second cycle according to a second reset level, so that the voltage level of the reset analog data signal is the second reset level. The second reset level is higher or lower than the first reset level.

Abstract: The present disclosure describes aspects of pulse-based writing for magnetic storage media. In some aspects, a pulse-based writer of magnetic storage media determines that a string of data bits having a same polarity corresponds to a magnet longer than a threshold associated with a magnetic media writer. The pulse-based writer inserts, into the string of data bits, a transition to a polarity opposite to the same polarity of the string of data bits. The string of data bits including the inserted transition is then transmitted to the magnetic media writer to cause a write head of the writer to pulse while writing the magnet to magnetic storage media. Various aspects may also implement a control signal to mask a transition or control polarity of the magnetic media writer. By so doing, magnets may be written to the magnetic storage media more efficiently or with less distortion to neighboring tracks.

Abstract: A method of calibrating a clock phase and a voltage offset includes receiving an input data signal that is periodically toggled. A clock phase calibration operation is performed based on an up signal and a down signal, such that phases of a plurality of clock signals are adjusted. The up signal and the down signal are generated based on the input data signal, a reference voltage and the plurality of clock signals. A voltage offset calibration operation is performed based on the up signal, the down signal and a first sample data signal, such that a voltage level of the reference voltage is adjusted. The first sample data signal is generated by sampling the input data signal based on one of the plurality of clock signals. The clock phase calibration operation and the voltage offset calibration operation are performed independently of each other and not to overlap with each other.

Abstract: Disclosed are a shift register unit, a gate driving circuit and a driving method thereof, the shift register unit including: an input sub-circuit configured to provide a trigger signal received by the signal input terminal to the pull-up node; an output sub-circuit configured to output, to the signal output terminal, a pulse signal provided by the first clock signal terminal as a driving signal for scanning a gate line under control of the pull-up node; a reset sub-circuit configured to reset the pull-up node and the signal output terminal under control of the reset terminal; and an input selection sub-circuit configured to select a trigger signal to be provided to the signal input terminal according to voltage levels at first to third control terminals.

Abstract: A first transceiver operable to establish a connection with a second transceiver over a channel. A receiver of the first transceiver maintains communication parameters for the connection with the second transceiver, and processes signals received over the channel according to the communication parameters. The receiver monitors for idle frames from the second transceiver, and begins running of a first idle period in response to detecting a predetermined number of consecutive idle frames. The receiver, during the first idle period, suspends adaptation of the communication parameters. At an end of the first idle period, the receiver receives a first frame from the second transceiver, selectively adapts the communication parameters based on the first frame, and selectively begins running of a second idle period. A transmitter of the first transceiver suspends transmitting frames to the second transceiver during the first idle period and the second idle period.

Abstract: An expurgated pulse position modulation (EPPM) technique can be used to encode information for wireless transmission. Such an EPPM technique can be compatible with a simple receiver architecture, such as including a shift register and pulse position modulation (PPM) decoder. A multi-level EPPM (MEPPM) approach can increase the available symbols in the modulation constellation and can be used to accommodate multiple users or devices concurrently. Interleaving techniques can be used such as to reduce inter-symbol interference. An optical transmitter and an optical receiver can be used, such as including using energy in a visible range of frequencies. In an example, an optical source such as including one or more light emitting diodes can provide visible light for illumination, and the EPPM technique can include using codewords specified to provide a desired dimming level when such codewords are used to intensity modulate the optical source, without perceptible flicker.

Abstract: A method for command processing in a memory controller includes receiving a serial input signal including a series of binary digits, capturing the binary digits at ones of odd locations or even locations of the serial input signal to form a first sub-series, capturing the binary digits at other ones of the odd locations or the even locations of the serial input signal to form a second sub-series, comparing the first and second sub-series, and performing a command represented by the first sub-series, if the first and second sub-series are complementary to each other.

Abstract: Systems and methods are described that include adaptation circuitry for processing a data signal. The adaptation circuitry may include summation node circuitry for processing an error value associated with the data signal. The adaptation circuitry may also include adaptation engine circuitry, coupled to the summation node circuitry, for controlling the operation of the summation node circuitry.

Abstract: A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal.

Abstract: To set an optimum offset voltage and detect an NRZ signal with a very small amplitude. An NRZ signal amplifying device 2 includes: input-side voltage detection means 13 for detecting a high-level voltage and a low-level voltage of an input signal to the main amplifier 12; output-side voltage detection means 14 for detecting the two signals inverted relative to each other; and offset voltage control means 15 for calculating a center voltage between the detected high-level voltage and low-level voltage, setting an offset voltage at which the center voltage is the center of an appropriate input range of the main amplifier 12 to the offset circuit 11, and finely adjusting the offset voltage, such that a voltage difference between the detected two signals inverted relative to each other and a polarity change point is close to 0.

Abstract: In a data carrier (1) which includes receiving means (5) for receiving a modulated carrier signal (MTS) which contains a data signal (DS1) encoded in conformity with an encoding method (MA, PW, MI, RTZ, FSK, PSK), demodulation means (9) for demodulating the received modulated carrier signal (MTS) and for outputting the encoded data signal (DS1) contained therein, decoding means (10, 20) for decoding the encoded data signal (DS1) and for outputting data (D1, D2), and data processing means (11) for processing the data (D1, D2) output by the decoding means (10, 20), the decoding means (10, 20) are provided with at least a first decoding stage (12) and a second decoding stage (13), the first decoding stage (12) being arranged to decode a data signal (DS1) encoded in conformity with a first method (RTZ) whereas the second decoding stage (13) is arranged to decode a data signal (DS1) encoded in conformity with a second method (MI).

Abstract: A method for encoding an input sequence of symbols to produce a bitstream and a method of decoding the bitstream to generate a reconstructed binary sequence. Encoding employs an encoding tree having primary codewords associated with leaf nodes and secondary codewords associated with internal nodes. A flush event may cause output of secondary codewords. A context model is used to select an encoding tree corresponding to an estimated probability at the encoder. The same context model is used by the decoder to select a decoding tree. The decoder interleaves bits from decoded bit sequences associated with different estimated probabilities based on the context model.

Abstract: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is encoded using a Non Return to Zero Inverted (NRZI) code and a 17 Parity Preserve/Prohibit (17PP) code, determining a 17PP modulated bit stream based upon the coded bit stream using a first selected decoding method, and generating a plurality of decisions by processing the 17PP modulated bit stream using a second selected decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in a source information.

Abstract: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is generated by encoding source information using a Non Return to Zero Inverted (NRZI) code, selecting an NRZI decoding method based on one or more parameters associated with noise in the received coded bit stream, and generating a plurality of decisions by processing the received coded bit stream using the selected NRZI decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in the source information.

Abstract: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is encoded using a Non Return to Zero Inverted (NRZI) code and a 17 Parity Preserve/Prohibit (17PP) code, determining a 17PP modulated bit stream based upon the coded bit stream using a first selected decoding method, and generating a plurality of decisions by processing the 17PP modulated bit stream using a second selected decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in a source information.

Abstract: A method of decoding is presented. The method includes the steps of receiving a coded bit stream that is generated by encoding source information using a Non Return to Zero Inverted (NRZI) code, selecting an NRZI decoding method based on one or more parameters associated with noise in the received coded bit stream, and generating a plurality of decisions by processing the received coded bit stream using the selected NRZI decoding method, wherein the received coded bit stream comprises a plurality of coded bits, and the plurality of decisions are estimates of a plurality of source bits in the source information.

Abstract: There is provided an information processing device, including a preamble detection portion, a sync detection portion, a storage portion, a storage control portion, a delay time imparting portion, a bias computation portion, a half sampling portion, an adaptive equalization portion an equalization performance determination portion that compares equalization errors for each one of the sync portion candidates for which the training equalization has been performed by the adaptive equalization portion, and that sets the candidate position with the least error, and a binary determination portion that decodes the Manchester code into NRZ code by subjecting to binary determination the received signal that has been adaptively equalized by the adaptive equalization portion. The storage control portion reads the received signal from the storage portion based on information about the candidate position with the least error that has been set by the equalization performance determination portion.

Abstract: An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion.

Abstract: A 4B5B encoder converts an inputted 4-bit data into a pattern of a 5-bit data in which (i) the number of bits of consecutive “0” data values is permitted to be maximum two, and, simultaneously, (ii) maximum one bit of head end two bits is permitted to have a “0” data value and maximum one bit of tail end two bits is permitted to have a “0” data value. A 5N-bit command encoder converts a command into a command pattern in which the number of bits contained in consecutive “0” data values is permitted to be maximum two. The data after the conversion and the command after the conversion are converted into NRZI codes by an NRZI encoder.

Abstract: A data demodulator includes: a conversion means for converting an RLL code obtained by converting data in which information bits including specific bits are inserted at fixed intervals which is included in an input signal in accordance with a modulation table having variable-length conversion rules into data in accordance with a demodulation table corresponding to the modulation table; a determination means for determining control segments for performing calculation intended by the information bits from the converted data; a calculation means for executing calculation intended by the specific bit inserted in the control segment different from a calculation target with respect to the data of the control segment as the calculation target; and a correction output means for selecting one of first data converted by the conversion means and second data obtained by converting the RLL code of the input signal corrected based on the calculation result in accordance with the demodulation table and outputting the data.

Abstract: A method and system for encoding a segment of user data words into a segment of code words so that both modulation constraints and a predetermined parity-check constraint are satisfied. Each segment of the user data is partitioned into several data words, and encoded separately by first and second types of component code, which are referred to as the normal constrained code and the parity-related constrained code, respectively. The parity-check constraint over the combined code word is achieved by concatenating the sequence of normal constrained code words with a specific parity-related constrained code word chosen from a candidate code word set. Both the component codes are finite-state constrained codes, which are designed to have rates close to the Shannon capacity. Furthermore, they are based on the same finite state machine (FSM), which enables them to be connected seamlessly, without violating the modulation constraints.

Abstract: An improved RFID Tag, Interrogator, and system wherein at least one tag modulates a radio frequency signal by modulated backscatter operations.

Abstract: The present invention provides a convolutional line coding method, including: constructing a sequence set, where the length of each sequence in the sequence set is n bits; selecting a balanced sequence in the sequence set, and obtaining source data of n?1 bits corresponding to the balanced sequence; performing Hamming distance detection for an unbalanced sequence in the sequence set to obtain source data of n?1 bits corresponding to the unbalanced sequence; sorting the balanced sequence and the unbalanced sequence according to an operation difference value, and generating a code table, where the source data of n?1 bits correspond to the sequence of n bits, and the code table is designed for line coding; and at time of encoding the source data of n?1 bits, obtaining a coding result of n bits according to a mapping relation in the code table.

Abstract: A gating logic receives a non-return-to-zero (NRZ) input signal and couples the NRZ input signal as an NRZ output signal when operating in a NRZ mode of operation and converts the NRZ input signal to a return-to-zero (RZ) output signal when operating in a RZ mode of operation. A circuit coupled to the gating logic receives a clock signal and couples the clock signal to the gating logic to convert the NRZ input signal to the RZ output signal in the RZ mode of operation. In the NRZ mode of operation, the circuit decouples the clock signal and places a predetermined signal state at the gating logic to pass through the NRZ input signal as the NRZ output signal. The circuit receives a select signal to select between the NRZ and RZ modes of operation and the NRZ and RZ modes are obtained by controlling the clock signal to the gating logic.

Abstract: According to one embodiment, a run length limiter includes a searcher configured to search a received digital data for a specific symbol, an operator configured to operate an exclusive OR operation of the specific symbol and the digital data, and an output module configured to output the exclusive OR operated digital data with the specific symbol.

Abstract: Provided is an encoding apparatus including an encoding unit that generates encoded data formed from a sequence of base-k data in which m pieces (m<n) of base-k symbols are combined, by converting input binary data in units of n bits based on a specific conversion rule that associates n-bit binary data and the base-k data. In case a DC balance of the base-k data obtained after conversion has a polarity, the encoding unit controls a polarity of a symbol included in the base-k data obtained after conversion such that the polarity of the DC balance of the base-k data obtained after conversion is different from a polarity of a DC balance of a sequence of base-k data previous to the base-k data obtained after conversion.

Abstract: A coder is fed with pre-coded data such that the absolute value of the RDS of the code words as produced by the coder is limited. This is achieved by ensuring that in a group of 2 code words the RDS of the first code word is compensated by the RDS of the second conde word. The RDS at the end of the second code word is then zero and the excursions of the RDS from the start of the first code word until the end of the second code word are limited because there are only a limited number of bits that can contribute to an increase of the absolute value of the RDS. This principle can easily be applied to the 17PP coder.

Abstract: A method for modulating a video input signal received into a modulation circuit is disclosed. A first step of the method generally comprises (A) during a first modulation pass, generating (i) a primary frame by inserting a plurality of primary synchronization codes into the video input signal, (ii) a secondary frame by inserting a plurality of secondary synchronization codes into the video input signal, (iii) a plurality of first values and a first digital sum value both for the primary frame and (iv) a plurality of second values and a second digital sum value both for the secondary frame. A second step of the method generally comprises (B) during a second modulation pass, generating a video output signal presented from the modulation circuit by modulating the video input signal using one set of (i) the first values and (ii) the second values as determined by the first digital sum value relative to the second digital sum value.

Abstract: A physical layer device includes a converter module to convert input data having a first predetermined number of bits into output data having a second predetermined number of bits. A scrambler module is operable to be activated and deactivated. The scrambler module receives the output data having the second predetermined number of bits. An encoding module modulates the output of the scrambler module in accordance with one of a plurality of modulation types and generates an encoded output signal having an output level. The encoding module is operable to vary the output levels of the encoded output signal.

Abstract: A run-length limited (RLL) encoder includes a block detection module that receives a data block that includes N portions and generates N?1 coding bits indicating whether corresponding ones of N?1 of the N portions of the data block include one of all ones and all zeros, where N is an integer greater than two. A mapping module generates an RLL codeword including N portions comprising bits that are determined by a first mapping table, a second mapping table, bits of the data block and the N?1 coding bits.

Abstract: An encoding technique is disclosed for mitigating against the effects of Intersymbol Interference (ISI) and DC creep by forcing data transitions at least every two data bits. Two consecutive bits of data in the original non-return-to-zero (NRZ) data stream are grouped and are converted by an encoding circuit into two new consecutive data bits of the same duration as the original bits. The new encoded bits in each group will necessarily transition between two of three possible data states, and specifically will transition between ‘?1’ and ‘0’ logic states, or ‘+1’ and ‘0’ logic states. Pursuant to this encoding scheme, no more than two consecutive encoded bits will ever be of the same logic state, which prevents any particular data state from predominating and causing DC creep.

Abstract: Devices and methods, record carrier and signal for embedding, extracting, carrying and representing secondary signal such as a copy protection signal embedded in a primary signal such as a blu ray disc signal modulated by a 17PP RMTR runlength limited modulation code. Each frame comprises a frame sync patterns followed by DC control blocks each including a DC control bit. Two modulation tables are used. Each bit of the secondary signal is represented by a relationship between the polarity of the frame sync signal and the values of the DC control bits in a fashion which complies with the constraints of the modulation code and the DC control algorithm.

Abstract: A demodulation table for converting variable length code (d, k; m, n; r) is provided. The variable length code has a maximum constraint length r>1, has a minimum run of d (d>0), has a maximum run of k, and a basic codeword length of n bits into data having a basic data length of m bits. The demodulation table includes: a basic table for converting code patterns composed of basic codes having a basic codeword length of n bits into data patterns composed of basic data having a basic data length of m bits; and a substitution table for converting code patterns of a plurality of different minimum run successive occurrence limiting patterns determined so as to limit successive occurrences of the minimum run to a maximum of N (N>1) times into a corresponding identical data pattern.

Abstract: A physical layer device comprises a mode selector that selects a mode. A clock selects a clock frequency from T clock frequencies based on the mode. A converter module selects one of N mapping functions based on the mode and converts an n-bit input to an m-bit output based on the selected one of the N mapping functions. A scrambler module scrambles the m-bit output or passes the m-bit output unchanged based on the mode. An encoding module modulates the m-bit output based on the selected clock frequency and one of M modulation modes selected based on the mode, where T, n, m, N and M are integers greater than one and n is not equal to m.

Abstract: A run-length limited (RLL) encoder includes a problematic-block detection module that receives a data block and that generates coding bits that indicate whether at least one of N portions of the data block include one of all ones and all zeros, where N is an integer greater than one. A mapping module generates an RLL codeword based on the data block and the coding bits. The RLL codeword includes N portions. One of the N portions of the RLL codeword is populated with the coding bits. At least another one of the remaining portions of the RLL codeword is populated with at least part of the data from one of the N portions of the data block that corresponds with the one of the N portions of the RLL codeword.

Abstract: A method of generating codewords that conform to a run length limited (RLL) constraint represented by (d, k, a, b), where d is a minimum run length of a codeword, k is a maximum run length of the codeword, a is a length of source data, and b is a length of the codeword. The method includes generating codewords conforming to the RLL(d, k) constraint, and removing codewords in which a relatively long T and a relatively short T are placed adjacent to each other from the generated codewords.

Abstract: Techniques to modify bias levels of a limiting amplifier based on a transition measurement and measurements before and after the transition.

Abstract: A system and method for decoding a received data stream is disclosed. The method includes detecting first and second data transitions of a received data stream. Each of the data transitions is of a first transition type (e.g. rising or falling transition). The time interval between the data transitions is measured, and a logic value of a data bit encoded in the data stream is decoded based on the measured time interval. By decoding the data stream based on the time intervals between data transitions, the number of decoding errors due to timing changes in the data stream (such as changes due to drift or jitter in the data stream) is reduced.

Abstract: A digital modulation apparatus capable of generating a modulated code so that binary slice is correctly performed when reproducing is provided. To achieve this, in a digital modulation apparatus (10A), a DSV change amount calculator (15) calculates change amounts (?DSVa, ?DSVb) in DSVs of candidate modulated codes (CODEa, CODEb) generated by a modulated code generator (11). A modulated code determinator (13) compares the change amounts (?DSVa, ?DSVb), and determines that the candidate modulated code having a smaller absolute value should be selected as a modulated code (CODE). A modulated code selector (14) selects one of the candidate modulated codes (CODEa, CODEb) which is determined by the modulated code determinator (13), and outputs the selected code as a modulated code (CODE) for source data (DATA).

Abstract: A method, apparatus and computer program for decoding a data stream. The method comprises the steps of acquiring an analog data signal, determining an initial polarity of the analog data signal, determining a threshold transition level, determining a plurality of transition edges where the analog data signal crosses the threshold transition level, and determining the number of unit intervals between each pair of transition edges. A binary value is assigned to each of the unit intervals, and the binary values are displayed to a user.

Abstract: The present invention relates to an encoding apparatus and a corresponding method for two-dimensionally encoding user data of a user data stream into channel data of a channel data stream along a two-dimensional channel strip of at least two bit rows one-dimensionally evolving along a first direction and being aligned with each other along a second direction, said two directions constituting a two-dimensional lattice of bit positions. According to the invention the apparatus comprises a modulation code encoder for modulation code encoding said user data into said channel data according to a two-dimensional modulation code being adapted to prevent predetermined worst case patterns of channel data in said channel data stream. The worst-case patterns are typical for high-density two-dimensional optical storage channels.

Abstract: The present invention facilitates data recovery without requiring selection of a sample phase. The data is recovered by sampling a received signal to obtain a number of samples at a number of phases over a given time period referred to as a bit time. The samples are analyzed to determine if a transition has occurred in one or more consecutive phases. Such a transition is also referred to as a data toggle. Generally, one or more toggles in a single bit time indicate one data value (e.g., a zero) whereas no transitions indicate another data value (e.g., a one).

Abstract: The present invention pertains to a modulation apparatus and method in which the modulation apparatus is realized with a simple circuit structure and is easily applicable to other systems. A pattern conversion unit 32 converts data having a basic data length of 2 bits supplied from a DSV control bit determination and insertion unit 31 into a variable-length code having a basic code length of 3 bits in accordance with a conversion table. A minimum-run-length limitation code detection unit 33 detects, from a data sequence containing a DSV control bit, the position of minimum runs consecutive from a channel bit string converted by the pattern conversion unit 32. A consecutive-minimum-run replacement unit 34 replaces a predetermined portion of the channel bit string supplied from the pattern conversion unit 32 for a predetermined pattern based on the position information supplied from the minimum-run-length limitation code detection unit 33, and limits the minimum run length to a predetermined number or less.

Abstract: A method and apparatus for data encoding such as 3 to 4 encoding (base64, uuencode etc.) is provided. Bytes of data to be encoded having negative values are made positive while preserving the information to be encoded. The positive values may be manipulated by addition (e.g. to a common store) and bit shifting to efficiently obtain encoded data such as by indexing an encoding alphabet.

Abstract: A physical layer device for a network device comprises a converter module that selectively converts an n-bit input to an m-bit output based on first and second mapping functions. A scrambler module selectively scrambles the m-bit output. An encoding module receives the m-bit output from the scrambler module and selectively maps the m-bit output based on the first mapping function to X level output signals and the m-bit output based on the second mapping function to Y level output signals, where X and Y are integers greater than one and X is different than Y.

Abstract: A 6-bit output code word is generated in response to every 4-bit input code word by referring to a set of encoding tables. The encoding tables contain output code words assigned to input code words, and contain encoding-table designation information accompanying each output code word. The encoding-table designation information designates an encoding table among the encoding tables which is used next to generate an output code word immediately following the output code word accompanied with the encoding-table designation information. The generated output code words are sequentially connected into a sequence of the generated output code words which follows predetermined run length limiting rules (1, k)RLL, where “k” denotes a predetermined natural number between 7 and 12.

Abstract: A transmitter of digital data includes a modulator with an input for a carrier signal and an input for a first stream of control symbols. The modulator modulates the carrier signal with a second stream of symbols produced by the modulator. Each symbol of the second stream has a value that corresponds to a sum of the present control symbol and the last K first symbols of the first stream. The integer K is greater than one.

Abstract: A method and apparatus for data coding for high-density recording channels exhibiting low frequency contents is disclosed. Coding is used that satisfies both Running Digital Sum (RDS) and Maximum Transition Run (MTR) properties, which are desirable for achieving high-density recording for recording channels exhibiting low frequency components such as perpendicular magnetic recording channel.

Abstract: A physical layer device for a network device comprises a converter module that selectively converts an n-bit input to an m-bit output based on first and second mapping functions. A scrambler module selectively scrambles the m-bit output. An encoding module receives the m-bit output from the scrambler module and selectively maps the m-bit output based on the first mapping function to three level output signals and the m-bit output based on the second mapping function to four level output signals.