Abstract: Apparatuses, systems, and methods for a system on chip (SoC) replacement mode. A memory device may be coupled to a SoC which may act as a controller of the memory. Commands and addresses may be sent along a command/address (CA) bus to a first decoder of the memory. The first decoder may use a first reference voltage to determine a value of signals along the CA bus. One of the pins of the CA bus may be coupled to a second decoder which may use a different second reference voltage. When the voltage on the pin exceeds the second reference voltage, the memory device may enter a SoC replacement mode, in which the memory may take various actions to preserve data integrity, while a new SoC comes online.

Abstract: A method for delivering media content over a network includes transcoding the media content to generate multiple copies of the media content, each of the multiple copies having a different destination type or a different source type or both, storing the multiple copies in a cache, receiving requests for the media content, and selecting and delivering a copy of one of the multiple copies in response to each of the requests. A further method for providing media content transcoding services includes fetching media content, selecting one of multiple transcoders for transcoding from multiple source types to multiple destination types, wherein the one transcoder is selected based at least on the destination type, sending the media content to the selected transcoder, transcoding the media content to the destination type, thereby generating transcoded media content, and transmitting the transcoded media content.

Abstract: In one aspect, methods and systems for variable-block length encoding of data, such as an inverted index for a file are disclosed. These methods and systems provide for relatively fast encoding and decoding, while also providing for compact storage. Other aspects include a nearly 1:1 inverted index comprising a position vector and a data store, wherein values that have a unique location mapping are represented directly in the position vector, while for 1:n values (n>1), the position vector can include a pointer, and potentially some portion of information that would typically be stored in the data area, in order to fully use fixed width portions of the position vector (where a maximum pointer size is smaller than a maximum location identifier size).

Abstract: An information processing device is provided that includes a signal receiving portion, an absolute value conversion portion, and an input data decoding portion. The signal receiving portion receives a signal that is encoded such that mutually distinct first and second bit values are respectively expressed by pluralities of mutually distinct first amplitude values and second amplitude values, the first and second bit values also being encoded such that the same amplitude value does not occur twice in succession and such that the polarities of the amplitude values are inverted with each cycle. The absolute value conversion portion converts into absolute values the amplitude values of the signal that has been received by the signal receiving portion. The input data decoding portion decodes the first and second bit values based on the amplitude values in the signal that have been converted into absolute values by the absolute value conversion portion.

Abstract: A method for coding information in an electronic circuit and an electronic circuit for coding information uses at least two electrically coupled signal paths (X0, X1). Cross-talk between two electrically coupled signal paths (X0, X1) can be utilized to perform logical computation. A signal is propagating on two signal paths (X0, X1) in the form of either rising or falling transitions. The relative delay between the transitions on the two paths (X0, X1) determines the logic value of the output signal (X) to be produced. If the signal on the first paths (X0) propagates faster than the signal on the second path (X1), an output signal (X) having a first logic value is produced. If the signal on the second path (X1) propagates faster than the signal on the first path (X0). an output signal (X) having a second logic value is produced.

Abstract: The multilevel data encoding and modulation technique uses a pair of complementary logic sets. In its most basic form, the sets are binary sets each containing a line level for a logical one and a line level for a logical zero for a total of four logic levels. The encoding technique requires a polar change in the line level after every bit. An optional fifth level may be used in order to skew the frequency or to enable automatic gain control circuitry to ensure consistent level discrimination. The encoding technique may be used in a bipolar device, or a bias level may be applied to the signal for unipolar transmission. The encoding technique involves inverting the polarity of alternating bits, filtering out all odd harmonics, transmitting and receiving the waveform, and decoding the demodulated waveform by comparing the absolute value of the half-cycle peak-to-peak voltage gain to a predetermined table.

Abstract: The present invention relates to a method for coding a data stream, in which the digital sum value of the coded data stream should be close to zero and two alternative code words can be used for the coding at least for some of the possible data values. It is the object of the invention to propose a method for coding a data stream which provides for simple coding of the data stream while at the same time ensuring a digital sum value close to zero. According to the invention, the object is achieved by a method in which the digital sum value of the coded data stream is determined, this value is compared with a first or a second boundary value in dependence on the polarity of the coded data stream and a received data value is coded by a first or a second code word belonging to the respective boundary value in dependence on the result of the comparison.

Abstract: A data-entry device having manually operable input means arranged in zones for operation by corresponding fingers of a user. The device includes means for color coding such that each zone is assigned a color and successive zones display colors ordered according to their relative positions within a spectrum-ordered color pattern. In one embodiment the device includes a keyboard, such as for a computer or typewriter, wherein the keys of the keyboard are color-coded according to a spectrum-ordered color pattern. The invention also provides a method of color coding a data-entry device.

Abstract: A CMI coding method, a CMI decoding method, a CMI coding circuit, and a CMI decoding circuit which do not adversely affect a main signal to be CMI-coded and which allow a high-speed asynchronous signal to be always transmitted by Coding Rule Violation, with a simple procedure and a simple hardware structure are provided. A CMI coding method is used in which an asynchronous signal is superposed on a main signal with the use of only CRV0 as CRV. In addition, when the main signal is replaced with CRV0 for a signal to be superposed, since the main signal cannot be transmitted, the CMI coding method is configured such that two bits of the main signal, which should be originally transmitted in a time slot (CRV-indication time slot) in which CRV0 is to be disposed and in the next time slot thereof, are two-bit-coded according to a predetermined rule, and the two-bit code is transmitted by the use of the first half and the second half of the next time slot (crammed main-signal time slot).

Abstract: A CMI coding method, a CMI decoding method, a CMI coding circuit, and a CMI decoding circuit which do not adversely affect a main signal to be CMI-coded and which allow a high-speed asynchronous signal to be always transmitted by Coding Rule Violation, with a simple procedure and a simple hardware structure are provided. A CMI coding method is used in which an asynchronous signal is superposed on a main signal with the use of only CRV0 as CRV. In addition, when the main signal is replaced with CRV0 for a signal to be superposed, since the main signal cannot be transmitted, the CMI coding method is configured such that two bits of the main signal, which should be originally transmitted in a time slot (CRV-indication time slot) in which CRV0 is to be disposed and in the next time slot thereof, are two-bit-coded according to a predetermined rule, and the two-bit code is transmitted by the use of the first half and the second half of the next time slot (crammed main-signal time slot).

Abstract: A circuit system suitable for codifying NRZ type binary signals into CMI type binary signals includes a plurality of bistable means, an EXOR type logical gate, a presynchronization device and a combinatory logic device capable of creating a CMI type binary signal by codifying with an identical circuit path the “1” bits and “0” bits, sequence of bit present in the NRZ type binary signals.

Abstract: A circuit system suitable for codifying NRZ type binary signals into CMI type binary signals includes a plurality of bistable means, an EXOR type logical gate, a presynchronization device and a combinatory logic device capable of creating a CMI type binary signal by codifying with an identical circuit path the “1” bits and “0” bits, sequence of bit present in the NRZ type binary signals.

Abstract: A system comprises an encoder, a precoder, a PRML channel, a detector, and a decoder. An input signal is received by the encoder. The encoder generates a code string by adding one or more bits and outputs the code string to the precoder. The encoder applies encoding such that the code string after passing through the precoder has a Hamming distance greater than one to eliminate error events with a small distance at the output of the PRML channel. The present invention also provides codes that after precoding have Hamming distance of 2 and 0 mod 3 number of ones. These codes when used over a PRML channel in an interleaved manner preclude +/-( . . . 010-10 . . . ) error events and error events +/-( . . . 01000-10 . . . ). The code string also has a predetermined minimum number of ones at the output of the PRML channel to help derive a clock from the input signal.

Abstract: A binary data encoding and decoding technique that alternates between starting polarities of a signal for both each occurrence of a binary 1 and each occurrence of two or more consecutive binary 0's. To encode a binary 1, the signal is one polarity for one-half of a bit interval and then the other polarity for the other half of the bit interval. To encode a binary 0, the signal remains at a zero level, unless there are two or more consecutive binary 0's, in which case the signal will be one polarity for the second half of the first binary 0 bit interval, the other polarity for the first half of the second binary 0 bit interval, and repeat this waveform for every for every two adjacent binary 0's. Decoding occurs by examination of either the signal level as compared to predetermined cut-levels, or the time equivalent distance between the peaks.

Abstract: An 8.fwdarw.10 modulator stores a conversion table, and, when receiving 8-bit data as an address, outputs 10-bit data stored at the received address as a modulated code. The conversion table of the 8.fwdarw.10 modulator is constructed such that each NRZI-represented 10-bit data includes at least one "0.

Abstract: A Coded Marked Inversion (CMI) encoding circuit having a completely synchronous and digital implementation for encoding a stream of digital data in non-return-to-zero (NRZ) format into the CMI format. The encoding circuit includes a clock for providing a clock signal having a certain period, an input circuit for obtaining two samples of the NRZ data during each clock period, and a state machine which, in response to the two samples of the NRZ data, produces CMI encoded data. In a more advanced implementation, the encoding circuit includes error encoding circuitry for detecting errors in the incoming samples of NRZ data. The encoding circuit then outputs data indicative of the rate at which errors are received.

Abstract: Loop Performance Monitoring (LPM) for DDS loops is described. Even though DDS loops have Intentional Bipolar Violations (BPVs), a Loop Coding Violations (LCVs) detection strategy based on further processing of BPVs is described. By monitoring LCVs a local loop terminating device can determine Bit Error Rate (BER).A system is described by which an Office Channel Unit (OCU) can process LCV information to determine signal quality of the signal over the incoming local loop. If the signal quality falls below a certain threshold, the OCU can cut the loop off from the DDS circuit and send control codes into the network.A system is also described where a Network Interface Unit (NIU) with the LPM system communicates incoming LCV information to the OCU using low speed signalling over the simplex path between the transmit and receive pairs. The OCU monitors incoming LCVs as well, and thus has the information necessary to determine bi-directional BER performance.

Abstract: Loop Performance Monitoring (LPM) for DDS loops is described. Even though DDS loops have Intentional Bipolar Violations (BPVs), a Loop Coding Violations (LCVs) detection strategy based on further processing of BPVs is described. By monitoring LCVs a local loop terminating device can determine Bit Error Rate (BER).A system is described by which an Office Channel Unit (OCU) can process LCV information to determine signal quality of the signal over the incoming local loop. If the signal quality falls below a certain threshold, the OCU can cut the loop off from the DDS circuit and send control codes into the network.A system is also described where a Network Interface Unit (NIU) with the LPM system communicates incoming LCV information to the OCU using low speed signalling over the simplex path between the transmit and receive pairs. The OCU monitors incoming LCVs as well, and thus has the information necessary to determine bi-directional BER performance.

Abstract: A phase comparing and CMI/NRZ decoding apparatus for accomplishing bit synchronization of CMI data by producing rising transition or falling transition of the clock pulse at the center of unit bit interval of incoming CMI data, by use of the clock pulse having a period equivalent to 2 unit bit intervals of CMI data, and for realizing stable decoding of CMI data to NRZ data. This apparatus is implemented by means of a data output means 2, a clock pulse generating means 1 for generating in-phase and inverse-phase pulses, a inter-transitions time interval information output means 3 for outputting information about line interval between the data transition and the clock pulse transition, a reference pulse generating means 4, a falling transition detecting and 3-step half-period shifting means 6, a rising transition detecting and 2-step half-period shifting means 5, a CMI/NRZ decoding circuit 7 and a code violation detecting means 8.

Abstract: A novel encoding method which facilitates handling at the time of demodulation (decoding) and is capable of further alleviating a burden imposed on a demodulation (decoding) circuit. When an input NRZ code signal is at, for instance, a logical "0" level during a given unit bit time, encoding is effected to obtain a signal having the same form as that of a CMI code such that the signal is set to a logical "1" level in correspondence with a first half of the unit bit time, and to the logical "0" level in correspondence with a second half thereof. Similarly, when the input NRZ code signal is at the logical "1" level during a given unit bit time, encoding is effected to obtain a signal such that the signal is unfailingly set to the logical "1" level during its initial bit time, and thereafter only during a bit time when the NRZ code signal is at the logical "1" level during the unit bit time, the logical "1" level and the logical "0" level are alternately repeated for each unit bit time.

Abstract: In a system wherein a main channel of data is transmitted between two stations by means of an optical waveguide, an additional optical channel may be transmitted. Bits of the additional optical channel are inserted into the main channel at a transcoder in the transmitting station in place of bits of the main channel at defined spacings, known to the transcoder of the receiving station, with a bit rate lower than that of the main channel. The inserted bits are removed from the optical main channel at the receiving station. The bits of the additional optical channel inserted into the main channel are double bits that are identical to a forbidden bit combination that results during the recoding of an electrical AMI code into an optical CMI code. In the receiving station, the double bits of the main channel replaced by the bits of the additional optical channel are recovered by using sequential logic and memory to apply the fixed rules of the electrical AMI code.

Abstract: A block encoded main signal and a balanced block encoded auxiliary signal are combined on a transmission path. The combined signal includes at least one block of encoded main channel signal alternating with one bit of the auxiliary channel signal. The block code for the auxiliary channel is simpler than the block code for the main channel.

Abstract: The apparatus converts an AMI signal into three unipolar signals by selectively amplifying the AMI signals so that higher frequency components are amplified greater than lower components and then comparing the AMI signal with a positive and negative threshold to provide a first unipolar signal having information relating to positive levels of said AMI signal, a second unipolar signal having information relating to negative levels of said AMI signal and a Or gate for combining said first and second signals to provide a third signal having information related to both positive and negative levels.

Abstract: A circuit having a completely synchronous and digital implementation for encoding a stream of digital data (NRZ form) into the coded marked inversion (CMI) format. The circuit includes a state machine having a predetermined number of defined legal and illegal states, an illegal state detection circuit, and an output circuit. When the state machine enters an illegal state because of, for example, the effects of noise or distortion on the digital data signal, the illegal state detection circuit forces the state machine back into a legal state.

Abstract: A NRZ/CMI (II) code converter comprising a D-type flip-flop for retiming a series of NRZ data bits received thereto with a clock synchronized therewith, an OR-gate connected to said one output of the D-type flip-flop to compose space bits of a series of said received NRZ data bits and a transmitted clock, and a delay element connected to the output of said OR-gate. The converter also comprises another OR gate connected to a negative output of said D-type flip-flop and another D-type flip-flop having a clock input connected to the output of said OR-gate. These elements function to compose mark bits of a series of the NRZ data bits with clock pulses and to generate two-divided alternative mark bits.An exclusive OR-gate is connected to the output of said another OR-gate and the output of said another D-type flip-flop.

Abstract: A coded transmission system wherein each bit of transmitted data having a logical value is coded depending on a coded result of a preceding bit. The coded transmission system contains a sender-side apparatus, a transmission line, and a receiver-side apparatus. In the sender-side apparatus, a resetting bit and a message are generated; a code of a bit last transmitted which is necessary to code a bit which is to be transmitted next is memorized in a first preceding code memorizing circuit; and the content of the first preceding code memorizing circuit is reset to an initial code responding to the resetting bit. A coding circuit receives the resetting bit and the message, codes each bit of the message in accordance with a predetermined coding rule and the content of the first preceding code memorizing circuit, and codes the resetting bit to a predetermined resetting code which is different from the codes used in the coding of the message.

Abstract: Encoding and decoding circuits, utilizing high speed ECL-like logic, simultaneously transmit and receive multiple binary signals via a single I/O pin.

Abstract: A coding method uses a pseudo-logarithmic compression law approximated by a straight line segment curve. Its code word on n+1 binary digits, where n is a positive invariant integer, has a lefthand part made up of a variable number p of binary digits having the same value (1) corresponding to the rank number of the segment concerned in the compression law and a righthand part, which may be absent, determining the interval within the segment concerned.

Abstract: A Simple Code encoder/decoder converts a ternary, or bipolar, signal having a strong clock component into a binary signal while maintaining the strong clock component for processing with digital equipment. The Simple Code is high for each positive value of the bipolar signal, low for each negative value of the bipolar signal, and alternates high/low for each zero value of the bipolar signal. The encoder uses an extractor circuit to generate a +PULSE signal, a -PULSE signal and a CLOCK signal from the bipolar signal. The +PULSE and CLOCK signals are combined to produce an intermediate binary signal, and the intermediate binary signal is combined with the -PULSE signal to produce the Simple Code binary signal. The decoder extracts the CLOCK signal from the Simple Code binary signal and uses the CLOCK signal to generate positive and negative pulse signals corresponding to the highs and lows of the binary signal of a duration equal to the period of the CLOCK signal.

Abstract: Decoding unit for CMI-encoded input signals. A signal having 0/1 transitions is first derived from a signal. A 0/1 transition occurs in a CMI-signal as the result of encoding a binary zero or two consecutive binary ones. In the latter case the 0/1 transition is preceded two bits earlier by a 1/0 transition. By deriving a signal having 1/0 transitions, delaying this signal by two bit intervals and by comparing it to the first signal, the 0/1 transitions corresponding to a binary zero are then accurately detected. The resultant signal can easily be extended by one bit period, so that independent of any phase inversions of the read clock, the appropriate binary information is always generated.

Abstract: A bidirectional device converts a series of data bits partitioned into first group of frames corresponding to a first type of interface into second groups of frames having a second type of interface. The converter first converts signals from a device operating under the first type of interface to standard bilevel digital signals and then converts the standard bilevel digital signals into the second type of interface.

Abstract: The invention is applicable to delta modulation. A method of codifying the bit-stream for more efficient storage and transmission is disclosed. The number of pulses from the a-to-d converter is counted, per batch of B clock beats. The count, or tally value T of the batch, may be issued as an N-bit group, e.g. a 4-bit nibble. The order and spacing of the pulses within the batch is ignored. When the signal is rebuilt, a batch of B clock beats are counted out, T of which are pulses. One value which the nibble can take is reserved and used to indicate a period of silence, by replacing a whole frame of silent nibbles. Both a fixed frame length and a variable frame length are disclosed. For greater sensitivity, the extreme tally values may be utilized to signal a change in the gain or response of the system. A median tally value may be used to cancel the gain change.

Abstract: In a digital communication system, a CMI (Coded Mark Inversion) decoder for extracting an optimum sampling timing from a CMI coded input signal so as to NRZ (Non-Return to Zero) format the input signal. A circuit for producing clock signals which are individually deviated in phase by +1/4 and -1/4 of a period relative to a reference clock signal that is extracted from the input signal is constituted by a logic circuit.

Abstract: Loop Performance Monitoring (LPM) for DDS loops is described. Even though DDS loops have Intentional Bipolar Violations (BPVs), a Loop Coding Violations (LCVs) detection strategy based on further processing of BPVs is described. By monitoring LCVs a local loop terminating device can determine Bit Error Rate (BER).A system is described by which an Office Channel Unit (OCU) can process LCV information to determine signal quality of the signal over the incoming local loop. If the signal quality falls below a certain threshold, the OCU can cut the loop off from the DDS circuit and send control codes into the network.A system is also described where a Network Interface Unit (NIU) with the LPM system communicates incoming LCV information to the OCU using low speed signalling over the simplex path between the transmit and receive pairs. The OCU monitors incoming LCVs as well, and thus has the information necessary to determine bi-directional BER performance.